CN117728551B

CN117728551B - BMS (Battery management System) for realizing parallel connection of master pack and slave pack of battery pack, method and battery pack with BMS

Info

Publication number: CN117728551B
Application number: CN202410174924.7A
Authority: CN
Inventors: 王立敏; 于国强; 吴兴玲; 冉亮; 黄建
Original assignee: Lvjin New Energy Technology Changshu Co ltd
Current assignee: Lvjin New Energy Technology Changshu Co ltd
Priority date: 2024-02-07
Filing date: 2024-02-07
Publication date: 2024-04-26
Anticipated expiration: 2044-02-07
Also published as: CN117728551A

Abstract

The invention discloses a BMS (battery management system) for realizing parallel connection of a master pack and a slave pack of a battery pack, and the BMS comprises a master pack BMS and a slave pack BMS, wherein the master pack BMS comprises a master pack AFE chip and a master pack MCU which are in communication and interconnection, the slave pack BMS comprises a slave pack AFE chip and a slave pack MCU which are in communication and interconnection, and the master pack MCU and the slave pack MCU are in direct communication through a CAN (controller area network) bus, so that the use of a central control chip is reduced, and the manufacturing cost and the failure rate of the battery pack are reduced. The slave packet BMS is independent from the master packet BMS so that the slave packet can seamlessly access and exit the master packet. The AFE module and the MOSFET control switch which are designed on the positive pole loop avoid the problem of communication isolation caused by the fact that a conventional power MOSFET is designed to the power negative pole of the circuit. In addition, after the master and slave packets are connected in parallel, the charge and discharge of the master and slave packets are controlled by controlling the on and off of the MOSFET switch, so that the problem of high-power current reverse filling caused by pressure difference between the master and slave packets is solved.

Description

BMS (Battery management System) for realizing parallel connection of master pack and slave pack of battery pack, method and battery pack with BMS

Technical Field

The invention relates to the technical field of battery management systems, in particular to a BMS (battery management system) for realizing parallel connection of a master pack and a slave pack of a battery pack, a method and the battery pack with the BMS.

Background

Outdoor battery packs, commonly referred to as outdoor mobile power supplies, are more and more common in daily outgoing, and the outdoor mobile power supplies are convenient to carry, and generally have smaller single volume and capacity, so that when the outdoor mobile power supplies power for external equipment continuously, the situation that the system alarm power is low and the load cannot be normally powered often occurs. At this time, it is necessary to access a portable power-up packet (slave packet) to the host (master packet) to continuously satisfy the power supply, and the access of the slave packet does not affect the normal use of the external device. The battery packs in the conventional fixed energy storage equipment are connected in parallel, and the number of preset fixed parallel battery cells is controlled by a general control chip, as described in patent (application number: 202321603113.1, name: a control circuit for parallel charging and discharging of multiple battery packs and multiple parallel battery packs), and the direct plug-in and direct use of the outdoor power supply is particularly important. In addition, the conventional parallel connection also needs to additionally add a current limiter module, a voltage comparison module and a charge-discharge identification loop, so that the addition of components increases the cost and the probability of faults. Therefore, a parallel scheme for realizing direct plug-in and direct use of an outdoor mobile power supply with low cost and high reliability is needed.

In addition, when the master battery pack and the slave battery packs are connected in parallel, when a voltage difference exists, the battery pack with high voltage can charge the battery pack with low voltage. Because the internal resistance of the battery is smaller, when the pressure difference between the master and slave packages is larger, the transient charging current is overlarge, and the high-voltage battery package is extremely easy to damage. Therefore, a BMS with parallel master-slave battery packs is needed to realize safe parallel connection of outdoor mobile power sources, and the problem of high-power current reverse-filling caused by pressure difference between the master-slave battery packs is solved.

Disclosure of Invention

The invention provides a BMS (battery management system) for realizing parallel connection of a master packet and a slave packet of a battery, a method and the battery with the same, wherein an AFE (active power element) module and a MOSFET (metal oxide semiconductor field effect transistor) control switch are arranged on a positive circuit of the master packet and a negative circuit of the master packet, and an MCU (micro control unit) of the master packet and a MCU of the slave packet are communicated directly through a CAN (controller area network) bus, so that the use of a central control chip is reduced; the slave packet BMS is independent from the master packet BMS so that the slave packet can seamlessly access and exit the master packet; after the master and slave packets are connected in parallel, the charge and discharge of the master and slave packets are controlled by controlling the on and off of the MOSFET switch, so that the problem of high-power current reverse filling caused by pressure difference between the master and slave packets is solved.

The technical scheme adopted by the invention is as follows: according to the BMS for realizing the parallel connection of the master pack and the slave pack of the battery pack, the BMS comprises a master pack BMS and a slave pack BMS, wherein the master pack BMS comprises a master pack AFE chip and a master pack MCU which are in communication and interconnection, the BMS further comprises a first NMOS tube and a second NMOS tube which are connected in series with the positive pole of the master pack, and a third NMOS tube, the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the master pack AFE chip, and the grid electrode of the third NMOS tube is connected with the master pack MCU. The secondary package BMS comprises a secondary package AFE chip and a secondary package MCU which are in communication connection, and further comprises a fourth NMOS tube and a fifth NMOS tube which are connected in series with the secondary package anode, drain electrodes of the fourth NMOS tube and the fifth NMOS tube are connected with each other, and a grid electrode of the fourth NMOS tube is connected with the secondary package AFE chip.

As an alternative scheme of the technical scheme of the invention, the master packet MCU is connected with the slave packet MCU through a CAN bus, the slave packet anode is connected with the source electrode of the third NMOS tube, and the slave packet cathode is connected with the master packet cathode.

As an alternative scheme of the technical scheme of the invention, two diodes are connected in parallel at two ends of the source electrode and the drain electrode of the first NMOS tube, the anode of each diode is connected with the source electrode of the first NMOS tube, and the cathode of each diode is connected with the drain electrode of the first NMOS tube; two diodes are connected in parallel at two ends of the source electrode and the drain electrode of the fourth NMOS tube, the anode of each diode is connected with the source electrode of the fourth NMOS tube, and the cathode of each diode is connected with the drain electrode of the fourth NMOS tube.

As an alternative scheme of the technical scheme of the invention, a BOOST circuit is connected between the grid electrodes of the first NMOS tube and the second NMOS tube and the main package AFE chip, a BOOST circuit is connected between the grid electrodes of the third NMOS tube and the main package MCU, and a BOOST circuit is connected between the grid electrodes of the fourth NMOS tube and the fifth NMOS tube and the sub package AFE chip.

As an alternative of the technical solution of the present invention, a method for implementing parallel connection of a master packet and a slave packet of a battery pack according to another embodiment of the present invention includes the following steps:

a) In a discharging mode, when the voltage of the master packet is larger than that of the slave packet, the master packet BMS starts the first NMOS tube, the second NMOS tube and the third NMOS tube, the slave packet BMS closes the fourth NMOS tube and starts the fifth NMOS tube until the slave packet AFE chip detects the discharging current, and the fourth NMOS tube is started; when the voltage of the master packet is smaller than that of the slave packet, the master packet BMS turns off the first NMOS tube, turns on the second NMOS tube and the third NMOS tube, turns on the fourth NMOS tube and the fifth NMOS tube from the slave packet until the master packet AFE chip detects discharge current, and turns on the first NMOS tube; when the master packet voltage is equal to the slave packet voltage, the master packet BMS starts the first NMOS tube, the second NMOS tube and the third NMOS tube, and the slave packet BMS starts the fourth NMOS tube and the fifth NMOS tube;

b) In a charging mode, when the voltage of the master packet is larger than that of the slave packet, the master packet BMS turns off the first NMOS tube and the second NMOS tube, turns on the third NMOS tube, and the slave packet BMS turns on the fourth NMOS tube and the fifth NMOS tube until the master packet AFE chip detects that charging is converted into the master packet, and turns on the first NMOS tube and the second NMOS tube; when the voltage of the master packet is smaller than that of the slave packet, the master packet BMS starts the first NMOS tube, the second NMOS tube and the third NMOS tube, the slave packet BMS closes the fourth NMOS tube and the fifth NMOS tube until the slave packet AFE chip detects that charging is commutated to the slave packet, and the fourth NMOS tube and the fifth NMOS tube are opened; when the master packet voltage is equal to the slave packet voltage, the master packet BMS starts the first NMOS tube, the second NMOS tube and the third NMOS tube, and the slave packet BMS starts the fourth NMOS tube and the fifth NMOS tube;

c) In the idle mode, when the voltage of the master packet is not equal to the voltage of the slave packet, the master packet BMS starts the first NMOS tube, the second NMOS tube and the third NMOS tube, and the slave packet BMS closes the fourth NMOS tube and the fifth NMOS tube; when the master packet voltage is equal to the slave packet voltage, the master packet BMS starts the first NMOS tube, the second NMOS tube and the third NMOS tube, and the slave packet BMS starts the fourth NMOS tube and the fifth NMOS tube;

d) In the exit mode, the master pack BMS turns on the first NMOS tube and the second NMOS tube, turns off the third NMOS tube, and the slave pack BMS turns off the fourth NMOS tube and the fifth NMOS tube.

As an alternative of the technical solution of the present invention, in the step a), when the voltages of the master packet and the slave packet are equal, the master packet BMS turns on the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor, and the slave packet BMS turns on the fourth NMOS transistor and the fifth NMOS transistor, and continuously discharges until the SOC of the master packet and the slave packet is 0% or a preset value.

As an alternative of the technical solution of the present invention, in the step b), when the voltages of the master packet and the slave packet are equal, the master packet BMS turns on the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor, and the slave packet BMS turns on the fourth NMOS transistor and the fifth NMOS transistor, and continuously charges until the SOC of the master packet and the slave packet is 100% or a preset value.

As an alternative scheme of the technical scheme of the invention, a battery pack for realizing the parallel connection of a master pack and a slave pack of the battery pack according to another embodiment of the invention comprises a master pack cell and a slave pack cell which are connected in parallel, and the battery pack for realizing the parallel connection of the master pack and the slave pack of the battery pack, wherein the master pack cell is connected with the master pack BMS, the positive electrode and the negative electrode of the master pack cell are connected with a master pack AFE chip, the slave pack cell is connected with a slave pack BMS, the positive electrode and the negative electrode of the slave pack cell are connected with the slave pack AFE chip, and the positive electrode and the negative electrode of the master pack are connected with a bidirectional inverter.

As an alternative scheme of the technical scheme of the invention, a first fuse is connected in series with the positive electrode of the main package battery core, a first current detection resistor is connected in series with the negative electrode of the main package battery core, the first fuse is controlled to be fused by the main package MCU, and two ends of the first current detection resistor are connected with the main package AFE chip; the secondary battery cell positive electrode is connected with a second fuse in series, the negative electrode is connected with a second current detection resistor in series, the second fuse is fused under the control of the secondary battery cell MCU, and two ends of the second current detection resistor are connected to the secondary battery cell AFE chip.

As an alternative scheme of the technical scheme of the invention, the battery pack further comprises a master pack photoelectric coupler and a slave pack photoelectric coupler which are connected in series, wherein the master pack photoelectric coupler is connected with the master pack MCU, and the slave pack photoelectric coupler is connected with the slave pack MCU.

The beneficial effects obtained by the invention are as follows: according to the BMS, the method for realizing the parallel connection of the master and slave battery packs and the battery pack with the same, the AFE module and the MOSFET control switch are arranged on the positive circuit of the master and slave battery packs, and the master and slave battery packs MCU directly communicate through the CAN bus, so that the use of a central control chip is reduced. The slave packet BMS is independent from the master packet BMS so that the slave packet can seamlessly access and exit the master packet. After the master-slave package is connected in parallel, the charge and discharge of the master-slave package are controlled by controlling the on and off of the MOSFET switch, so that the problem of high-power current reverse filling caused by pressure difference between the master-slave package is effectively solved, and the conditions of overheat and even burning of the package with high voltage are avoided. Besides, the AFE module and the MOSFET control switch are designed on the positive pole loop, so that the problem of communication isolation caused by the fact that a conventional power MOSFET is designed to a circuit power negative pole is avoided; the current limiter module, the voltage comparison module and the charge-discharge identification loop are reduced, and the manufacturing cost and the failure rate of the battery pack are reduced.

The effects of the present invention are not limited to the above-described effects, and those skilled in the art can obtain effects not described above from the following description.

Drawings

Fig. 1 is a circuit diagram of a BMS implementing a master-slave packet parallel connection of a battery pack according to an embodiment of the present invention.

Fig. 2 is a list of operating modes for turning on and off MOSFETs implementing a battery pack master-slave pack parallel method according to an embodiment of the present invention.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects solved by the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the following specific examples are intended to illustrate the invention and are not intended to limit the invention. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are based on the following examples, which fall within the scope of the invention.

It should be noted that, in the description of the present invention, the positional or positional relationship indicated by the terms such as "upper", "lower", "left", "right", "front", "rear", etc. are based on the positional or positional relationship of the drawings, and are merely for convenience of description of the present invention, and are not indicative or implying that the apparatus or element in question must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the present invention. In the description of the embodiments, the terms "disposed," "connected," and the like are to be construed broadly unless otherwise specifically indicated and defined. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.

Example 1

As shown in fig. 1, according to the BMS circuit diagram for implementing the parallel connection of the master and slave packets of the battery pack according to the embodiment of the invention, a master packet 001 is arranged above, a master packet cell is arranged in the master packet, a slave packet 002 is arranged below, and a slave packet cell is arranged in the slave packet, wherein the master packet 001 and the slave packet 002 are connected in parallel. Be provided with main package BMS in the main package 001, including main package AFE chip and main package MCU, through cable interconnection communication between main package AFE chip and the main package MCU. The main package BMS still includes first NMOS pipe C1, second NMOS pipe D1 and third NMOS pipe P1, and wherein first NMOS pipe C1 and second NMOS pipe D1 drain electrode concatenate behind the interconnect in main package 001 positive pole, and first NMOS pipe C1 is located and is close to main package electric core end, and first NMOS pipe C1 and second NMOS pipe D1 grid establish ties BOOST BOOST circuit respectively and connect main package AFE chip afterwards. The drain electrode of the third NMOS tube P1 is connected with the positive electrode of the main package 001, namely the source electrode of the second NMOS tube D1, and the grid electrode is connected with the BOOST circuit in series and then is connected with the main package MCU. The slave pack 002 is internally provided with a slave pack BMS which comprises a slave pack AFE chip and a slave pack MCU, wherein the slave pack AFE chip and the slave pack MCU are communicated through a cable interconnection. The secondary package BMS further comprises a fourth NMOS tube C2 and a fifth NMOS tube D2, drain electrodes of the fourth NMOS tube C2 and the fifth NMOS tube D2 are connected in series with the positive electrode of the secondary package 002 after being connected with each other, the fourth NMOS tube C2 is close to a secondary package battery core end, a source electrode of the fifth NMOS tube D2 is connected with a source electrode of the third NMOS tube P1, and grid electrodes of the fourth NMOS tube C2 and the fifth NMOS tube D2 are respectively connected with a BOOST circuit in series and then are connected with a secondary package AFE chip.

The main package BMS also comprises two diodes connected in parallel with the source electrode and the drain electrode of the first NMOS tube C1, wherein the anode of each diode is connected with the source electrode of the first NMOS tube C1, and the cathode of each diode is connected with the drain electrode of the first NMOS tube C1. The parallel diode in the main package is used for preventing the first NMOS tube C1 from being burnt out when the main package voltage is lower than the slave package voltage in the discharging mode. The secondary package BMS also comprises two diodes connected in parallel with the source electrode and the drain electrode of the fourth NMOS tube C2, wherein the anode of each diode is connected with the source electrode of the fourth NMOS tube C2, and the cathode of each diode is connected with the drain electrode of the fourth NMOS tube C2. The parallel diode in the slave package is used to prevent the fourth NMOS transistor C2 from being burned out when the master package voltage is higher than the slave package voltage in the discharge mode. In addition, since the first NMOS tube C1 to the fifth NMOS tube D2 are connected to the high side, and the on-board voltages of the master-slave package AFE chip and the master-package MCU are small, the gate voltage is insufficient to control the turn-on of the first NMOS tube C1 to the fifth NMOS tube D2, and therefore, the BOOST circuits are all required to be connected in series.

Example two

The method for implementing the parallel connection of the master and slave battery packs by using the BMS according to the first embodiment relates to BMS operation logic in four modes of discharging, charging, idle and exiting, as shown in fig. 2, and a specific method is as follows.

In the discharging mode, when the master packet voltage is greater than the slave packet voltage, the slave packets need to continue to be responsible for discharging after being connected in parallel, and the slave packets do not discharge until the master packet voltage falls to be equal to the slave packet voltage. Therefore, after the secondary packets are connected in parallel, the master packet BMS starts the first NMOS tube C1, the second NMOS tube D1 and the third NMOS tube P1, the secondary packet BMS closes the fourth NMOS tube C2 and starts the fifth NMOS tube D2, and the fourth NMOS tube C2 body diode is matched with the opened fifth NMOS tube D2, so that the secondary packet can only discharge and cannot be reversely charged by the master packet. When the voltage of the master packet is equal to that of the slave packet, the slave packet needs to start discharging, the slave packet AFE chip detects the discharging current, the fourth NMOS tube C2 is started, and the master and slave packets continue discharging until the SOC of the battery packet is 0% or a preset value.

In the discharging mode, when the master packet voltage is smaller than the slave packet voltage, the slave packets need to start to take charge of discharging after being connected in parallel, and the master packet stops discharging until the slave packet voltage is reduced to be equal to the master packet voltage. Therefore, when the secondary packets are connected in parallel, the master packet BMS closes the first NMOS tube C1, opens the second NMOS tube D1 and the third NMOS tube P1, opens the secondary packets into the fourth NMOS tube C2 and the fifth NMOS tube D2, and the first NMOS tube C1 body diode is matched with the opened second NMOS tube D1, so that the master packet can only discharge and cannot be reversely charged by the secondary packets. When the voltage of the slave packet is equal to the voltage of the master packet, the master packet needs to start discharging, the master packet AFE chip detects the discharging current, the first NMOS tube C1 is started, and the master and slave packets are continuously discharged together until the SOC of the battery packet is 0% or a preset value.

In the discharging mode, when the voltage of the master pack is equal to that of the slave pack, the master pack and the slave pack are required to be discharged together after the slave pack is connected in parallel, so that when the slave pack is connected in parallel, the master pack BMS starts the first NMOS tube C1, the second NMOS tube D1 and the third NMOS tube P1, the slave pack BMS starts the fourth NMOS tube C2 and the fifth NMOS tube D2, and the master pack and the slave pack are continuously discharged together until the SOC of the battery pack is 0% or a preset value.

Preferably, for prolonging the service life of the battery, the master pack BMS and the slave pack BMS are both provided with an SOC threshold value 1 and an SOC threshold value 2, when the master pack BMS discharges to the SOC threshold value 1, the BMS alarms, and when the master pack BMS discharges to the SOC threshold value 2, the master pack BMS closes the first NMOS tube C1, the second NMOS tube D1 and the third NMOS tube P1, and the slave pack BMS closes the fourth NMOS tube C2 and the fifth NMOS tube D2.

In the charging mode, when the master packet voltage is greater than the slave packet voltage, the slave packets need to stop charging after being connected in parallel and the slave packets start charging until the slave packet voltage is equal to the master packet voltage. Therefore, when the slave package is connected in parallel, the master package BMS closes the first NMOS tube C1 and the second NMOS tube D1, opens the third NMOS tube P1, and the slave package BMS opens the fourth NMOS tube C2 and the fifth NMOS tube D2, and the first NMOS tube C1 and the second NMOS tube D1 are closed, so that the master package is prevented from reversely filling the slave package. When the secondary package voltage is equal to the primary package voltage, the primary package needs to start charging, the primary package AFE chip detects that charging is converted into the primary package, the first NMOS tube C1 and the second NMOS tube D1 are started, and the primary package and the secondary package are continuously charged together until the SOC of the battery package is 100% or a preset value.

In the charging mode, when the master packet voltage is smaller than the slave packet voltage, the slave packets are required to be charged continuously after being connected in parallel, and the slave packets stop charging until the master packet voltage is equal to the slave packet voltage. Therefore, when the slave package is connected in parallel, the master package BMS turns on the first NMOS tube C1, the second NMOS tube D1 and the third NMOS tube P1, the slave package BMS turns off the fourth NMOS tube C2 and the fifth NMOS tube D2, and the fourth NMOS tube C2 and the fifth NMOS tube D2 are turned off to prevent the slave package from reversely filling the master package. When the voltage of the master packet is equal to that of the slave packet, the slave packet needs to start charging, the slave packet AFE chip detects that charging is commutated to the slave packet, the fourth NMOS tube C2 and the fifth NMOS tube D2 are started, and the master and slave packets are continuously charged together until the SOC of the battery packet is 100% or a preset value.

In the charging mode, when the voltage of the master pack is equal to that of the slave pack, the master pack and the slave pack are required to be charged together after the slave pack is connected in parallel, so when the slave pack is connected in parallel, the master pack BMS starts the first NMOS tube C1, the second NMOS tube D1 and the third NMOS tube P1, the slave pack BMS starts the fourth NMOS tube C2 and the fifth NMOS tube D2, and the master pack and the slave pack are continuously charged together until the SOC of the battery pack is 100% or a preset value.

In the idle mode, when the voltage of the master packet is not equal to that of the slave packet, the slave packet needs to be in a state of to-be-charged and discharged after the slave packet is connected in parallel and the slave packet is in a disconnected state, so when the slave packet is connected in parallel, the master packet BMS starts the first NMOS tube C1, the second NMOS tube D1 and the third NMOS tube P1, the slave packet BMS closes the fourth NMOS tube C2 and the fifth NMOS tube D2, and when the load is accessed into the load or the power supply is accessed into the charging state, the slave packet is switched into a discharging mode and a charging mode in corresponding states.

In the idle mode, when the voltage of the master packet is equal to that of the slave packet, no mutual charging occurs between the master packet and the slave packet after the slave packet is connected in parallel, and the master packet BMS is in a state to be charged and discharged, so that when the slave packet is connected in parallel, the master packet BMS starts the first NMOS tube C1, the second NMOS tube D1 and the third NMOS tube P1, the slave packet BMS starts the fourth NMOS tube C2 and the fifth NMOS tube D2, and when the master packet is connected into a load to enter a discharging state or is connected into a power supply to enter a charging state, the master packet is switched into a discharging mode and a charging mode in corresponding states.

In the exit mode, the main package is only charged and discharged, and the secondary package is disconnected and exits, so that the main package BMS opens the first NMOS tube C1 and the second NMOS tube D1, closes the third NMOS tube P1, and closes the fourth NMOS tube C2 and the fifth NMOS tube D2.

In the method for realizing the parallel connection of the master and slave packets of the battery, the voltages of the master and slave packets are equal to each other in a theoretical state, a master and slave packet differential pressure threshold is set in reality, and when the master and slave packet differential pressure is within the set threshold range, the master and slave packet voltages are equal.

Example III

A battery pack with a parallel master-slave pack is achieved by the BMS according to the first embodiment, as shown in fig. 1, the battery pack comprises a master pack 001 and a slave pack 002 which are connected in parallel, a master pack battery core is arranged in the master pack 001, the master pack battery core is connected with the master pack BMS, the positive electrode and the negative electrode of the master pack battery core are connected with a master pack AFE chip, the positive electrode of the master pack battery core is connected with a first FUSE FUSE-1 in series, the first FUSE FUSE-1 is connected with a master pack MCU, and the master pack MCU controls the first FUSE FUSE-1 to FUSE so as to effectively avoid abnormality caused by overvoltage, overcurrent and overtemperature. The negative electrode of the main package battery cell is connected in series with a first current detection resistor R-sense-1, and two ends of the first current detection resistor R-sense-1 are connected to the main package AFE chip and used for monitoring the current of the main package battery cell. The secondary battery cell is arranged in the secondary battery pack 002, the secondary battery cell is connected with the secondary battery pack BMS, the positive electrode and the negative electrode of the secondary battery cell are connected with the secondary battery pack AFE chip, the positive electrode of the secondary battery cell is connected with the second FUSE FUSE-2 in series, the second FUSE FUSE-2 is connected with the secondary battery pack MCU, and the secondary battery pack MCU controls the fusing of the second FUSE FUSE-2 to effectively avoid the abnormality caused by overvoltage, overcurrent and overtemperature. The secondary battery cell negative electrode is connected with a second current detection resistor R-sense-2 in series, and two ends of the second current detection resistor R-sense-2 are connected with a secondary battery cell AFE chip for monitoring the current of the secondary battery cell.

In addition, the master packet MCU and the slave packet MCU are in communication connection through the CAN bus, the anode of the slave packet 002 is connected with the source electrode of the third NMOS tube P1, and the connection and disconnection of the slave packet 002 and the master packet 001 are controlled by opening and closing the third NMOS tube P1. The main package MCU and the slave package MCU are also connected in series with a main package photoelectric coupler and a slave package photoelectric coupler, the main package photoelectric coupler is connected with the main package MCU, the slave package photoelectric coupler is connected with the slave package MCU, and when the main package or the slave package is in a shutdown mode, the battery package can be started in a soft mode through controlling the photoelectric coupler. The positive and negative poles of the main bag 001 are also provided with a bidirectional inverter for externally connecting a load and a charging power supply.

In summary, according to the BMS, the method and the battery pack with the battery pack, which are used for realizing the parallel connection of the master and slave packs, provided by the invention, the AFE module and the MOSFET control switch are arranged on the positive circuit of the master and slave packs, the master and slave packs MCU are in communication connection through the CAN bus, and the charge and discharge of the master and slave packs are controlled by controlling the on and off of the MOSFET switch after the master and slave packs are connected in parallel. The invention can bring beneficial effects including but not limited to the following:

(1) The slave packet BMS is independent of the master packet BMS, so that the slave packet can be seamlessly accessed and exited from the master packet without affecting the normal operation of external equipment or a power supply;

(2) The master-slave packet MCU directly communicates through the CAN bus, so that a central control chip, a current limiter module, a voltage comparison module and a charge-discharge identification loop are reduced, and the manufacturing cost and the failure rate of the battery packet are reduced;

(3) The charge and discharge of the master-slave package are controlled by controlling the on and off of the MOSFET switch, so that the problem of high-power current reverse filling caused by pressure difference between the master-slave package is effectively solved, and the situation that the package with high voltage is overheated or even burnt is avoided;

(4) Setting an SOC threshold value, and complementing the phenomenon that the service life of the battery pack is influenced due to continuous discharge at the discharge end of the battery pack in the differential pressure logic;

(5) The AFE module and the MOSFET control switch are designed on the positive pole loop, so that the problem of communication isolation caused by the fact that a conventional power MOSFET is designed to a circuit power negative pole is avoided;

(6) When the parallel mode exits, the situation of avoiding the electric shock of a user is achieved by closing the secondary package MOSFET control switch;

(7) When the master pack or the slave pack is in a shutdown mode, soft start of the battery pack can be achieved by controlling the photoelectric coupler.

The effects of the present invention are not limited to the effects listed above, and those skilled in the art can derive effects not described above from the description.

The above-described embodiments of the BMS, the method for implementing the master-slave pack parallel connection of the battery packs and the battery packs having the same are only illustrative of the preferred embodiments, and are not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principles of the present invention should be included in the scope of the present invention. In addition, the technical solutions between the embodiments may be combined with each other, but must be based on the implementation by those of ordinary skill in the art; when the combination of the technical solutions is contradictory or impossible to realize, it should be considered that the combination of the technical solutions does not exist and is not within the scope of protection claimed by the present invention.

Claims

1. A method for implementing a master-slave packet parallel connection of battery packs, comprising a BMS used, the BMS comprising:

The main package BMS comprises a main package AFE chip and a main package MCU which are in communication and interconnection, and further comprises a first NMOS tube and a second NMOS tube which are connected in series with the positive electrode of the main package, and a third NMOS tube, wherein the drain electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube, the grid electrode of the first NMOS tube is connected with the main package AFE chip, and the grid electrode of the third NMOS tube is connected with the main package MCU;

The secondary package BMS comprises a secondary package AFE chip and a secondary package MCU which are in communication and interconnection, and further comprises a fourth NMOS tube and a fifth NMOS tube which are connected in series with the positive electrode of the secondary package, wherein the drains of the fourth NMOS tube and the fifth NMOS tube are connected with each other, and the grid is connected with the secondary package AFE chip;

The method comprises the following steps:

2. The method for realizing the parallel connection of the master and slave packets of the battery pack according to claim 1, wherein in the BMS, the master packet MCU is connected with the slave packet MCU through a CAN bus, the slave packet positive electrode is connected with a third NMOS tube source electrode, and the slave packet negative electrode is connected with a master packet negative electrode.

3. The method for realizing the master-slave packet parallel connection of the battery pack according to claim 1, wherein two diodes are connected in parallel to two ends of a source electrode and a drain electrode of the first NMOS tube in the BMS, the anode of each diode is connected with the source electrode of the first NMOS tube, and the cathode of each diode is connected with the drain electrode of the first NMOS tube; two diodes are connected in parallel at two ends of the source electrode and the drain electrode of the fourth NMOS tube, the anode of each diode is connected with the source electrode of the fourth NMOS tube, and the cathode of each diode is connected with the drain electrode of the fourth NMOS tube.

4. The method for implementing the master-slave packet parallel connection of the battery pack according to claim 1, wherein a BOOST circuit is connected between the gates of the first NMOS transistor and the second NMOS transistor and the master-pack AFE chip, a BOOST circuit is connected between the gate of the third NMOS transistor and the master-pack MCU, and a BOOST circuit is connected between the gates of the fourth NMOS transistor and the fifth NMOS transistor and the slave-pack AFE chip.

5. The method for realizing the parallel connection of the master and the slave of the battery pack according to claim 1, wherein in the step a), when the voltages of the master pack and the slave pack are equal, the master pack BMS turns on the first NMOS tube, the second NMOS tube and the third NMOS tube, the slave pack BMS turns on the fourth NMOS tube and the fifth NMOS tube, and the discharge is continued until the SOC of the master pack and the slave pack is 0% or a preset value.

6. The method for realizing the parallel connection of the master and the slave of the battery pack according to claim 1, wherein in the step b), when the voltages of the master pack and the slave pack are equal, the master pack BMS turns on the first NMOS tube, the second NMOS tube and the third NMOS tube, the slave pack BMS turns on the fourth NMOS tube and the fifth NMOS tube, and the master pack and the slave pack are continuously charged until the SOC is 100% or a preset value.