CN117727356B - Method for repairing memory chip based on test equipment - Google Patents
Method for repairing memory chip based on test equipment Download PDFInfo
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- CN117727356B CN117727356B CN202410179287.2A CN202410179287A CN117727356B CN 117727356 B CN117727356 B CN 117727356B CN 202410179287 A CN202410179287 A CN 202410179287A CN 117727356 B CN117727356 B CN 117727356B
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- 238000012360 testing method Methods 0.000 title claims abstract description 48
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000008439 repair process Effects 0.000 claims abstract description 36
- 238000003860 storage Methods 0.000 claims abstract description 28
- 238000009826 distribution Methods 0.000 claims description 4
- 238000012216 screening Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 description 11
- 238000004458 analytical method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000007781 pre-processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a method for repairing a memory chip based on test equipment, which belongs to the technical field of chip test and specifically comprises the following steps: acquiring failure unit circuit information in a memory chip; taking the block number as a storage key value and the circuit coordinate of the failure unit as a storage value to construct an X-Y hash table structure and a Y-X hash table structure; traversing the hash table, if a failure unit circuit set exceeding a preset threshold exists, designating the set as a specific failure unit circuit, and distributing a specific type of standby circuit to repair the area; if no standby circuit is available, marking and deleting the memory chip; if no invalid unit circuit set exceeding a preset threshold exists, the set is called a sparse invalid unit circuit, a maximum set value is obtained, a standby circuit is allocated, and if no standby circuit is available, the memory chip is marked and deleted; if a standby circuit is available, normal repair is performed; the invention improves the repair utilization rate of the failure unit circuit.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a method for repairing a memory chip based on testing equipment.
Background
Memory chip testing is primarily directed to memory, including random access memory, flash memory, etc., semiconductor devices used to store and read data or program code. The contents of the test include some performance parameters such as read time, write recovery time, data save time, etc. The purpose of these tests is to ensure that the memory reliably and accurately stores and reads data under a variety of conditions.
Compared with the test of the system-level chip, the memory chip has an extra repairing flow, the tester acquires the failed circuit information of each chip according to the test requirement to form a log file of a failed unit circuit, a repairing analysis program of the tester loads the log file to generate a repairing scheme, a standby circuit is used for repairing the damaged circuit, and if the number of the standby circuits on each chip cannot repair the damaged circuit area on the chip, the chip is removed and does not enter the subsequent flow.
The repair distribution algorithm of the processing failure unit circuit of the testing machine can influence the yield of the storage chip in the testing and packaging process, the optimal repair scheme can maximize the production economic value of the chip, but because the failure information of the chip repair is complex, the solution distributed by the program can only reach a relatively better solution, the existing repair method is generally distributed directly according to the failure unit circuit information, the correlation among the failure unit circuits is not analyzed, and the distributed repair scheme is a non-optimal solution.
Disclosure of Invention
The invention aims to provide a method for repairing a memory chip based on test equipment, which solves the following technical problems:
because the failure information of the chip repair is complex, the solution of program allocation can only reach a relatively better solution, the existing repair method is generally directly allocated according to the failure unit circuit information, the correlation between the failure unit circuits is not analyzed, and the allocated repair scheme is a non-optimal solution.
The aim of the invention can be achieved by the following technical scheme:
a method for repairing a memory chip based on test equipment comprises the following steps:
The test equipment is connected with the memory chip for testing, the memory chip is divided into a plurality of blocks and numbered, and failure unit circuit information in the memory chip is extracted from the binary test log;
Counting the number of the invalid unit circuits under different blocks, taking the number of any block as a storage key value, taking the number of the invalid unit circuits of the block and the coordinate information (X, Y) of the invalid unit circuits as storage values, and storing all the information of the invalid unit circuits into a hash table data structure;
In any block, taking any X address bit as a key value and a corresponding set of Y address bits as a storage value to obtain an X-Y hash table structure; taking any Y address bit as a key value and a corresponding X address bit set as a storage value to obtain a Y-X hash table structure;
Traversing the X-Y hash table structure and the Y-X hash table structure respectively to obtain a Y address bit set Gx corresponding to any X address bit and an X address bit set Gy corresponding to any Y address bit, and if the numerical value of the set Gx is larger than the maximum number of the column standby circuits for repairing the column direction, randomly distributing a group of row standby circuits for repairing; if the value of the set Gy is larger than the maximum failure unit circuit number of the row standby circuit for repairing the row direction; then a set of column standby circuit repairs are arbitrarily allocated; if no row/column standby circuit can be allocated, marking and deleting the memory chip, updating the hash table structure and stopping traversing; if the row/column standby circuit can be allocated, updating the X-Y and Y-X hash table structures, and deleting the repaired failure unit circuit address information;
Comparing the deleted X-Y and Y-X hash table structures, acquiring the maximum aggregate value M according to the aggregate size of the storage values corresponding to each key value, if M corresponds to an X address bit coordinate, distributing row standby circuits, if M corresponds to a Y address bit coordinate, distributing column standby circuits, and if no standby circuit can be used, marking the storage chip and deleting; if the standby circuit is available, the service condition of the standby circuit is recorded, the X-Y and Y-X hash table structures are updated, the repaired failure unit circuit address information is deleted until the data values in the X-Y and Y-X hash table structures are empty, and the traversal is stopped, so that the memory chip can be repaired normally.
As a further scheme of the invention: the process of collecting the circuit information of the failure unit is as follows:
The method comprises the steps of collecting initial failure unit circuit information of a storage chip through test equipment and recording the initial failure unit circuit information into a memory medium, and obtaining configuration information of the storage chip and coding specifications of the test equipment, wherein the configuration information comprises the number of blocks, the address bit information of the failure unit circuit, the number and distribution of standby circuits, the failure unit circuit information is extracted from the memory medium, and the failure unit circuit information comprises failure unit circuit block numbers, failure unit circuit coordinate information (X, Y) and input-output line numbers.
As a further scheme of the invention: the standby circuit comprises a column standby circuit and a row standby circuit, wherein the column standby circuit is used for repairing a failure unit circuit in the column direction in the memory chip, and the row standby circuit is used for repairing a failure unit circuit in the row direction in the memory chip.
As a further scheme of the invention: obtaining the maximum number Ti of the standby repair circuit units and the number Fi of the failure unit circuits of each block in the memory chip, wherein i represents the block number, if Fi is larger than Ti, the memory chip cannot be repaired, the memory chip is marked, and the failure unit circuit information of the memory chip is deleted from the hash table data structure.
As a further scheme of the invention: the specific process of traversing is as follows:
Traversing the X-Y hash table structure to obtain a Y address bit set Gx corresponding to the X address bits, wherein V Gx is expressed as the numerical value of the set Gx, and if V Gx＞Colmax,Colmax is expressed as the maximum failure unit circuit number in the column direction, the column standby circuit can be repaired; setting the X address bit as a specific failure unit circuit of a row standby circuit, arbitrarily distributing a group of row standby circuits for repairing, marking and deleting the memory chip if no row standby circuit is available, and updating the hash table structure; if available line standby circuits exist, updating the X-Y and Y-X hash table structures, and deleting the repaired address information of the failure unit circuit;
Traversing the Y-X hash table structure to obtain an X address bit set Gy corresponding to the Y address bits, wherein V Gy is expressed as a numerical value of the set Gy, and if V Gy＞Rowmax,Rowmax is expressed as the maximum number of invalid unit circuits in the row direction, the row standby circuit can repair; setting the Y address bit to a column spare circuit specific fail cell circuit; optionally allocating a group of column standby circuits for repairing, if no column standby circuits are available, marking and deleting the memory chip, and updating the hash table structure; if there is a column redundancy circuit available, the X-Y and Y-X hash table structures are updated and the repaired failed cell circuit address information is deleted.
As a further scheme of the invention: the specific process of comparison is as follows:
Marking the rest of deleted invalid unit circuits as sparse invalid unit circuits, acquiring the maximum set of values max-X, max-x=max (hash-table (X-Y)) in all the X-Y hash tables at the moment, and recording the corresponding X value at the moment; and obtaining the numerical value max-Y of the maximum set in all Y-X hash tables, recording the Y value corresponding to the numerical value max-y=max (hash-table (Y-X)), screening the value of the maximum set in the two hash tables as M, wherein M=max { max-x|max-Y }.
As a further scheme of the invention: if max-x=max-y, the maximum set value stored in the two hash tables is equal, and max-y is determined as M output.
As a further scheme of the invention: when the test information of all the memory chips is traversed, outputting the normal repairable memory chip information, and eliminating the memory chip information which cannot be repaired.
The invention has the beneficial effects that:
The present invention classifies failed cell circuits into two types: the method comprises the steps of pre-processing a specific repair failure unit circuit area in a failure area of a specific repair type and a sparse repair type; and then, a greedy strategy in the heuristic strategy is fused into the generation of a chip repair scheme, the correlation between sparse failure unit circuits is analyzed, the repair utilization rate of the row and column standby circuits is improved, and the yield of the memory chip in test repair can be effectively improved.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic flow chart of the present invention;
FIG. 2 is a diagram illustrating a failure cell circuit of a single block of a memory chip according to the present invention;
FIG. 3 is an exemplary diagram of a column alternate circuit repair area of the present invention;
fig. 4 is an exemplary diagram of a row redundancy circuit repair area of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-4, a method for repairing a memory chip based on a test device includes the following steps:
The test equipment is connected with the memory chip for testing, the memory chip is divided into a plurality of blocks and numbered, and failure unit circuit information in the memory chip is extracted from the binary test log;
Counting the number of the invalid unit circuits under different blocks, taking the number of any block as a storage key value, taking the number of the invalid unit circuits of the block and the coordinate information (X, Y) of the invalid unit circuits as storage values, and storing all the information of the invalid unit circuits into a hash table data structure;
In any block, taking any X address bit as a key value and a corresponding set of Y address bits as a storage value to obtain an X-Y hash table structure; taking any Y address bit as a key value and a corresponding X address bit set as a storage value to obtain a Y-X hash table structure;
Traversing the X-Y hash table structure and the Y-X hash table structure respectively to obtain a Y address bit set Gx corresponding to any X address bit and an X address bit set Gy corresponding to any Y address bit, and if the numerical value of the set Gx is larger than the maximum number of the column standby circuits for repairing the column direction, randomly distributing a group of row standby circuits for repairing; if the value of the set Gy is larger than the maximum failure unit circuit number of the row standby circuit for repairing the row direction; then a set of column standby circuit repairs are arbitrarily allocated; if no row/column standby circuit can be allocated, marking and deleting the memory chip, updating the hash table structure and stopping traversing; if the row/column standby circuit can be allocated, updating the X-Y and Y-X hash table structures, and deleting the repaired failure unit circuit address information;
Comparing the deleted X-Y and Y-X hash table structures, acquiring the maximum aggregate value M according to the aggregate size of the storage values corresponding to each key value, if M corresponds to an X address bit coordinate, distributing row standby circuits, if M corresponds to a Y address bit coordinate, distributing column standby circuits, and if no standby circuit can be used, marking the storage chip and deleting; if the standby circuit is available, the service condition of the standby circuit is recorded, the X-Y and Y-X hash table structures are updated, the repaired failure unit circuit address information is deleted until the data values in the X-Y and Y-X hash table structures are empty, and the traversal is stopped, so that the memory chip can be repaired normally.
The existing scheme is directly distributed according to the information of the failure unit circuits, the method is high in running speed, correlation among the failure unit circuits is not analyzed, and the distributed repairing scheme is a non-optimal solution.
The testing steps of the invention are as follows:
Preparing a chip test program, and acquiring chip failure information (binary) by an execution program;
extracting failure information of a chip from binary test log data, wherein the failure information comprises a memory chip block number and address information of a failure unit;
storing the extracted failure information into a hash table structure according to the block numbers;
Analyzing the failure information of the chip in the last step, traversing according to the chip structure, and stopping analyzing if the number of failure units of the block number is greater than the number of units which can be repaired by the block, wherein the block cannot be repaired; otherwise, the next step is carried out;
Obtaining a specific row and column repair area according to the X-Y, Y-X, and distributing corresponding types of circuits for repair; if the standby circuit is used enough, normally distributing a repair scheme, otherwise, stopping analysis, wherein the block cannot be repaired;
And (3) processing a sparse failure unit circuit, analyzing coordinates corresponding to the maximum value of the corresponding set sizes in the X-Y and Y-X hash tables as a repair value, and distributing a standby circuit, wherein if the standby circuit is used, but a failure unit still exists, the analysis is stopped, and the block cannot be repaired.
In another preferred embodiment of the present invention, the process of collecting the failure unit circuit information is:
the specific process for collecting the circuit information of the failure unit is as follows:
Step 1, setting different types of test items, preparing a memory chip test program, connecting test equipment with crystal grains or chips to call the test program, testing the chips according to the test items (performance parameters), and recording failure circuit information of each crystal grain or chip into a memory medium (binary coding format) by the test equipment;
step 2, acquiring failure circuit information (binary coding format) from a memory by a program of test equipment, and extracting coordinate information (X, Y information), block number (bank information) and input-output line number (IO number) of crystal grains or chip failure information from binary data according to configuration information (different specifications, different configuration information including block number, X, Y address bit information, number and distribution of standby circuits) of different memory chip products and coding specifications of the test equipment;
step 3, counting the number of the failure circuits under different blocks according to the number of the blocks as a storage key value, wherein the number of the failure circuits and address (X, Y address bit information) information in the number of the blocks are used as storage values, and storing all the failure circuit information into a hash table data structure;
Step 4, analyzing the data structure obtained in the step 3, comparing the maximum number Ti of the standby circuit repair circuit units in each block in each crystal grain or chip with the measured quantity Fi of the failure circuit units, wherein i represents the block number, and each product is different and generally has the value range of i E (1, 8]; if Fi is greater than Ti, the crystal grain or chip cannot be repaired, marking and rejecting the crystal grain or chip, skipping from the analysis and solution process, and deleting the failure circuit information of the crystal grain or chip from the hash table;
and step 5, after the processing in the step 4, the storage chip failure information processing method based on the test equipment finishes the preprocessing flow of generating failure information for the test.
In another preferred embodiment of the present invention, the standby circuit includes a column standby circuit for repairing a column-direction fail cell circuit in the memory chip and a row standby circuit for repairing a row-direction fail cell circuit in the memory chip.
In another preferred embodiment of the present invention, the maximum number Ti of spare repair circuit units and the number Fi of failed unit circuits of each block in the memory chip are obtained, i represents the block number, if Fi is greater than Ti, the memory chip cannot be repaired, the memory chip is marked, and the failed unit circuit information of the memory chip is deleted from the hash table data structure.
In another preferred embodiment of the present invention, the specific process of traversing is:
Traversing the X-Y hash table structure to obtain a Y address bit set Gx corresponding to the X address bits, wherein V Gx is expressed as the numerical value of the set Gx, and if V Gx＞Colmax,Colmax is expressed as the maximum failure unit circuit number in the column direction, the column standby circuit can be repaired; setting the X address bit as a specific failure unit circuit of a row standby circuit, arbitrarily distributing a group of row standby circuits for repairing, marking and deleting the memory chip if no row standby circuit is available, and updating the hash table structure; if available line standby circuits exist, updating the X-Y and Y-X hash table structures, and deleting the repaired address information of the failure unit circuit;
Traversing the Y-X hash table structure to obtain an X address bit set Gy corresponding to the Y address bits, wherein V Gy is expressed as a numerical value of the set Gy, and if V Gy＞Rowmax,Rowmax is expressed as the maximum number of invalid unit circuits in the row direction, the row standby circuit can repair; setting the Y address bit to a column spare circuit specific fail cell circuit; optionally allocating a group of column standby circuits for repairing, if no column standby circuits are available, marking and deleting the memory chip, and updating the hash table structure; if there is a column redundancy circuit available, the X-Y and Y-X hash table structures are updated and the repaired failed cell circuit address information is deleted.
In another preferred embodiment of the present invention, the specific process of comparison is:
Marking the rest of deleted invalid unit circuits as sparse invalid unit circuits, acquiring the maximum set of values max-X, max-x=max (hash-table (X-Y)) in all the X-Y hash tables at the moment, and recording the corresponding X value at the moment; and obtaining the numerical value max-Y of the maximum set in all Y-X hash tables, recording the Y value corresponding to the numerical value max-y=max (hash-table (Y-X)), screening the value of the maximum set in the two hash tables as M, wherein M=max { max-x|max-Y }.
In a preferred case of this embodiment, if max-x=max-y, and the maximum set value stored in the two hash tables is equal, then max-y is determined as M output.
In another preferred embodiment of the present invention, an X or Y bit coordinate corresponding to M is obtained, if the X value is the row standby circuit, the Y value is the column standby circuit, if the standby circuit is not available, the die or chip is marked and removed, the data traversing the die or chip is stopped, and the next die or chip is entered into the repair solution process; if the solution can be normally found, recording the service condition of the standby circuit, updating the X-Y and Y-X hash table structures, deleting the repaired failure unit circuit address information until the data values in the X-Y and Y-X hash table structures are empty, stopping traversing, and enabling the crystal grain or chip to be normally repaired;
Repeating all the steps until the test information of all the crystal grains or chips is traversed, and outputting the normal repairable crystal grains or chips (coordinate information and repair scheme information) and the coordinate information of the removed crystal grains or chips.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.
Claims (7)
1. The method for repairing the memory chip based on the test equipment is characterized by comprising the following steps of:
The test equipment is connected with the memory chip for testing, the memory chip is divided into a plurality of blocks and numbered, and failure unit circuit information in the memory chip is extracted from the binary test log;
Counting the number of the invalid unit circuits under different blocks, taking the number of any block as a storage key value, taking the number of the invalid unit circuits of the block and the coordinate information (X, Y) of the invalid unit circuits as storage values, and storing all the information of the invalid unit circuits into a hash table data structure;
In any block, taking any X address bit as a key value and a corresponding set of Y address bits as a storage value to obtain an X-Y hash table structure; taking any Y address bit as a key value and a corresponding X address bit set as a storage value to obtain a Y-X hash table structure;
Traversing the X-Y hash table structure and the Y-X hash table structure respectively to obtain a Y address bit set Gx corresponding to any X address bit and an X address bit set Gy corresponding to any Y address bit, and if the numerical value of the set Gx is larger than the maximum number of the column standby circuits for repairing the column direction, randomly distributing a group of row standby circuits for repairing; if the value of the set Gy is larger than the maximum failure unit circuit number of the row standby circuit for repairing the row direction; then a set of column standby circuit repairs are arbitrarily allocated; if no row/column standby circuit can be allocated, marking and deleting the memory chip, updating the hash table structure and stopping traversing; if the row/column standby circuit can be allocated, updating the X-Y and Y-X hash table structures, and deleting the repaired failure unit circuit address information;
Comparing the deleted X-Y and Y-X hash table structures, acquiring the maximum aggregate value M according to the aggregate size of the storage values corresponding to each key value, if M corresponds to an X address bit coordinate, distributing row standby circuits, if M corresponds to a Y address bit coordinate, distributing column standby circuits, and if no standby circuit can be used, marking the storage chip and deleting; if a usable standby circuit exists, recording the service condition of the standby circuit, updating the X-Y and Y-X hash table structures, deleting the repaired failure unit circuit address information until the data values in the X-Y and Y-X hash table structures are empty, and stopping traversing, so that the memory chip can be repaired normally;
The specific process of comparison is as follows:
Marking the rest of deleted invalid unit circuits as sparse invalid unit circuits, acquiring the maximum set of values max-X, max-x=max (hash-table (X-Y)) in all the X-Y hash tables at the moment, and recording the corresponding X value at the moment; and obtaining the numerical value max-Y of the maximum set in all Y-X hash tables, recording the Y value corresponding to the numerical value max-y=max (hash-table (Y-X)), screening the value of the maximum set in the two hash tables as M, wherein M=max { max-x|max-Y }.
2. The method for repairing a memory chip based on a test apparatus according to claim 1, wherein the process of collecting the failure unit circuit information is as follows:
The method comprises the steps of collecting initial failure unit circuit information of a storage chip through test equipment and recording the initial failure unit circuit information into a memory medium, and obtaining configuration information of the storage chip and coding specifications of the test equipment, wherein the configuration information comprises the number of blocks, the address bit information of the failure unit circuit, the number and distribution of standby circuits, the failure unit circuit information is extracted from the memory medium, and the failure unit circuit information comprises failure unit circuit block numbers, failure unit circuit coordinate information (X, Y) and input-output line numbers.
3. The method for repairing a memory chip according to claim 1, wherein the standby circuit includes a column standby circuit for repairing a failed cell circuit in a column direction in the memory chip and a row standby circuit for repairing a failed cell circuit in a row direction in the memory chip.
4. The method for repairing a memory chip according to claim 1, wherein a maximum number Ti of spare repair circuit units and a failure unit circuit number Fi of each block in the memory chip are obtained, i represents a block number, if Fi is greater than Ti, the memory chip cannot be repaired, the memory chip is marked, and failure unit circuit information of the memory chip is deleted from the hash table data structure.
5. The method for repairing a memory chip based on test equipment according to claim 1, wherein the specific process of traversing is:
Traversing the X-Y hash table structure to obtain a Y address bit set Gx corresponding to the X address bits, wherein V Gx is expressed as the numerical value of the set Gx, and if V Gx＞Colmax,Colmax is expressed as the maximum failure unit circuit number in the column direction, the column standby circuit can be repaired; setting the X address bit as a specific failure unit circuit of a row standby circuit, arbitrarily distributing a group of row standby circuits for repairing, marking and deleting the memory chip if no row standby circuit is available, and updating the hash table structure; if available line standby circuits exist, updating the X-Y and Y-X hash table structures, and deleting the repaired address information of the failure unit circuit;
Traversing the Y-X hash table structure to obtain an X address bit set Gy corresponding to the Y address bits, wherein V Gy is expressed as a numerical value of the set Gy, and if V Gy＞Rowmax,Rowmax is expressed as the maximum number of invalid unit circuits in the row direction, the row standby circuit can repair; setting the Y address bit to a column spare circuit specific fail cell circuit; optionally allocating a group of column standby circuits for repairing, if no column standby circuits are available, marking and deleting the memory chip, and updating the hash table structure; if there is a column redundancy circuit available, the X-Y and Y-X hash table structures are updated and the repaired failed cell circuit address information is deleted.
6. The method according to claim 1, wherein if max-x=max-y, the maximum set value stored in the two hash tables is equal, then max-y is determined as M output.
7. The method for repairing memory chips based on test equipment according to claim 1, wherein when all the test information of the memory chips is traversed, normal repairable memory chip information is output, and unrepairable memory chip information is removed.
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