CN117712165A - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN117712165A CN117712165A CN202311434993.9A CN202311434993A CN117712165A CN 117712165 A CN117712165 A CN 117712165A CN 202311434993 A CN202311434993 A CN 202311434993A CN 117712165 A CN117712165 A CN 117712165A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 69
- 238000000034 method Methods 0.000 title claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims abstract description 32
- 238000002955 isolation Methods 0.000 claims description 49
- 229910052732 germanium Inorganic materials 0.000 claims description 28
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 28
- 239000011810 insulating material Substances 0.000 claims description 12
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 11
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 11
- 238000000231 atomic layer deposition Methods 0.000 claims description 5
- 238000011065 in-situ storage Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 170
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000005530 etching Methods 0.000 description 7
- 230000006870 function Effects 0.000 description 7
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 description 6
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 description 6
- OQNXPQOQCWVVHP-UHFFFAOYSA-N [Si].O=[Ge] Chemical compound [Si].O=[Ge] OQNXPQOQCWVVHP-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- DFIYWQBRYUCBMH-UHFFFAOYSA-N oxogermane Chemical compound [GeH2]=O DFIYWQBRYUCBMH-UHFFFAOYSA-N 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
Abstract
The invention relates to a semiconductor device and a method of forming the same, the semiconductor device including a substrate, a gate line, and a stress layer. The substrate comprises a plurality of first height fins and a plurality of second height fins protruding away from the substrate, wherein the first height fins and the second height fins have different heights; the grid line is positioned above the second height fin and connected with the first side wall of the first height fin; the stress layer is of a material different from that of the first height fin and covers over the second sidewall of the first height fin; the first side wall of the first height fin is arranged at one side adjacent to the second height fin, and the second side wall of the first height fin is arranged at the other side far away from the second height fin.
Description
Technical Field
The present invention relates generally to a semiconductor device and a method of forming the same, and more particularly, to a semiconductor memory device and a method of forming the same.
Background
Shrinking the size of memory cells to increase the level of integration is a trend for many years in the memory industry as well as in the semiconductor industry, thereby increasing the storage capacity of dynamic random access memory chips. In a DRAM cell with a buried gate, the current leakage caused by the capacitor is reduced or avoided, thanks to the relatively long length of the channel under the buried gate. Accordingly, since the buried gate has superior performance, more and more dynamic random access memory cells are equipped with the buried gate, instead of the conventional planar gate structure. In general, a dynamic random access memory cell having a buried gate includes a transistor device and a charge storage device capable of receiving signals from a bit line and a word line during operation. However, due to manufacturing technology limitations, many defects are formed in dynamic random access memory cells with buried gates.
Disclosure of Invention
It is an object of the present invention to provide a semiconductor device and method of forming the same in which a germanium-containing layer, including, for example, germanium, silicon germanium, germanium oxide, silicon germanium oxide, etc., is provided on the sides of the fin to provide proper stress to the channel of the device and to improve the lattice structure of the device channel. Therefore, the channel of the semiconductor device of the present invention can thus obtain a preferable electron mobility.
To achieve the above object, one embodiment of the present invention provides a semiconductor device including a substrate, a gate line, and a stress layer. The substrate comprises a plurality of first height fins and a plurality of second height fins protruding away from the substrate, wherein the first height fins and the second height fins have different heights; the grid line is positioned above the second height fin and connected with the first side wall of the first height fin; the stress layer is of a material different from that of the first height fin and covers over the second sidewall of the first height fin; the first side wall of the first height fin is arranged at one side adjacent to the second height fin, and the second side wall of the first height fin is arranged at the other side far away from the second height fin.
In order to achieve the above object, another embodiment of the present invention provides a semiconductor device including a substrate, a stress layer, a gate line, and a capping layer. The substrate includes a plurality of fins separated by shallow trench isolation; the stress layer is made of a material different from that of the fins and is arranged between the fins and the shallow trench isolation; the gate line is positioned in the active region and comprises a gate dielectric layer and a gate electrode layer which are stacked in sequence; the covering layer is positioned on the grid line; wherein the top of the stress layer is higher than the top of the gate electrode layer in a direction away from the substrate.
In order to achieve the above object, another embodiment of the present invention provides a method of forming a semiconductor device, including the following steps. First, a substrate is provided, and a plurality of first-height fins are formed on the substrate. A stress layer is then formed on the sidewalls of the first height fins, wherein the stress layer is of a material different from the material of the first height fins. Then, filling an insulating material to isolate the plurality of first-height fins; a trench is formed in the first height fin, the trench defining a second height fin having a different height. Finally, a gate dielectric layer, a gate electrode layer and a capping layer are sequentially stacked on the second-height fins. Wherein the top of the stress layer is higher than the top of the gate electrode layer in a vertical direction away from the substrate.
In general, the semiconductor device of the present invention further includes a germanium-containing layer disposed on a side surface of the fin and a gate line crossing the fin, wherein the germanium-containing layer generates appropriate stress and a preferred lattice structure for a channel of the semiconductor device, and thus, the semiconductor device can thus obtain enhanced high electron mobility. The germanium-containing layer may include, for example, germanium, silicon germanium, germanium oxide, or other suitable materials. In this way, the semiconductor device of the present invention achieves better functionality and performance.
The objects of the present invention will no doubt become obvious to those skilled in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.
Drawings
Fig. 1 to 11 are schematic diagrams showing a method of forming a semiconductor device according to a first preferred embodiment of the present invention, in which:
fig. 1 shows a top view of a semiconductor device after forming an active region;
FIG. 2 shows a cross-sectional view taken along section line A-A' in FIG. 1;
fig. 3 shows a cross-sectional view of the semiconductor device after formation of a stress layer;
fig. 4 shows a cross-sectional view of the semiconductor device after shallow trench isolation is formed;
fig. 5 shows a top view of the semiconductor device after forming a trench;
FIG. 6 shows a cross-sectional view taken along section line A-A' in FIG. 5;
FIG. 7 shows a cross-sectional view taken along section line B-B' in FIG. 5;
fig. 8 shows a cross-sectional view of the semiconductor device after performing an oxidation fabrication process;
fig. 9 shows a top view of the semiconductor device after forming the gate line;
FIG. 10 shows a cross-sectional view taken along section line A-A' in FIG. 9;
FIG. 11 shows a cross-sectional view taken along section line B-B' in FIG. 9;
fig. 12-13 are schematic diagrams illustrating a method of forming a semiconductor device according to a second preferred embodiment of the present invention, wherein:
fig. 12 shows a cross-sectional view of the semiconductor device after shallow trench isolation is formed;
fig. 13 shows a cross-sectional view of the semiconductor device after forming a trench;
fig. 14 shows another cross-sectional view of the semiconductor device after forming a trench;
fig. 15 shows a schematic view of a method of forming a semiconductor device according to a third preferred embodiment of the present invention.
Wherein reference numerals are as follows:
100. substrate and method for manufacturing the same
101. Topmost surface
102. Groove(s)
105. Groove(s)
105a exposed side wall
105b expose the bottom wall
110. Fin type fin
115. Fin type fin
130. Stress layer
150. Shallow trench isolation
150a shallow trench isolation
151. A first insulating layer
152. Oxide layer
153. Second insulating layer
155. Shallow trench isolation
155a shallow trench isolation
155b shallow trench isolation
170. Oxide layer
170a oxide layer
171. Oxide layer
171a oxide layer
173. Oxide layer
190. Gate structure
190a gate structure
191. Gate dielectric layer
193. Gate electrode layer
210. Cover layer
300. Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
500. Semiconductor device with a semiconductor layer having a plurality of semiconductor layers
D1 Direction of
D2 Direction of
G1 Distance of
G2 Distance of
H1 Height of (1)
H2 Height of (1)
T1 thickness
T2 thickness
T3 thickness
T4 thickness
Detailed Description
For a better understanding of the present invention, preferred embodiments will be described in detail hereinafter. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements. Furthermore, technical features in different embodiments described below may be replaced, recombined or mixed with each other to constitute another embodiment without departing from the spirit of the invention.
Fig. 1-11 illustrate a method of forming a semiconductor device according to a preferred embodiment of the present invention, wherein fig. 1, 5, 9 each illustrate a top view of the semiconductor device during formation, and the other figures each illustrate a cross-sectional view of the semiconductor device during formation. First, as shown in fig. 1-2, a substrate 100 such as a silicon substrate or a silicon-containing substrate is provided, and a plurality of fins 110 are formed on the substrate 100, each fin 110 protruding from the topmost surface 101 of the substrate 100. In other words, although the plurality of fins 110 and the substrate 100 are integrally formed, the topmost surface 101 of the substrate 100 may still be considered as the interface between the plurality of fins 110 and the substrate 100 (e.g., the dashed line shown in fig. 1).
In one embodiment, the plurality of fins 110 may be formed through a self-aligned double patterning (SADP) fabrication process or a self-aligned reverse double patterning (SARP) fabrication process, wherein a plurality of mandrels (not shown) are first formed on a bulk silicon substrate (not shown) by using photolithography and etching processes, then spacers (not shown) are formed on sidewalls of each of the mandrels, and the mandrels are removed, and the bulk silicon substrate is patterned using the spacers as a mask, thereby forming a plurality of trenches 102 as shown in fig. 2, to simultaneously define the plurality of fins 110. Alternatively, the plurality of fins 110 may be formed by first forming a patterned mask (not shown) on the substrate 100 to partially cover the topmost surface 101 of the substrate 100, and then performing an epitaxial process on the substrate 100 through the patterned mask, thereby forming a semiconductor layer (not shown) on the topmost surface 101 of the substrate 100 exposed, wherein the semiconductor layer serves as a corresponding plurality of fins.
In an embodiment, each fin 110 is preferably parallel to each other and extends in a direction D1 via a top view as shown in fig. 1, wherein the direction D1 forms an angle θ with an x-direction or a y-direction (e.g., the direction D2 shown in fig. 1), but is not limited thereto. Furthermore, as shown in fig. 1-2, the grooves 102 may include different distance ratios G1/G2 in the direction D2 such that some of the fins 110 may be spaced from each other by a relatively small distance G1 and other of the fins 110 may be spaced from each other by a relatively large distance G2. However, in another embodiment, each of the fins 110 may be spaced apart from each other by the same distance (not shown) based on actual product requirements.
As shown in fig. 3, a stress (material) layer 130 is next formed on the surfaces of the plurality of fins 110 and the topmost surface 101 of the substrate 100, for example, by a deposition process or an epitaxial growth process. Preferably, stress (material) layer 130 comprises a germanium-containing layer that can generate an appropriate stress and preferably a lattice structure, wherein the germanium-containing layer includes, for example, but is not limited to, germanium, silicon germanium, and the like. For example, the stress (material) layer 130 may comprise silicon germanium or germanium, while the substrate 100 and the plurality of fins 110 comprise silicon, thereby improving the lattice structure of the substrate 100 and the fins 110. However, in other embodiments, the stress (material) layer 130 may include other materials, such as carbide, silicon carbide, etc., for generating appropriate stress and improving the lattice structure. In addition, the stress (material) layer 130 includes a relatively small thickness T1 with respect to the substrate 100, for example, the thickness T1 may be about 1 angstrom to 10 nanometers, but is not limited thereto.
Then, as shown in fig. 4, shallow trench isolations 150 are formed on the substrate 100 to cover the stress (material) layer 130, wherein the shallow trench isolations 150 surround each fin 110. In an embodiment, the shallow trench isolation 150 may be formed through at least one deposition process and a planarization process, wherein a first insulating material layer (not shown) may be preferentially deposited on the substrate 100 to fill at least the trench 102 having a relatively small distance G1, a second insulating material layer (not shown) may be subsequently deposited on the first insulating material layer to fill the trench 102 having a relatively large distance G2, and an etch back process or a chemical mechanical polishing/planarization process may be performed to remove the second insulating material layer and the first insulating material layer disposed on the topmost surface of the plurality of fins 110, thereby forming the shallow trench isolation 150 aligned with the topmost surface of the fins 110 as shown in fig. 4. Those skilled in the art will fully recognize that shallow trench isolation 150 may also be formed by other processes such as an Atomic Layer Deposition (ALD) process or an in situ vapor generation (ISSG) process, based on actual product requirements.
The first insulating material layer and the second insulating material layer comprise, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride or silicon carbonitride, and the materials of the first insulating material layer and the second insulating material layer are optionally the same as or different from each other. Preferably, the first and second layers of insulating material are of different materials, including but not limited to silicon oxide and silicon nitride, respectively, for example. Accordingly, the shallow trench isolation 150 disposed within the trench 102 having the relatively large distance G2 may have a multi-layered structure including a first insulating layer (including silicon oxide) 151 and a second insulating layer (including silicon nitride) 153 stacked from bottom to top, and the shallow trench isolation 150 disposed within the trench 102 having the relatively small distance G1 may have a single layer structure including only the first insulating layer 151 as shown in fig. 4. However, in another embodiment, the trenches 102 may also be filled with the same dielectric material having different densities or more various dielectric materials to form shallow trench isolation having a partial multi-layer structure and a partial single-layer structure.
Next, as shown in fig. 5-7, at least one trench 105 is formed in the direction D2 to intersect the plurality of fins 110. Those skilled in the art will readily appreciate that the exact number of grooves 105 may vary based on actual product requirements, such as, but not limited to, five as shown in fig. 5. In an embodiment, each of the trenches 105 is parallel to each other in the direction D2 to simultaneously penetrate the plurality of fins 110 extending in the direction D1, and if each of the fins 110 is seen from the top view shown in fig. 5, each of the fins may be penetrated by two of the trenches 105 at the same time, but is not limited thereto. The trench 105 may be formed by first providing a mask (not shown) on the substrate 100, the mask having at least one opening (not shown) where the opening partially exposes the plurality of fins 110 and the shallow trench isolation 150, and performing at least one etching process to partially remove the exposed portions of the plurality of fins 110 and the shallow trench isolation 150. Thus, each trench 105 may pass through both the shallow trench isolation 150 and the plurality of fins 110 to form the plurality of fins 115 and the shallow trench isolation 155, both of which have a reduced height within the trench 105 as shown in fig. 5-6. As shown in fig. 7, the plurality of fins 115 are formed of etched portions of the plurality of fins 110, and the maximum height H1 of the fins 115 is significantly smaller than the maximum height H2 of the fins 110, wherein the heights H1, H2 of the fins 115 and 110 may be regarded as distances between the topmost surfaces of the fins 115 and 110, respectively, and the topmost surface 101 of the substrate 100.
It is noted that during the etching process, there may be different degrees of etching of the plurality of fins 110 and the shallow trench isolation 150 because the etch rate may vary based on the materials of the plurality of fins 110 and the shallow trench isolation 150. Thus, the bottom wall of each trench 105 at the plurality of fins 115 and the shallow trench isolation 155 may be uneven, for example, as shown in fig. 6, the topmost surface of the plurality of fins 115 may be relatively higher than the topmost surface of the shallow trench isolation 155. It should also be noted that the stress (material) layer 130 disposed on the exposed portions of the plurality of fins 110 is also removed during the etching process, thereby forming a stress layer 130 that directly exposes the topmost surface of each fin 115, as shown in fig. 6. In other words, after the etching process, as shown in fig. 7, the stress layer 130 covers the topmost surface and the side surfaces of each fin 110, and as shown in fig. 6, the stress layer 130 covers only the side surfaces of each fin 115, and the portion of each trench 105 located within the fin 110 has exposed sidewalls 105a and exposed bottom walls 105b (i.e., the topmost surface of each fin 115).
In turn, as shown in fig. 8, an oxidation process, such as an ALD process or an ISSG process, is performed on all exposed surfaces of the plurality of fins 110 and the plurality of fins 115 to form an oxide layer 170. Precisely, the oxide layer 170 is formed by simultaneously consuming the underlying exposed surfaces, and thus the oxide layer 171 disposed on the side surface of each fin 115 and in direct contact with the stress layer 130 may include the same elements as the stress layer 130. For example, although stress layer 130 comprises silicon germanium or germanium, and a portion of oxide layer 171 may comprise silicon germanium oxide (SiGeO x ) Or germanium oxide (GeO) x ) But is not limited thereto. On the other hand, the oxide layer 173 of another portion disposed on the topmost surface of each fin 115 and in direct contact with the plurality of fins 115 may include the same element as the plurality of fins 115, for example, include silicon oxide (SiO x ) And the plurality of fins 115 includes, but is not limited to, silicon or silicon-containing materials. Likewise, although not shown in fig. 8, another portion of the oxide layer 171 (not shown in fig. 8, but shown in fig. 11) disposed on the topmost surface of each fin 110 may also include the same elements as the underlying stress layer 130, and the material thereof may thus be silicon germanium oxide or germanium oxide; and the oxide layer 173 (not shown in fig. 8, but shown in fig. 11) of another portion disposed on the exposed sidewalls 105a of each trench 105 may also include the same element as the plurality of fins 110, and thus the material thereof may be, but is not limited to, silicon oxide.
It is noted that due to material differences between different portions of oxide layer 170 (i.e., the portion of oxide layer 171 and the other portion of oxide layer 173), oxide layer 170 between different portions may include different thicknesses, such as, but not limited to, a thickness T2 of a portion of oxide layer 171 (e.g., including germanium oxide or silicon oxide) being relatively greater than a thickness T3 of another portion of oxide layer 173 (e.g., including silicon oxide). Furthermore, following the oxidation process, the underlying stress layer 130 may thus include different element concentrations in different portions. For example, if stress layer 130 comprises silicon germanium or germanium, various portions of stress layer 130 may comprise different germanium concentrations after an oxidation process, wherein stress layer 130 disposed below oxide layer 170 (i.e., portions of oxide layer 171) has a relatively low germanium concentration relative to stress layer 130 disposed below shallow trench isolation 155.
Thereafter, as shown in fig. 9-11, at least one gate structure 190 is formed within trench 105 to fill the bottom of trench 105, and then a cap layer 210 is formed over gate structure 190 to fill the remainder of trench 105. Those skilled in the art will readily recognize that the exact number of gate structures 190 may be consistent with the actual number of trenches 105, such as, but not limited to, five as shown in fig. 9. As shown in fig. 10-11, each gate structure 190 extends in direction D2 to span the plurality of fins 115 and shallow trench isolation 155, and further includes a gate dielectric layer 191 and a gate electrode layer 193 stacked from bottom to top within each trench 105. In an embodiment, gate structure 190 may be formed by conformally forming a dielectric layer (not shown, e.g., comprising silicon oxide, silicon nitride, or other suitable dielectric material) over substrate 100 to cover at least the surface of each trench 105, then forming a conductive layer (not shown) over the dielectric layer to fill at least each trench 105, performing an etch-back process to partially remove the conductive layer and dielectric layer filled in each trench 105 in the case of a conductive layer, e.g., comprising a low resistance metal such as tungsten, aluminum, or copper, thereby forming gate dielectric layer 191 and gate electrode layer 193, and then forming capping layer 210 over gate structure 190 to fill each trench 105.
Through these processes, a semiconductor device 300 according to a preferred embodiment of the present invention is obtained that includes a plurality of gate lines (i.e., gate structures 190) embedded in the plurality of fins 110 and shallow trench isolation 150, respectively, to behave as buried gate lines. Further, after obtaining the structure shown in fig. 9-11, a plurality of conductive lines (not shown) and at least one capacitor (not shown) may be further formed on the topmost surface of the plurality of fins 110, the semiconductor device 300 may thus function as a memory device like a Dynamic Random Access Memory (DRAM) device, wherein each gate structure 190 functions like a Word Line (WL) and each conductive line functions like a Bit Line (BL) for receiving and transmitting signals in the dynamic random access memory array during operation. However, in another embodiment, other active elements may be formed on the plurality of fins 110 in a subsequent process, and the semiconductor device 300 may thus perform various functions or performances as other semiconductor memory devices.
With further reference to fig. 11, a semiconductor device 300 in accordance with a preferred embodiment of the present invention includes at least one trench 105 through a plurality of fins 110 and shallow trench isolation 150, and at least one gate line (i.e., gate structure 190) buried at the bottom of the at least one trench 105 to span the plurality of fins 115 and shallow trench isolation 155 of reduced height. As can be seen from the cross-sectional view shown in fig. 11, the plurality of fins 110 are disposed on both sides of the plurality of fins 115, and the plurality of fins 110, 115 are surrounded by the shallow trench isolation 150, and the maximum height H2 of the plurality of fins 110 is greater than the maximum height H1 of the plurality of fins 115. Specifically, the at least one gate line includes a gate dielectric layer 191 and a gate electrode layer 193 stacked from bottom to top, wherein the gate dielectric layer 191 is disposed between the plurality of fins 115 and the gate electrode layer 193, and the gate dielectric layer 191 may include a U-shaped structure as shown by the cross-sectional view of fig. 11. In addition, semiconductor device 300 includes a stress layer 130 disposed on the side surfaces of the plurality of fins 115 and the topmost surface 101 of substrate 100. The stress layer 130 preferably comprises a germanium-containing layer that can create an appropriate stress and preferably a lattice structure, and the germanium-containing layer preferably comprises a material other than the substrate 100, including, for example, germanium, silicon germanium, and the like. In this way, the channel of at least one gate line can thus obtain a suitable stress and a preferred lattice structure, thereby improving the electron mobility and performance of the drive current. In addition, as shown in fig. 11, the stress layer 130 is also disposed on the topmost surface and the side surfaces of the plurality of fins 110, because the formation of the stress layer 130 is prioritized over the formation of the shallow trench isolation 150, and the germanium concentration within the stress layer 130 may be different for different distribution portions, such as having a relatively lower concentration in the upper portion and a relatively higher concentration in the bottom portion or no residue.
The semiconductor device 300 further includes an oxide layer 170, the oxide layer 170 being formed by simultaneously consuming exposed surfaces underneath, such as the stress layer 130 or the exposed surfaces of the plurality of fins 110, 115. Accordingly, a portion of the oxide layer 171 may also include germanium, and it is disposed on side surfaces of the plurality of fins 115 and the topmost surface of the plurality of fins 110 to have an L-shaped structure as shown in fig. 11. On the other hand, another portion of the oxide layer 173 may also include silicon and be disposed on the topmost surface of the plurality of fins 115 (also referred to as the bottom wall of the trench 105) and on the sidewalls of the trench 105 to form a U-shaped structure between the gate structure 190 within each trench 105 and the plurality of fins 110, 115, as shown in fig. 10-11. In this way, different portions of oxide layer 170 (i.e., the portion of oxide layer 171 and the other portion of oxide layer 173) may include different materials and different thicknesses T2, T3. In an embodiment, a portion of oxide layer 171 may include silicon germanium oxide or germanium oxide, and another portion of oxide layer 173 may include, but is not limited to, silicon oxide.
Those skilled in the art will readily recognize that the semiconductor device and method of forming the same in the present invention are not limited to the embodiments described above, and may include other examples or variations as well. The following description will describe in detail different embodiments of the semiconductor device and the method of forming the same in the present invention. In order to simplify the description, the following description will describe in detail the differences between the different embodiments, and the same features will not be repeated. In order to easily compare differences between the embodiments, the same parts in each of the following embodiments are labeled with the same symbols.
Referring to fig. 12-13, a method of forming a semiconductor device according to a second preferred embodiment of the present invention is shown. The previous steps of this embodiment are substantially the same as those of the first preferred embodiment, and will not be described again. The difference between the foregoing first preferred embodiment and the present embodiment is that the shallow trench isolation 150a of the portion of the present embodiment includes a three-layer structure including an oxide layer 152, a first isolation layer 151, and a second isolation layer 153. As shown in fig. 12, oxide layer 152 is formed by an ALD process or ISSG process and consumes and oxidizes at least a portion of the elements (e.g., germanium, silicon germanium) within stress layer 130 to form oxide layer 152 (e.g., including germanium, silicon germanium). Thereafter, the trench 105 is formed by partially removing the plurality of fins 110 and the shallow trench isolation 150a (including the oxide layer 152, the first isolation layer 151, and the second isolation layer 153), and thereby the plurality of fins 115 and the shallow trench isolation 155a having a reduced height as shown in fig. 13 are formed. Then, similar to fig. 7-11 of the first preferred embodiment described above, the oxide layer 170 and gate structure 190 may be further formed in a subsequent process to span the plurality of fins 115. However, in another embodiment, the oxide layer 152 and the isolation layer (including the first isolation layer 151 and the second isolation layer 153) may have different etching degrees when forming the trench 105, and thus, the plurality of fins 115 and the shallow trench isolation 155b are formed, wherein the oxide layer 152 remains on the entire side surfaces of the plurality of fins 155 to protrude from the topmost surface portions of the first isolation layer 151 and the second isolation layer 153 as shown in fig. 14. In another embodiment, an oxide layer (not shown) formed in a subsequent oxidation process may be disposed on the oxide layer 152, the oxide layer 152 protruding from the topmost surfaces of the first and second isolation layers 151 and 153, and may be optionally combined with the oxide layer 152.
Thus, the semiconductor device formed in this embodiment includes a germanium-containing layer (e.g., stress layer 130, oxide layer 171, or oxide layer 152) disposed on the side surfaces of the plurality of fins 115 to provide appropriate stress and improved lattice structure to the channel. Then, the semiconductor device of the present embodiment is allowed to obtain a larger electron mobility, realizing a better function and performance.
Referring to fig. 15, a method of forming a semiconductor device 500 according to a third preferred embodiment of the present invention is shown. The previous steps of this embodiment are substantially the same as those of the first preferred embodiment, and will not be described again. The difference between the foregoing first preferred embodiment and the present embodiment is that a portion of the oxide layer 171a in the present embodiment is formed by completely consuming and oxidizing the underlying stress layer 130, thereby obtaining a greater thickness T4. Accordingly, as shown in fig. 15, the oxide layer 170a of the present embodiment includes a first portion (i.e., the oxide layer 173) directly disposed on the topmost surface of the plurality of fins 115 and a second portion (i.e., the oxide layer 171 a) directly disposed on the side surfaces of the plurality of fins 115, wherein the first portion 173 and the second portion 171a include different materials and thicknesses T3, T4, respectively. In the present embodiment, the first portion 173 includes, for example, silicon oxide, and the second portion 171a includes, for example, germanium oxide or silicon oxide, but is not limited thereto. Subsequently, a gate electrode layer 193 is formed to fill the bottom of the trench 105, and then a capping layer 210 is formed on the gate electrode layer 193 to fill the remaining portion of the trench 105. Then, the gate electrode layer 193 and the oxide layer 170a may together form a gate structure 190a. In other words, the gate dielectric layer 191 of the foregoing first preferred embodiment is omitted in the present embodiment, and the oxide layer 170a formed in the present embodiment is disposed between the gate electrode layer 193 and the plurality of fins 115, i.e., can serve as the gate dielectric layer of the gate structure 190a.
Thus, the semiconductor device 500 formed in this embodiment also includes a germanium-containing layer (e.g., oxide layer 171 a) disposed on the side surfaces of the plurality of fins 115 to provide appropriate stress and improved lattice structure to the channel. Then, the semiconductor device 500 of the present embodiment is allowed to obtain a larger electron mobility, realizing a better function and performance.
In general, the semiconductor device of the present invention includes a germanium-containing layer disposed on side surfaces of a plurality of fins with gate lines crossing the plurality of fins, the germanium-containing layer imparting appropriate stress and a preferred lattice structure to its channels. The germanium-containing layer comprises germanium, silicon germanium, germanium oxide (GeO) x ) Silicon germanium oxide (SiGeO) x ) Or other suitable material, thereby allowing the semiconductor device of the present invention to achieve greater electron mobility and thus better function and performance.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (13)
1. A semiconductor device, comprising:
a substrate comprising a plurality of first height fins and a plurality of second height fins protruding away from the substrate, wherein the first height fins and the second height fins have different heights;
a gate line located above the second height fin and connected to a first sidewall of the first height fin;
a stress layer of a material different from the material of the first height fin and overlying the second sidewall of the first height fin; the first side wall of the first height fin is arranged at one side adjacent to the second height fin, and the second side wall of the first height fin is arranged at the other side far away from the second height fin.
2. The semiconductor device of claim 1, further comprising an oxide layer between the gate line and the plurality of second-height fins, wherein the oxide layer comprises a first portion disposed on a topmost surface of the plurality of second-height fins and a second portion disposed on a side surface of the plurality of second-height fins.
3. The semiconductor device of claim 2, wherein the first portion and the second portion comprise different materials.
4. The semiconductor device of claim 2, wherein a portion of the stress layer covers a side surface of the second height fin and is in direct contact with a second portion of the oxide layer.
5. The semiconductor device of claim 2, wherein the second portion comprises the same element as the stress layer.
6. The semiconductor device of claim 1, wherein a maximum height of the first plurality of height fins is greater than a maximum height of the second plurality of height fins.
7. The semiconductor device of claim 1, further comprising shallow trench isolation surrounding the plurality of first height fins and the plurality of second height fins.
8. The semiconductor device of claim 1, wherein the stress layer comprises silicon germanium or germanium.
9. A semiconductor device, comprising:
a substrate comprising a plurality of fins separated by shallow trench isolation;
a stress layer of a material different from that of the plurality of fins and disposed between the plurality of fins and the shallow trench isolation;
a gate line located within the active region and including a gate dielectric layer and a gate electrode layer stacked in sequence;
a capping layer on the gate line;
wherein the top of the stress layer is higher than the top of the gate electrode layer in a direction away from the substrate.
10. A method of forming a semiconductor device, comprising:
providing a substrate, and forming a plurality of first-height fins on the substrate;
forming a stress layer on sidewalls of the first height fin, wherein a material of the stress layer is different from a material of the first height fin;
filling an insulating material to isolate the plurality of first height fins;
forming a trench in the first height fin, the trench defining a second height fin having a different height;
sequentially stacking a gate dielectric layer, a gate electrode layer and a capping layer on the second height fin;
wherein the top of the stress layer is higher than the top of the gate electrode layer in a vertical direction away from the substrate.
11. The method of forming a semiconductor device of claim 10, further comprising forming an oxide layer by an atomic layer deposition process or an in situ vapor generation process, wherein the oxide layer is formed between the gate line and the plurality of first and second height fins.
12. The method of forming a semiconductor device of claim 11, wherein the oxide layer further comprises a first portion and a second portion, the first portion disposed on a topmost surface of the plurality of second height fins to directly contact the plurality of second height fins, and the second portion disposed on a side surface of the plurality of second height fins.
13. The method of forming a semiconductor device of claim 11, wherein the first portion and the second portion comprise different materials and the second portion comprises the same element as the stress layer.
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