CN215600366U - Semiconductor device with a plurality of transistors - Google Patents

Abstract

The utility model relates to a semiconductor device including a substrate, a gate line and a stress layer. The substrate has a plurality of first fins protruding from the substrate. The gate line is disposed on the substrate across the first fin to further include a gate electrode layer and a gate dielectric layer, wherein the gate dielectric layer is disposed between the gate electrode layer and the first fin. The stress layer is disposed only on side surfaces of the first fins and on a topmost surface of the substrate, wherein a material of the stress layer is different from a material of the first fins.

Description

Semiconductor device with a plurality of transistors

Technical Field

The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor memory device.

Background

It has been a trend in the memory industry and semiconductor industry to shrink the size of memory cells to increase the level of integration, thereby increasing the storage capacity of dram chips. In a DRAM cell with a buried gate, current leakage due to the capacitor is reduced or avoided due to the relatively long length of the channel under the buried gate. Therefore, more and more dram cells are equipped with buried gates, rather than the conventional planar gate structure, due to the superior performance of the buried gates. In general, a dynamic random access memory cell having a buried gate includes a transistor device and a charge storage device capable of receiving signals from a bitline and a wordline during operation. However, due to limitations of manufacturing techniques, many defects are formed in dynamic random access memory cells having buried gates.

SUMMERY OF THE UTILITY MODEL

It is an object of the present invention to provide a semiconductor device in which a ge-containing layer, for example comprising ge, sige, germania, sige oxide, etc., is provided on the sides of the fin to provide appropriate stress to the channel of the device as well as an improved lattice structure of the channel of the device. Therefore, the channel of the semiconductor device in the present invention can thus obtain better electron mobility.

In order to achieve the above object, one embodiment of the present invention provides a semiconductor device including a substrate, a gate line, and a stress layer. The substrate has a plurality of first fins protruding from the substrate. The gate line is disposed on the substrate across the plurality of first fins to further include a gate electrode layer and a gate dielectric layer, wherein the dielectric layer is disposed between the gate electrode layer and the first fins. The stress layer is disposed only on side surfaces of the plurality of first fins and on a topmost surface of the substrate, wherein a material of the stress layer is different from a material of the plurality of first fins.

In some embodiments, the semiconductor device further includes an oxide layer between the gate line and the plurality of first fins, wherein the oxide layer includes a first portion disposed on the topmost surface of the plurality of first fins and a second portion disposed on the side surfaces of the plurality of first fins.

In some embodiments, the first portion and the second portion comprise different materials.

In some embodiments, the first portion and the second portion comprise different thicknesses.

In some embodiments, the second portion directly contacts the stress layer disposed on the side surface of the plurality of first fins, and the first portion directly contacts the plurality of first fins.

In some embodiments, the second portion comprises the same element as the stress layer.

In some embodiments, the semiconductor device further comprises the plurality of second fins protruding from the substrate, wherein a maximum height of the plurality of second fins is greater than a maximum height of the plurality of first fins.

In some embodiments, the semiconductor device further comprises a shallow trench isolation surrounding the plurality of first fins and the plurality of second fins, wherein the shallow trench isolation is located on the stress layer disposed on the topmost surface of the substrate.

In some embodiments, the stress layer comprises silicon germanium or germanium.

In order to achieve the above object, another embodiment of the present invention provides a semiconductor device including a substrate and a gate line. The substrate has a plurality of first fins protruding therefrom, and the gate line is disposed on the substrate and crosses the plurality of first fins. The gate line includes a gate electrode layer and a gate dielectric layer between the gate electrode layer and the plurality of first fins, wherein the gate dielectric layer includes a first portion disposed on a topmost surface of the plurality of first fins and a second portion disposed on a side surface of the plurality of first fins and including silicon germanium oxide or germanium oxide.

In some embodiments, the first portion and the second portion comprise different thicknesses.

In some embodiments, the semiconductor device further comprises:

a plurality of second fins protruding from the substrate, wherein a maximum height of the plurality of second fins is greater than a maximum height of the plurality of first fins; and

shallow trench isolation surrounding the plurality of first fins and the plurality of second fins.

In summary, the semiconductor device of the present invention further includes a germanium-containing layer disposed on a side surface of the fin and a gate line crossing the fin, wherein the germanium-containing layer generates appropriate stress and a preferable lattice structure for a channel of the semiconductor device, and thus, the semiconductor device can obtain enhanced electron mobility. The ge-containing layer includes, for example, ge, sige, ge oxide, or other suitable material. In this way, the semiconductor device of the present invention achieves better function and performance.

The objects of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the various drawing figures.

Drawings

Fig. 1 to 11 are schematic diagrams showing a method of forming a semiconductor device according to a first preferred embodiment of the present invention, in which:

fig. 1 shows a top view of a semiconductor device after forming an active region;

FIG. 2 shows a cross-sectional view taken along section line A-A' in FIG. 1;

FIG. 3 illustrates a cross-sectional view of the semiconductor device after forming a stress layer;

FIG. 4 illustrates a cross-sectional view of the semiconductor device after shallow trench isolation is formed;

fig. 5 shows a top view of the semiconductor device after forming the trench;

FIG. 6 shows a cross-sectional view taken along section line A-A' in FIG. 5;

FIG. 7 shows a cross-sectional view taken along section line B-B' in FIG. 5;

FIG. 8 illustrates a cross-sectional view of the semiconductor device after an oxidation fabrication process has been performed;

fig. 9 shows a top view of the semiconductor device after forming gate lines;

FIG. 10 shows a cross-sectional view taken along section line A-A' in FIG. 9;

FIG. 11 shows a cross-sectional view taken along section line B-B' in FIG. 9;

fig. 12 to 13 are schematic diagrams showing a method of forming a semiconductor device according to a second preferred embodiment of the present invention, in which:

fig. 12 illustrates a cross-sectional view of the semiconductor device after shallow trench isolation is formed;

fig. 13 shows a cross-sectional view of the semiconductor device after forming a trench;

fig. 14 shows another cross-sectional view of the semiconductor device after forming the trench;

fig. 15 shows a schematic view of a method of forming a semiconductor device according to a third preferred embodiment of the present invention.

Wherein the reference numerals are as follows:

100 substrate

101 topmost surface

102 trench

105 grooves

105a exposed sidewall

105b exposed bottom wall

110 second fin

115 first fin

130 stress layer

150 shallow trench isolation

150a shallow trench isolation

151 first insulating layer

152 oxide layer

153 second insulating layer

155 shallow trench isolation

155a shallow trench isolation

155b shallow trench isolation

170 oxide layer

170a oxide layer

171 oxide layer

171a oxide layer

173 oxide layer

190 grid structure

190a gate structure

191 gate dielectric layer

193 gate electrode layer

210 cover layer

300 semiconductor device

500 semiconductor device

Direction D1

Direction D2

Distance G1

Distance G2

Height H1

Height H2

T1 thickness

T2 thickness

T3 thickness

T4 thickness

Detailed Description

For a better understanding of the present invention, preferred embodiments will be described in detail below. Preferred embodiments of the present invention are illustrated by the numbered elements in the figures. Furthermore, technical features in different embodiments described below may be replaced with, recombined with, or mixed with each other to constitute another embodiment without departing from the spirit of the present invention.

Fig. 1 to 11 illustrate a method of forming a semiconductor device according to a preferred embodiment of the present invention, wherein fig. 1, 5, and 9 respectively illustrate a top view of the semiconductor device during formation, and the other figures respectively illustrate a cross-sectional view of the semiconductor device during formation. First, as shown in fig. 1-2, a substrate 100, such as a silicon substrate or a silicon-containing substrate, is provided, and a plurality of second fins 110 are formed on the substrate 100, each second fin 110 protruding from the topmost surface 101 of the substrate 100. In other words, although the plurality of second fins 110 and the substrate 100 are integrally formed, the topmost surface 101 of the substrate 100 may still be considered to be an interface (e.g., the dashed line shown in fig. 1) between the plurality of second fins 110 and the substrate 100.

In one embodiment, the plurality of second fins 110 may be formed by a self-aligned double patterning (SADP) process or a self-aligned reverse double patterning (SARP) process, in which a plurality of mandrels (not shown) are first formed on a bulk silicon substrate (not shown) by using a photolithography and etching process, then spacers (not shown) are formed on sidewalls of each of the mandrels, and the mandrels are removed, and the bulk silicon substrate is patterned using the spacers as a mask, thereby forming a plurality of trenches 102 as shown in fig. 2 to simultaneously define the plurality of second fins 110. Alternatively, the plurality of second fins 110 may be formed by first forming a patterned mask (not shown) on the substrate 100 to partially cover the topmost surface 101 of the substrate 100, and then performing an epitaxial process on the substrate 100 through the patterned mask, thereby forming a semiconductor layer (not shown) on the exposed topmost surface 101 of the substrate 100, wherein the semiconductor layer serves as the corresponding plurality of fins.

In an embodiment, each of the second fins 110 is preferably parallel to each other and extends in a direction D1 via a top view as shown in fig. 1, wherein the direction D1 has an angle θ with the x-direction or y-direction (e.g., the direction D2 shown in fig. 1), but is not limited thereto. 1-2, trenches 102 may include different distance ratios G1/G2 in direction D2 such that some of second fins 110 may be spaced apart from each other by a relatively small distance G1 and other of second fins 110 may be spaced apart from each other by a relatively large distance G2. However, in another embodiment, each of the second fins 110 may be spaced apart from each other by the same distance (not shown) based on actual product requirements.

As shown in fig. 3, a stress (material) layer 130 is next formed on the surfaces of the plurality of second fins 110 and the topmost surface 101 of the substrate 100, for example, by a deposition process or an epitaxial growth process. Preferably, the stress (material) layer 130 includes a ge-containing layer that can generate appropriate stress and a preferred lattice structure, wherein the ge-containing layer includes, but is not limited to, ge, sige, etc. For example, the stress (material) layer 130 may include silicon germanium or germanium, while the substrate 100 and the plurality of second fins 110 include silicon, thereby improving the lattice structure of the substrate 100 and the second fins 110. However, in other embodiments, the stress (material) layer 130 may include other materials such as carbide, silicon carbide, and the like for creating appropriate stress and improving the lattice structure. Furthermore, stress (material) layer 130 includes a relatively small thickness T1 with respect to substrate 100, for example, thickness T1 may be about 1 angstrom to 10 nanometers, but is not limited thereto.

Then, as shown in fig. 4, shallow trench isolations 150 are formed on the substrate 100 to cover the stress (material) layer 130, wherein the shallow trench isolations 150 surround each of the second fins 110. In one embodiment, the shallow trench isolation 150 may be formed by at least one deposition process and a planarization process, wherein a first insulating material layer (not shown) may be preferentially deposited on the substrate 100 to fill at least the trench 102 having the relatively small distance G1, a second insulating material layer (not shown) may be subsequently deposited on the first insulating material layer to fill the trench 102 having the relatively large distance G2, and an etch-back process or a chemical mechanical polishing/planarization process may be performed to remove the second insulating material layer and the first insulating material layer disposed on the topmost surfaces of the plurality of second fins 110, thereby forming the shallow trench isolation 150 flush with the topmost surfaces of the second fins 110 as shown in fig. 4. Those skilled in the art will appreciate that shallow trench isolation 150 may also be formed by other processes such as an Atomic Layer Deposition (ALD) process or an in situ vapor generation (ISSG) process, based on actual product requirements.

The first insulating material layer and the second insulating material layer include, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride, and the materials of the first insulating material layer and the second insulating material layer are optionally the same as or different from each other. Preferably, the first layer of insulating material and the second layer of insulating material are different materials, for example including but not limited to silicon oxide and silicon nitride, respectively. Accordingly, the shallow trench isolation 150 disposed within the trench 102 having the relatively large distance G2 may have a multi-layered structure including the first insulating layer (including silicon oxide) 151 and the second insulating layer (including silicon nitride) 153 stacked from bottom to top, and the shallow trench isolation 150 disposed within the trench 102 having the relatively small distance G1 may have a single-layered structure including only the first insulating layer 151 as shown in fig. 4. However, in another embodiment, the trench 102 may be filled with the same dielectric material or more dielectric materials with different densities to form a shallow trench isolation having a partial multi-layer structure and a partial single-layer structure.

Next, as shown in fig. 5-7, at least one trench 105 is formed in the direction D2 to intersect the plurality of second fins 110. Those skilled in the art will readily appreciate that the exact number of grooves 105 may vary based on actual product requirements, such as, but not limited to, five as shown in fig. 5. In one embodiment, each of the trenches 105 is parallel to each other in the direction D2 to simultaneously penetrate the plurality of second fins 110 extending in the direction D1, and each of the second fins 110 may be simultaneously penetrated by two trenches 105 if viewed from the top view shown in fig. 5, but is not limited thereto. The trench 105 may be formed by first providing a mask (not shown) on the substrate 100, the mask having at least one opening (not shown), wherein the opening partially exposes the plurality of second fins 110 and the shallow trench isolation 150, and performing at least one etching process to partially remove the exposed portions of the plurality of second fins 110 and the shallow trench isolation 150, thereby forming the trench 105. Accordingly, each trench 105 may simultaneously pass through the shallow trench isolation 150 and the plurality of second fins 110 to form a plurality of first fins 115 and shallow trench isolations 155, both of which have a reduced height within the trench 105 as shown in fig. 5-6. As shown in fig. 7, the plurality of first fins 115 are formed by etching portions of the plurality of second fins 110, and a maximum height H1 of the first fins 115 is significantly less than a maximum height H2 of the second fins 110, wherein the heights H1 and H2 of the first fins 115 and the second fins 110 can be considered as distances between the topmost surfaces of the first fins 115 and the second fins 110, respectively, and the topmost surface 101 of the substrate 100.

It is noted that during the etching process, the plurality of second fins 110 and the shallow trench isolations 150 may have different etching degrees because the etching rate may be different based on the materials of the plurality of second fins 110 and the shallow trench isolations 150. Thus, the bottom wall of each trench 105 located in the plurality of first fins 115 and the shallow trench isolation 155 may not be flush, e.g., as shown in fig. 6, the topmost surface of the plurality of first fins 115 may be relatively higher than the topmost surface of the shallow trench isolation 155. It should also be noted that the stress (material) layer 130 disposed on the exposed portions of the plurality of second fins 110 is also removed during the etching process, thereby forming a stress layer 130 that directly exposes the topmost surface of each first fin 115, as shown in fig. 6. In other words, after the etching process, as shown in fig. 7, the stress layer 130 covers the topmost surface and the side surfaces of each second fin 110, and as shown in fig. 6, the stress layer 130 covers only the side surfaces of each first fin 115, and the portion of each trench 105 located within the second fins 110 has an exposed sidewall 105a and an exposed bottom wall 105b (i.e., the topmost surface of each first fin 115).

Accordingly, as shown in fig. 8, an oxidation process, such as an ALD process or an ISSG process, is performed on all exposed surfaces of the plurality of second fins 110 and the plurality of first fins 115 to form an oxide layer 170. Specifically, the oxide layer 170 is formed by simultaneously consuming the underlying exposed surface, and thus the oxide layer 171 disposed on the side surface of each of the first fins 115 and the portion directly contacting the stress layer 130 may include the same elements as the stress layer 130. For example, although the stress layer 130 includes silicon germanium or germanium, and portions of the oxide layer 171 may beIncluding silicon germanium oxide (SiGeO)_x) Or germanium oxide (GeO)_x) But is not limited thereto. On the other hand, the oxide layer 173 disposed on the topmost surface of each of the first fins 115 and another portion directly contacting the plurality of first fins 115 may include the same element as the plurality of first fins 115, for example, including silicon oxide (SiO) including_x) And the plurality of first fins 115 includes, but is not limited to, silicon or a silicon-containing material. Likewise, although not shown in fig. 8, another portion of the oxide layer 171 (not shown in fig. 8, but shown in fig. 11) disposed on the topmost surface of each second fin 110 may also include the same elements as the underlying stress layer 130, and its material may thus be a silicon germanium oxide or a germanium oxide; and another portion of the oxide layer 173 (not shown in fig. 8, but shown in fig. 11) disposed on the exposed sidewalls 105a of each trench 105 may also include the same elements as the plurality of second fins 110, and thus, the material thereof may be, but is not limited to, silicon oxide.

It is noted that due to material differences between different portions of oxide layer 170 (i.e., the portion of oxide layer 171 and the another portion of oxide layer 173), oxide layer 170 may comprise different thicknesses between the different portions, such as, but not limited to, a thickness T2 of a portion of oxide layer 171 (e.g., comprising germanium oxide or silicon oxide) being greater than a thickness T3 of another portion of oxide layer 173 (e.g., comprising silicon oxide). Furthermore, after the oxidation process, the underlying stress layer 130 may thus comprise different elemental concentrations in different parts. For example, if the stress layer 130 comprises silicon germanium or germanium, various portions of the stress layer 130 may comprise different germanium concentrations after the oxidation process, wherein the stress layer 130 disposed below the oxide layer 170 (i.e., the portion of the oxide layer 171) has a relatively lower germanium concentration relative to the stress layer 130 disposed below the shallow trench isolation 155.

Thereafter, as shown in fig. 9-11, at least one gate structure 190 is formed within the trench 105 to fill the bottom of the trench 105, and then a capping layer 210 is formed over the gate structure 190 to fill the remaining portion of the trench 105. Those skilled in the art will readily recognize that the exact number of gate structures 190 may correspond to the actual number of trenches 105, such as, but not limited to, five as shown in fig. 9. As shown in fig. 10-11, each gate structure 190 extends in direction D2 to span the plurality of first fins 115 and the shallow trench isolations 155, and further includes a gate dielectric layer 191 and a gate electrode layer 193 stacked from bottom to top within each trench 105. In an embodiment, the gate structure 190 may be formed by conformally forming a dielectric layer (not shown in the figure, for example, comprising silicon oxide, silicon nitride or other suitable dielectric material) on the substrate 100 to cover at least a surface of each trench 105, then forming a conductive layer (not shown in the figure) on the dielectric layer to fill at least each trench 105, performing an etch-back process to partially remove the conductive layer and the dielectric layer filled in each trench 105 in the case of the conductive layer comprising, for example, a low resistance metal such as tungsten, aluminum or copper to form the gate dielectric layer 191 and the gate electrode layer 193, and then forming a capping layer 210 on the gate structure 190 to fill each trench 105.

Through these processes, the semiconductor device 300 according to the preferred embodiment of the present invention is obtained, which includes a plurality of gate lines (i.e., gate structures 190) embedded respectively in the plurality of second fins 110 and the shallow trench isolations 150 to behave as buried gate lines. Furthermore, after obtaining the structures shown in fig. 9-11, a plurality of conductive lines (not shown) and at least one capacitor (not shown) may be further formed on the topmost surface of the plurality of second fins 110, and the semiconductor device 300 may thus function as a memory device like a Dynamic Random Access Memory (DRAM) device, wherein each gate structure 190 functions like a Word Line (WL) and each conductive line functions like a Bit Line (BL) for receiving and transmitting signals in the dynamic random access memory array during operation. However, in another embodiment, other active elements may be formed on the plurality of second fins 110 in a subsequent process, and the semiconductor device 300 may thus perform various functions or performances as other semiconductor memory devices.

Referring further to fig. 11, a semiconductor device 300 according to a preferred embodiment of the present invention includes at least one trench 105 passing through the plurality of second fins 110 and the shallow trench isolations 150, and buried at the bottom of the at least one trench 105 to span at least one gate line (i.e., gate structure 190) of the plurality of first fins 115 and the shallow trench isolations 155 of reduced height. As can be seen from the cross-sectional view shown in fig. 11, the plurality of second fins 110 are disposed on both sides of the plurality of first fins 115, and the plurality of second fins 110, 115 are surrounded by the shallow trench isolations 150, and the maximum height H2 of the plurality of second fins 110 is greater than the maximum height H1 of the plurality of first fins 115. Specifically, the at least one gate line includes a gate dielectric layer 191 and a gate electrode layer 193 stacked from bottom to top, wherein the gate dielectric layer 191 is disposed between the plurality of first fins 115 and the gate electrode layer 193, and the gate dielectric layer 191 may include a U-shaped structure as shown by a cross-sectional view of fig. 11. Further, the semiconductor device 300 includes a stress layer 130 disposed on side surfaces of the plurality of first fins 115 and the topmost surface 101 of the substrate 100. The stress layer 130 preferably comprises a ge-containing layer that can produce suitable stress and a preferred lattice structure, and the ge-containing layer preferably comprises a material different from the substrate 100, including, for example, ge, sige, and the like. In this way, the channel of the at least one gate line may thus obtain a suitable stress and a better lattice structure, thereby improving the electron mobility and performance of the driving current. Furthermore, as shown in fig. 11, the stress layer 130 is also disposed on the topmost surface and the side surfaces of the plurality of second fins 110, because the formation of the stress layer 130 is prior to the formation of the shallow trench isolation 150, and the germanium concentration within the stress layer 130 may be different for different profiles, e.g., a relatively lower concentration at the upper portion and a relatively higher concentration at the bottom portion or no residue.

In addition, the semiconductor device 300 further includes an oxide layer 170, the oxide layer 170 being formed by simultaneously consuming exposed surfaces thereunder, such as exposed surfaces of the stress layer 130 or the plurality of second fins 110, 115. Accordingly, a portion of the oxide layer 171 may also include germanium and be disposed on the side surfaces of the first fins 115 and the top-most surfaces of the second fins 110 to have an L-shaped structure as shown in fig. 11. On the other hand, another portion of the oxide layer 173 may also include silicon and is disposed on the topmost surface of the plurality of first fins 115 (also referred to as the bottom wall of the trench 105) and the sidewalls of the trench 105 to form a U-shaped structure between the gate structure 190 and the plurality of second fins 110, 115 within each trench 105, as shown in fig. 10-11. In this way, different portions of oxide layer 170 (i.e., the portion of oxide layer 171 and the other portion of oxide layer 173) may include different materials and different thicknesses T2, T3. In an embodiment, a portion of oxide layer 171 may comprise silicon germanium oxide or germanium oxide, and another portion of oxide layer 173 may comprise, but is not limited to, silicon oxide.

Those skilled in the art will readily recognize that the semiconductor device and the method of forming the same in the present invention are not limited to the above-described embodiments, and may also include other examples or variations. The following description will describe in detail various embodiments of the semiconductor device and the method of forming the same in the present invention. In order to simplify the description, the following description will explain differences between different embodiments in detail, and the same features will not be repeated. In order to easily compare differences between the embodiments, the same components in each of the following embodiments are labeled with the same symbols.

Referring to fig. 12-13, a method of forming a semiconductor device according to a second preferred embodiment of the present invention is shown. The previous steps of this embodiment are substantially the same as those of the first preferred embodiment, and will not be described again. The difference between the aforementioned first preferred embodiment and the present embodiment is that a portion of the shallow trench isolation 150a of the present embodiment includes a three-layer structure, wherein the three-layer structure includes an oxide layer 152, a first isolation layer 151, and a second isolation layer 153. As shown in fig. 12, the oxide layer 152 is formed by an ALD process or an ISSG process and at least a portion of the elements (e.g., germanium, silicon germanium) within the stress layer 130 are consumed and oxidized to form the oxide layer 152 (e.g., comprising germanium, silicon germanium). Thereafter, the trenches 105 are formed by partially removing the plurality of second fins 110 and the shallow trench isolations 150a (including the oxide layer 152, the first isolation layer 151, and the second isolation layer 153), and thereby the plurality of first fins 115 and the shallow trench isolations 155a having reduced heights as shown in fig. 13 are formed. Then, similar to fig. 7-11 of the first preferred embodiment described above, the oxide layer 170 and the gate structure 190 may be further formed in subsequent processes to span the plurality of first fins 115. However, in another embodiment, the oxide layer 152 and the isolation layer (including the first isolation layer 151 and the second isolation layer 153) may have different etching degrees when forming the trench 105, and thus, the plurality of first fins 115 and the shallow trench isolations 155b are formed, in which the oxide layer 152 remains on the entire side surfaces of the plurality of fins 155 to protrude from the topmost surface portions of the first isolation layer 151 and the second isolation layer 153 as shown in fig. 14. In another embodiment, an oxide layer (not shown in the drawings) formed in a subsequent oxidation process may be disposed on the oxide layer 152, the oxide layer 152 protruding from the topmost surfaces of the first and second isolation layers 151 and 153, and may be optionally combined with the oxide layer 152.

Thus, the semiconductor device formed in the present embodiment includes a germanium-containing layer (e.g., stress layer 130, oxide layer 171, or oxide layer 152) disposed on the side surfaces of the plurality of first fins 115 to provide appropriate stress and an improved lattice structure to the channel. Then, the semiconductor device of the present embodiment is allowed to obtain a larger electron mobility, and achieve a better function and performance.

Referring to fig. 15, a method for forming a semiconductor device 500 according to a third preferred embodiment of the present invention is shown. The previous steps of this embodiment are substantially the same as those of the first preferred embodiment, and will not be described again. The difference between the foregoing first preferred embodiment and this embodiment is that a portion of the oxide layer 171a in this embodiment is formed by fully consuming and oxidizing the underlying stress layer 130, thereby achieving a greater thickness T4. Accordingly, as shown in fig. 15, the oxide layer 170a of the present embodiment includes a first portion (i.e., oxide layer 173) directly disposed on the topmost surface of the plurality of first fins 115 and a second portion (i.e., oxide layer 171a) directly disposed on the side surfaces of the plurality of first fins 115, wherein the first portion 173 and the second portion 171a include different materials and thicknesses T3, T4, respectively. In the present embodiment, the first portion 173 includes, for example, silicon oxide, and the second portion 171a includes, for example, germanium oxide or silicon oxide, but is not limited thereto. Subsequently, a gate electrode layer 193 is formed to fill the bottom of the trench 105, and then a cap layer 210 is formed on the gate electrode layer 193 to fill the remaining portion of the trench 105. Then, the gate electrode layer 193 and the oxide layer 170a may together form a gate structure 190 a. In other words, the gate dielectric layer 191 of the first preferred embodiment is omitted in the present embodiment, and the oxide layer 170a formed in the present embodiment is disposed between the gate electrode layer 193 and the plurality of first fins 115, i.e., can be used as the gate dielectric layer of the gate structure 190 a.

Thus, the semiconductor device 500 formed in the present embodiment further includes a germanium-containing layer (e.g., oxide layer 171a) disposed on the side surfaces of the plurality of first fins 115 to provide appropriate stress and an improved lattice structure to the channel. Then, the semiconductor device 500 of the present embodiment is allowed to obtain a greater electron mobility, achieving better function and performance.

In general, the semiconductor device of the present invention includes a ge-containing layer disposed on side surfaces of a plurality of fins, and a gate line straddling the plurality of fins, the ge-containing layer creating an appropriate stress and a preferred lattice structure for a channel thereof. Germanium-containing layers, for example, include germanium, silicon germanium, germanium oxide (GeO)_x) Silicon germanium oxide (SiGeO)_x) Or other suitable materials, thereby allowing greater electron mobility and hence better function and performance of the semiconductor device of the present invention.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (12)

1. A semiconductor device, comprising:

a substrate having a plurality of first fins protruding from the substrate;

a gate line crossing the plurality of first fins and including:

a gate electrode layer; and

a gate dielectric layer disposed between the gate electrode layer and the plurality of first fins; and

a stress layer disposed only on side surfaces of the plurality of first fins and on a topmost surface of the substrate, wherein a material of the stress layer is different from a material of the plurality of first fins.

2. The semiconductor device of claim 1, further comprising an oxide layer between the gate line and the plurality of first fins, wherein the oxide layer comprises a first portion disposed on the topmost surface of the plurality of first fins and a second portion disposed on the side surface of the plurality of first fins.

3. The semiconductor device of claim 2, wherein the first portion and the second portion comprise different materials.

4. The semiconductor device of claim 2, wherein the first portion and the second portion comprise different thicknesses.

5. The semiconductor device of claim 2, wherein the second portion directly contacts the stress layer disposed on the side surface of the plurality of first fins and the first portion directly contacts the plurality of first fins.

6. The semiconductor device of claim 2, wherein the second portion comprises the same element as the stress layer.

7. The semiconductor device of claim 1, further comprising the plurality of second fins protruding from the substrate, wherein a maximum height of the plurality of second fins is greater than a maximum height of the plurality of first fins.

8. The semiconductor device of claim 7, further comprising shallow trench isolation surrounding the plurality of first fins and the plurality of second fins, wherein the shallow trench isolation is located on the stress layer disposed on the topmost surface of the substrate.

9. The semiconductor device of claim 6, wherein the stress layer comprises silicon germanium or germanium.

10. A semiconductor device, comprising:

a substrate having a plurality of first fins protruding from the substrate;

a gate line disposed on the substrate, crossing the plurality of first fins and including:

a gate electrode layer; and

a gate dielectric layer disposed between the gate electrode layer and the plurality of first fins,

wherein the gate dielectric layer includes a first portion disposed on a topmost surface of the plurality of first fins and a second portion disposed on a side surface of the plurality of first fins, and the second portion includes silicon germanium oxide or germanium oxide.

11. The semiconductor device of claim 10, wherein the first portion and the second portion comprise different thicknesses.

12. The semiconductor device according to claim 10, further comprising:

a plurality of second fins protruding from the substrate, wherein a maximum height of the plurality of second fins is greater than a maximum height of the plurality of first fins; and

shallow trench isolation surrounding the plurality of first fins and the plurality of second fins.

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