CN117712124A - High-performance CMOS device based on 4H-SiC substrate - Google Patents
High-performance CMOS device based on 4H-SiC substrate Download PDFInfo
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- CN117712124A CN117712124A CN202410160894.4A CN202410160894A CN117712124A CN 117712124 A CN117712124 A CN 117712124A CN 202410160894 A CN202410160894 A CN 202410160894A CN 117712124 A CN117712124 A CN 117712124A
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- 239000000758 substrate Substances 0.000 title claims abstract description 50
- 239000004065 semiconductor Substances 0.000 claims abstract description 5
- 238000002955 isolation Methods 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 17
- 238000000137 annealing Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 9
- 229910002704 AlGaN Inorganic materials 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 229910052682 stishovite Inorganic materials 0.000 claims description 5
- 229910052905 tridymite Inorganic materials 0.000 claims description 5
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 229910005091 Si3N Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910018885 Pt—Au Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003208 petroleum Substances 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to the technical field of semiconductor devices, and particularly discloses a high-performance CMOS device based on a 4H-SiC substrate, which comprises the 4H-SiC substrate, an NMOS channel, a PMOS epitaxial layer, a PMOS channel, an NMOS ohmic electrode and a PMOS ohmic electrode.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a high-performance CMOS device based on a 4H-SiC substrate.
Background
CMOS (complementary metal oxide semiconductor) is the mainstream technology of the present-stage large-scale integrated circuit, and has many advantages such as low power consumption, low power supply voltage, high speed, strong anti-interference capability, high integration level, etc., so CMOS devices are widely used in various fields such as temperature sensors, image sensors, radio frequency power amplifiers, etc. At present, with the rapid development of the high-precision technology industry, some basic industries such as metallurgical chemical industry and petroleum exploration need to be performed in a high-temperature environment, and higher requirements are put on the performance of electronic equipment, so that an electronic device capable of keeping stable at a high temperature is particularly important. In addition, since the advent of silicon chip technology, transistor channels have been shrinking as device dimensions have been shrinking. However, quantum tunneling is very likely to occur after the channel is shortened to some extent, and thus a suitable structure is required to provide a smaller leakage current.
Disclosure of Invention
The invention aims to provide a high-performance CMOS device based on a 4H-SiC substrate, which is prepared on the same 4H-SiC substrate and provides smaller leakage current, smaller gate delay and larger current driving capability by utilizing a FinFET structure.
In order to solve the technical problems, the technical scheme of the invention is as follows:
in a first aspect, the invention provides a high-performance CMOS device based on a 4H-SiC substrate, which comprises a 4H-SiC substrate 1, an NMOS channel, a PMOS epitaxial layer, a PMOS channel, an NMOS ohmic electrode 10 and a PMOS ohmic electrode 11,4H-SiC substrate 1, wherein the NMOS channel and the PMOS epitaxial layer are connected, the PMOS epitaxial layer is provided with the PMOS channel, the NMOS Schottky gate electrode 8 is arranged above the NMOS channel, the PMOS Schottky gate electrode 9 is arranged above the PMOS channel, the NMOS ohmic electrode 10 is arranged on two sides of the top of the NMOS channel, and the PMOS ohmic electrode 11 is arranged on two sides of the top of the PMOS channel; the NMOS channel comprises an NMOS fin 2 and an NMOS isolation layer 6, and the NMOS isolation layer 6 is arranged on the top of the NMOS fin 2; the PMOS channel comprises a PMOS fin 5 and a PMOS isolation layer 7, and the PMOS isolation layer 7 is arranged on the top of the PMOS fin 5; the PMOS epitaxial layer comprises an epitaxial layer I3 and an epitaxial layer II 4, and the epitaxial layer II 4 is arranged on the top surface of the epitaxial layer I3.
Preferably, the NMOS fin 2 includes 2 fins, the PMOS fin 5 includes 2 fins, and the NMOS schottky gate electrode 8 and the PMOS schottky gate electrode 9 are fin structures.
Preferably, fin tops of the NMOS fin 2 and the PMOS fin 5 are rounded, fin thicknesses of the NMOS fin 2 and the PMOS fin 5 are 10-50nm, and fin heights of the NMOS fin 2 and the PMOS fin 5 are 100-200nm.
Preferably, the fin thickness of the NMOS fin 2 and the PMOS fin 5 is 30nm, and the fin height of the NMOS fin 2 and the PMOS fin 5 is 150nm.
Preferably, the first epitaxial layer 3 and the second epitaxial layer 4 are undoped semiconductors, the thickness of the first epitaxial layer 3 is 100-300nm, and the thickness of the second epitaxial layer 4 is 200-500nm.
Preferably, the thickness of the first epitaxial layer 3 is 200nm, and the thickness of the second epitaxial layer 4 is 300nm.
Preferably, the material of the first epitaxial layer 3 is GaN, and the material of the second epitaxial layer 4 is any one of GaN and AlGaN.
Preferably, the ion doping concentration of the epitaxial layer one 3 is 1X 1018-1X 1020cm-3.
Preferably, the thickness of the NMOS isolation layer 6 and the PMOS isolation layer 7 is 10-50nm.
Preferably, the thickness of the NMOS isolation layer 6 and the PMOS isolation layer 7 is 20nm.
Preferably, the material of the NMOS isolation layer 6 and the PMOS isolation layer 7 is any one of SiO2 and Si3N4 or a combination of SiO2 and Si3N 4.
Preferably, the NMOS fin 2 is made of any one of 4H-SiC or SiC, the PMOS fin 5 is made of AlGaN, the NMOS schottky gate electrode 8 is made of any one of Ni metal or Ni-Ti-Au metal stack, the PMOS schottky gate electrode 9 is made of any one of Ni-Au metal stack and Pt-Au metal stack, the NMOS ohmic electrode 10 is made of Ti-Al-Ni-Au metal stack, and the PMOS ohmic electrode 11 is made of Ni metal.
More preferably, the ion doping concentration of the PMOS fin 5 is 1×1016-1×1017cm-3.
More preferably, the ni—ti—au metal stack is a metal stack of Ni, ti, and Au in order from the bottom end surface to the top end surface, and the ni—au metal stack is a metal stack of Ni, and Au in order from the bottom end surface to the top end surface.
In a second aspect, the present invention provides a method for fabricating a high performance CMOS device based on a 4H-SiC substrate, comprising the steps of:
1. growing an NMOS fin layer, an epitaxial layer I, an epitaxial layer II and a PMOS fin layer on the 4H-SiC substrate by adopting a thermal oxidation method;
2. adopting a photoetching developing method and a dry etching method to realize the electric isolation of the NMOS fin layer and the epitaxial layer I, the epitaxial layer II and the PMOS fin layer;
3. carrying out dry etching on the NMOS fin layer to obtain NMOS fins, and annealing in a high-temperature hydrogen atmosphere;
4. carrying out dry etching on the PMOS fin layer to obtain a PMOS fin, and annealing in a high-temperature hydrogen atmosphere;
5. oxidizing and depositing an NMOS isolation layer above the NMOS fins, and annealing to obtain an NMOS channel;
6. oxidizing and depositing a PMOS isolation layer above the PMOS fins, and annealing to obtain a PMOS channel;
7. forming an NMOS Schottky gate electrode above the NMOS channel and forming a PMOS Schottky gate electrode above the PMOS channel by adopting an oxidation deposition method or an electron beam evaporation method;
8. and forming NMOS ohmic electrodes on two sides above the NMOS channel by adopting an electron beam evaporation method or a magnetron sputtering method, and forming PMOS ohmic electrodes on two sides above the PMOS channel to obtain the high-performance CMOS device based on the 4H-SiC substrate.
Preferably, in step 4, the high temperature is 1100 ℃ to 1200 ℃.
Preferably, in step 5, the high temperature is 1100 ℃ to 1200 ℃.
By adopting the technical scheme, the method has the following beneficial effects:
(1) The invention provides a high-performance CMOS device based on a 4H-SiC substrate, which adopts a FinFET structure, so that not only is the short channel effect inhibited, but also the carrier mobility is improved, the gate control capability is stronger, and the application field is wider;
(2) The invention provides a high-performance CMOS device based on a 4H-SiC substrate, which adopts a 4H-SiC material with a larger forbidden bandwidth as a substrate, and the 4H-SiC material has higher thermal conductivity and can radiate heat, so that the radiating pressure of the CMOS device can be relieved, and the CMOS device with the 4H-SiC substrate has the capability of stably working at high temperature;
(3) The invention provides a high-performance CMOS device based on a 4H-SiC substrate, wherein the tops of NMOS fins and PMOS fins are round, which is beneficial to improving the subthreshold performance of the device.
Drawings
FIG. 1 is a front view of a high performance CMOS device based on a 4H-SiC substrate of example 1;
FIG. 2 is a cross-sectional view of A-A of a high performance CMOS device based on a 4H-SiC substrate of example 1;
fig. 3 is a B-B cross-sectional view of a 4H-SiC substrate based high performance CMOS device of example 1.
In the figure: 1-4H-SiC substrate, 2-NMOS fin, 3-epitaxial layer I, 4-epitaxial layer II, 5-PMOS fin, 6-NMOS isolation layer, 7-PMOS isolation layer, 8-NMOS Schottky gate electrode, 9-PMOS Schottky gate electrode, 10-NMOS ohmic electrode and 11-PMOS ohmic electrode.
Detailed Description
The following describes the embodiments of the present invention further with reference to the drawings. The description of these embodiments is provided to assist understanding of the present invention, but is not intended to limit the present invention. In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
Example 1
The embodiment provides a high-performance CMOS device based on a 4H-SiC substrate, which comprises a 4H-SiC substrate 1, an NMOS channel, a PMOS epitaxial layer, a PMOS channel, an NMOS ohmic electrode 10 and a PMOS ohmic electrode 11,4H-SiC substrate 1, wherein the NMOS channel and the PMOS epitaxial layer are connected, the PMOS epitaxial layer is provided with the PMOS channel, the NMOS Schottky gate electrode 8 is arranged above the NMOS channel, the PMOS Schottky gate electrode 9 is arranged above the PMOS channel, the NMOS ohmic electrode 10 is arranged on two sides of the top of the NMOS channel, and the PMOS ohmic electrode 11 is arranged on two sides of the top of the PMOS channel; the NMOS channel comprises an NMOS fin 2 and an NMOS isolation layer 6, and the NMOS isolation layer 6 is arranged on the top of the NMOS fin 2; the PMOS channel comprises a PMOS fin 5 and a PMOS isolation layer 7, and the PMOS isolation layer 7 is arranged on the top of the PMOS fin 5; the PMOS epitaxial layer comprises an epitaxial layer I3 and an epitaxial layer II 4, the epitaxial layer II 4 is arranged on the top surface of the epitaxial layer I3, and the epitaxial layer II 4 is arranged above the epitaxial layer I3, and the structure elevation view of the PMOS epitaxial layer is shown in figure 1.
The NMOS fins 2 and 5 comprise 2 fins, the tops of the NMOS fins 2 and the PMOS fins 5 are round, the thicknesses of the NMOS fins 2 and the PMOS fins 5 are 30nm, and the heights of the NMOS fins 2 and the PMOS fins 5 are 150nm.
Wherein the first epitaxial layer 3 is GaN with ion doping concentration of 1X 1018cm < -3 > and thickness of 200nm; the material of the second epitaxial layer 4 is AlGaN, and the thickness is 300nm.
Wherein the thickness of the NMOS isolation layer 6 and the PMOS isolation layer 7 is 20nm, and the materials of the NMOS isolation layer 6 and the PMOS isolation layer 7 are a combination of SiO2 and Si3N 4.
Wherein, the NMOS fin 2 is made of 4H-SiC, the PMOS fin 5 is made of GaN with ion doping concentration of 1X 1016cm < -3 >, the NMOS Schottky gate electrode 8 is made of Ni-Ti-Au metal lamination, the PMOS Schottky gate electrode 9 is made of Ni-Au metal lamination, the NMOS ohmic electrode 10 is made of Ti-Al-Ni-Au metal lamination, and the PMOS ohmic electrode 11 is made of Ni metal.
A cross-sectional view of a high performance CMOS device based on a 4H-SiC substrate in example 1 is shown in fig. 2, and it can be seen from fig. 2 that after the high performance CMOS device based on a 4H-SiC substrate is cut from A-A, the 4H-SiC substrate 1, the NMOS fin 2, the NMOS isolation layer 6 and the NMOS schottky gate electrode 8 are from bottom to top.
The cross-sectional view of the B-B of the high-performance CMOS device based on the 4H-SiC substrate in example 1 is shown in fig. 3, and it can be seen from fig. 2 that the high-performance CMOS device based on the 4H-SiC substrate is a 4H-SiC substrate 1, an epitaxial layer one 3, an epitaxial layer two 4, a PMOS fin 5, a PMOS isolation layer 7 and a PMOS schottky gate electrode 9 from bottom to top after being cut from the B-B.
Example 2
The embodiment provides a high-performance CMOS device based on a 4H-SiC substrate, which is different from embodiment 1 in that the thicknesses of the fins of an NMOS fin 2 and a PMOS fin 5 are 10nm, the heights of the fins of the NMOS fin 2 and the PMOS fin 5 are 100nm, and the material of the PMOS fin 5 is GaN with ion doping concentration of 1X 1017cm < -3 >; the first epitaxial layer 3 is GaN with ion doping concentration of 1 multiplied by 1020cm < -3 > and thickness of 100nm; the second epitaxial layer 4 is made of AlGaN and has a thickness of 200nm; the thickness of the NMOS isolation layer 6 and the PMOS isolation layer 7 is 10nm.
Example 3
The present embodiment provides a high performance CMOS device based on a 4H-SiC substrate, which is different from embodiment 1 in that the thicknesses of the fins of the NMOS fin 2 and the PMOS fin 5 are 50nm, and the heights of the fins are 200nm; the PMOS fin 5 is made of GaN with ion doping concentration of 1X 1017cm < -3 >; the first epitaxial layer 3 is GaN with ion doping concentration of 1 multiplied by 1020cm < -3 > and thickness of 300nm; the second epitaxial layer 4 is made of AlGaN and has a thickness of 500nm; the thickness of the NMOS isolation layer 6 and the PMOS isolation layer 7 is 50nm.
Example 4
The embodiment provides a preparation method of a high-performance CMOS device based on a 4H-SiC substrate, which comprises the following steps:
1. growing an NMOS fin layer, an epitaxial layer I, an epitaxial layer II and a PMOS fin layer on the 4H-SiC substrate by adopting a thermal oxidation method;
2. adopting a photoetching developing method and a dry etching method to realize the electric isolation of the NMOS fin layer and the epitaxial layer I, the epitaxial layer II and the PMOS fin layer;
3. carrying out dry etching on the NMOS fin layer to obtain an NMOS fin, and annealing in a hydrogen atmosphere at 1100-1200 ℃;
4. dry etching is adopted to the PMOS fin layer to obtain a PMOS fin, and annealing is carried out in a hydrogen atmosphere at 1100-1200 ℃;
5. oxidizing and depositing an NMOS isolation layer above the NMOS fins, and annealing to obtain an NMOS channel;
6, oxidizing and depositing a PMOS isolation layer above the PMOS fins, and annealing to obtain a PMOS channel;
7. forming an NMOS Schottky gate electrode above the NMOS channel and forming a PMOS Schottky gate electrode above the PMOS channel by adopting an oxidation deposition method or an electron beam evaporation method;
8. and forming NMOS ohmic electrodes on two sides above the NMOS channel by adopting an electron beam evaporation method or a magnetron sputtering method, and forming PMOS ohmic electrodes on two sides above the PMOS channel to obtain the high-performance CMOS device based on the 4H-SiC substrate.
The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. It will be apparent to those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, and yet fall within the scope of the invention.
Claims (10)
1. The high-performance CMOS device based on the 4H-SiC substrate is characterized by comprising a 4H-SiC substrate (1), an NMOS channel, a PMOS epitaxial layer, a PMOS channel, NMOS ohmic electrodes (10) and PMOS ohmic electrodes (11), wherein the 4H-SiC substrate (1) is connected with the NMOS channel and the PMOS epitaxial layer, the PMOS epitaxial layer is provided with the PMOS channel, the NMOS Schottky gate electrode (8) is arranged above the NMOS channel, the PMOS Schottky gate electrode (9) is arranged above the PMOS channel, the NMOS ohmic electrodes (10) are arranged on two sides of the top of the NMOS channel, and the PMOS ohmic electrodes (11) are arranged on two sides of the top of the PMOS channel;
the NMOS channel comprises an NMOS fin (2) and an NMOS isolation layer (6), and the NMOS isolation layer (6) is arranged at the top of the NMOS fin (2); the PMOS channel comprises a PMOS fin (5) and a PMOS isolation layer (7), and the PMOS isolation layer (7) is arranged at the top of the PMOS fin (5); the PMOS epitaxial layer comprises an epitaxial layer I (3) and an epitaxial layer II (4), and the epitaxial layer II (4) is arranged on the top surface of the epitaxial layer I (3).
2. The high performance CMOS device based on a 4H-SiC substrate according to claim 1, characterized in that the NMOS fin (2) comprises 2 fins, the PMOS fin (5) comprises 2 fins, the NMOS schottky gate electrode (8) and the PMOS schottky gate electrode (9) are fin-like structures.
3. The high performance CMOS device based on a 4H-SiC substrate according to claim 2, wherein the fin tops of the NMOS fin (2) and the PMOS fin (5) are rounded, the fin thickness of the NMOS fin (2) and the PMOS fin (5) is 10-50nm, and the fin heights of the NMOS fin (2) and the PMOS fin (5) are 100-200nm.
4. A high performance CMOS device based on a 4H-SiC substrate according to claim 3, characterized in that the fin thickness of the NMOS fin (2) and the PMOS fin (5) is 30nm, and the fin height of the NMOS fin (2) and the PMOS fin (5) is 150nm.
5. The high performance CMOS device based on a 4H-SiC substrate according to any one of claims 1 to 4, wherein the first epitaxial layer (3) and the second epitaxial layer (4) are undoped semiconductors, the thickness of the first epitaxial layer (3) is 100-300nm, and the thickness of the second epitaxial layer (4) is 200-500nm.
6. The high performance CMOS device based on a 4H-SiC substrate according to claim 5, wherein the thickness of the first epitaxial layer (3) is 200nm and the thickness of the second epitaxial layer (4) is 300nm.
7. The high-performance CMOS device based on a 4H-SiC substrate according to claim 5, wherein the material of the first epitaxial layer (3) is GaN, and the material of the second epitaxial layer (4) is either GaN or AlGaN.
8. High performance CMOS device based on a 4H-SiC substrate according to claim 5, characterized in that the thickness of the NMOS isolation layer (6) and the PMOS isolation layer (7) is 10-50nm.
9. The high-performance CMOS device based on a 4H-SiC substrate according to claim 1, wherein the material of the NMOS fin (2) is any one of 4H-SiC or SiC, the material of the PMOS fin (5) is GaN, the material of the NMOS isolation layer (6) and the PMOS isolation layer (7) is any one of SiO2, si3N4 or a combination of SiO2, si3N4, the material of the NMOS schottky gate electrode (8) is any one of Ni metal or Ni-Ti-Au metal stack, the material of the PMOS schottky gate electrode (9) is any one of Ni-Au metal stack, pt-Au metal stack, the material of the NMOS ohmic electrode (10) is Ti-Al-Ni-Au metal stack, and the material of the PMOS ohmic electrode (11) is Ni metal.
10. A method of manufacturing a high performance CMOS device based on a 4H-SiC substrate according to any one of claims 1 to 9, comprising the steps of:
(1) Growing an NMOS fin layer, an epitaxial layer I, an epitaxial layer II and a PMOS fin layer on a 4H-SiC substrate by adopting a thermal oxidation method;
(2) Adopting a photoetching developing method and a dry etching method to realize the electric isolation of the NMOS fin layer and the epitaxial layer I, the epitaxial layer II and the PMOS fin layer;
(3) Carrying out dry etching on the NMOS fin layer to obtain NMOS fins, and annealing in a high-temperature hydrogen atmosphere;
(4) Carrying out dry etching on the PMOS fin layer to obtain a PMOS fin, and annealing in a high-temperature hydrogen atmosphere;
(5) Oxidizing and depositing an NMOS isolation layer above the NMOS fins, and annealing to obtain an NMOS channel;
(6) Oxidizing and depositing a PMOS isolation layer above the PMOS fins, and annealing to obtain a PMOS channel;
(7) Forming an NMOS Schottky gate electrode above the NMOS channel and forming a PMOS Schottky gate electrode above the PMOS channel by adopting an oxidation deposition method or an electron beam evaporation method;
(8) And forming NMOS ohmic electrodes on two sides above the NMOS channel by adopting an electron beam evaporation method or a magnetron sputtering method, and forming PMOS ohmic electrodes on two sides above the PMOS channel to obtain the high-performance CMOS device based on the 4H-SiC substrate.
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