CN117690904A - Antifuse array and memory - Google Patents

Abstract

The embodiment of the disclosure relates to the field of memories, and provides an antifuse array and a memory. The antifuse array includes: at least one column of first active regions arranged along a first direction, wherein the end parts of the first active regions are provided with first concave parts, and the first active regions comprise first programming regions and second programming regions which are positioned at two sides of the first concave parts in a third direction; at least one row of second active regions arranged along the first direction, wherein the end parts of the second active regions are provided with second recesses, and the second active regions comprise third programming regions and fourth programming regions which are positioned at two sides of the second recesses in the third direction; the second programming region is located in the second recess, and the third programming region is located in the first recess; the programming grid line covers each first programming area and each second programming area in a row of first active areas, and also covers each third programming area and each fourth programming area in a row of second active areas. The antifuse array can at least improve the memory integration level and the programming success rate of the memory.

Description

Antifuse array and memory

Technical Field

The embodiment of the disclosure relates to the field of memories, in particular to an antifuse array and a memory.

Background

With the continuous progress and development of microelectronic technology, the types of memories are increasing, and the current Memory types are mainly classified into two types, namely RAM (Ramdom Access Memory, random access Memory) and ROM (Read Only Memory). In many applications, since some data, such as a cache or a memory of a computer, does not need to be stored for a long period of time, a volatile memory (e.g., RAM) has a characteristic (volatile) of disappearing data after power failure, but a conventional nonvolatile memory is relatively complex in structure and high in cost. Therefore, selecting an OTP (one-Time programmable ) memory not only provides low power consumption performance, but also can meet the requirements of a nonvolatile memory. The one-time programmable memory may include a fuse type FPGA (Field Programmable Gate Array, field-programmable gate array) or an antifuse type FPGA.

Fuse (Fuse) programming technology uses fuses as switching elements that are normally (when not programmed) in a connected state, and when power-up programming is performed, the fuses are blown at the locations where no connection is needed, and the Fuse pattern remaining in the device determines the logic function of the corresponding device. Antifuse (Anti-fuse) programming techniques are also known as fuse programming techniques, and such devices use antifuses as switching elements. When the switch element is in an open circuit state in the non-programming process, programming voltage is added to two ends of the anti-fuse switch element at the position where the anti-fuse switch element is required to be connected, the anti-fuse is changed from high impedance to low impedance, connection between two points is realized, and the anti-fuse mode in the device after programming determines the logic function of the corresponding device.

Among them, the antifuse type FPGA has been paid more and more attention to its advantages of non-volatility, low power consumption, high integration level, stable performance, total dose resistance, and the like. However, there is room for improvement in the integration level and programming success rate of antifuse arrays.

Disclosure of Invention

The embodiment of the disclosure provides an antifuse array and a memory, which are at least beneficial to improving the integration level and the programming success rate of the memory.

According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides an antifuse array, including: at least one column of first active regions arranged along a first direction, the first active regions extending along a second direction, the end parts of the first active regions having first recesses, the first active regions including first programming regions and second programming regions located on both sides of the first recesses in a third direction; at least one row of second active regions arranged along the first direction, the second active regions extending along the second direction, the end parts of the second active regions having second recesses, the second active regions including third and fourth programming regions located at both sides of the second recesses in the third direction; the second programming region is at least partially located within the second recess, and the third programming region is at least partially located within the first recess; the programming grid line extends along the first direction, covers each first programming region and each second programming region in a column of first active regions, and also covers each third programming region and each fourth programming region in a column of second active regions; the first direction is intersected with the second direction and the third direction, and the second direction is perpendicular to the third direction.

In some embodiments, the included angle between the first direction and the third direction ranges from [20 °,70 ° ].

In some embodiments, the width of the first active region is equal to the width of the second active region in the third direction.

In some embodiments, the width of the first programming region is greater than the width of the second programming region in the third direction; in the third direction, the width of the fourth programming region is greater than the width of the third programming region.

In some embodiments, the width of the second programming region is equal to the width of the third programming region; the width of the first programming region is equal to the width of the fourth programming region.

In some embodiments, the ratio of the width of the second programming region to the width of the first active region in the third direction ranges from 1/15 to 1/5.

In some embodiments, the first active region further comprises: the first channel region, and the first source drain region and the second source drain region which are positioned at two sides of the first channel region; the second active region further includes: the second channel region, the third source drain region and the fourth source drain region are positioned on two sides of the second channel region; the antifuse array further comprises: a first gate line extending in a first direction, the first gate line covering each first channel region in a column of first active regions; and the second grid line extends along the first direction and covers each second channel region in a row of second active regions.

In some embodiments, the first active region further comprises: the third channel region, the fifth source drain region and the sixth source drain region which are positioned at two sides of the third channel region, and the third recess are positioned at the end part of the first active region opposite to the first recess.

In some embodiments, the first active region includes a fifth programming region located on both sides of the third recess in the third direction and a sixth programming region, the fifth programming region being opposite the second programming region.

In some embodiments, the width of the fifth programming region is less than the width of the sixth programming region in the third direction.

In some embodiments, the planar shape of the first active region is a centrally symmetric pattern.

In some embodiments, the second active region further comprises: the fourth channel region, a seventh source drain region, an eighth source drain region and a fourth recess are arranged on two sides of the fourth channel region; the planar shape of the second active region is a center symmetrical pattern.

In some embodiments, the first active region and the second active region have the same shape and size.

In some embodiments, the first channel region is electrically connected to the third channel region by a second source drain region and a fifth source drain region, the second source drain region and the fifth source drain region together forming a bit line connection region.

In some embodiments, the first active region includes a central region and a peripheral region along a fourth direction, the first programming region being located at the peripheral region, the fourth direction being parallel to the first active region surface and mutually perpendicular to the first direction; in the third direction, the spacing between adjacent peripheral regions is the same as the spacing between adjacent central regions.

In some embodiments, the first active region further comprises: the first gate dielectric layer is positioned in the peripheral area, the second gate dielectric layer is positioned in the central area, and the thickness of the first gate dielectric layer is smaller than that of the second gate dielectric layer.

According to some embodiments of the present disclosure, there is also provided, in another aspect, a memory including an antifuse array according to any of the above embodiments.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

in the technical scheme provided by the embodiment of the disclosure, the first active region comprises a first programming region and a second programming region which are positioned at two sides of the first recess in the third direction, and the second active region comprises a third programming region and a fourth programming region which are positioned at two sides of the second recess in the third direction. The second programming region is at least partially positioned in the second recess, the third programming region is at least partially positioned in the first recess, namely, in the same device area, the first active region and the second active region are clamped through the first recess and the second recess, so that the space utilization rate can be improved, the quantity of antifuses in a device in unit area can be increased, and the programming success rate is improved; the method can also realize dense stacking, reduce or avoid distortion of the first active region and the second active region during exposure of the programming region, expand the first active region and the second active region to reach target values, expand the space utilization ratio and realize the miniaturization of the device.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

FIG. 1 is a schematic diagram of an antifuse array;

FIG. 2 is a schematic diagram of another configuration of an antifuse array;

FIG. 3 is a schematic diagram of an antifuse array according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a partial structure of an antifuse array according to an embodiment of the present disclosure;

FIG. 5 is a schematic cross-sectional view of an antifuse array according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of a first active region according to an embodiment of the present disclosure;

fig. 7 is a schematic cross-sectional structure of a first active region according to an embodiment of the disclosure;

FIG. 8 is a schematic diagram of a structure of a second active region according to an embodiment of the present disclosure;

FIG. 9 is an antifuse circuit diagram of an antifuse array provided by an embodiment of the present disclosure;

fig. 10 to 13 are schematic structural diagrams corresponding to each step of a method for manufacturing an antifuse array according to an embodiment of the present disclosure.

Detailed Description

FIG. 1 is a schematic diagram of an antifuse array; fig. 2 is a schematic diagram of another structure of an antifuse array, fig. 1 is a schematic diagram of a prior structure of an active region formed by etching, and fig. 2 is a schematic diagram of an actual structure of an antifuse array. Referring now to fig. 1 and 2, the antifuse array comprises at least one column of first active regions 1 arranged in a first direction Y, the first active regions 1 extending in a second direction X, the ends of the first active regions 11 having first programming regions 18; at least one column of second active regions 2 arranged along a first direction Y, the second active regions 2 extending along a second direction X, the first active regions 2 having second programming regions 28 at the ends thereof; wherein the first direction Y is perpendicular to the second direction X; in the first direction Y, the width of the first programming regions 18 is smaller than the width of the first active regions 1, the width of the recesses 17 between adjacent first programming regions 18 is larger than the width of the recesses 17 between adjacent first active regions 1, and when the recesses 17 and the first active regions 1 arranged at intervals are formed by etching the original substrate, there is an etching load effect on the formed antifuse array due to the difference in width, that is, at the portion G of the antifuse array shown in fig. 2, exposure distortion (profile reduction, rounding) occurs to the profile of the first programming regions 18, reducing the area of the first active regions 1. Similarly, the second programming region 28 of the second active region 2 also has exposure distortion due to loading effects, reducing the area of the second active region 2. In addition, the current antifuse array has the problem of poor integration and programming success rate.

The embodiment of the disclosure provides an anti-fuse array and a storage structure, wherein the anti-fuse array is provided with a first active region with a first recess, a second active region with a second recess, a second programming region at one side of the first recess is at least partially positioned in the second recess, and a third programming region at one side of the second recess is at least partially positioned in the second recess, so that the clamping of the first active region and the second active region is realized, the space utilization rate can be improved, the number of anti-fuses in a unit area device can be increased, and the programming success rate is improved; the first active region and the second active region are clamped through the first recess and the second recess, so that profile distortion of a programming region (shown in fig. 1-2) caused by etching load effect can be reduced or avoided, meanwhile, dense stacking can be realized, and miniaturization of devices is realized. In addition, the first active region includes a first programming region and a second programming region located at both sides of the first recess in the third direction, and the second active region includes a third programming region and a fourth programming region located at both sides of the second recess in the third direction, and a programming area of the programming regions can be increased as compared with one active region having only one programming region, thereby improving a programming success rate.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

FIG. 3 is a schematic diagram of an antifuse array according to an embodiment of the present disclosure; FIG. 4 is a schematic diagram of a partial structure of an antifuse array according to an embodiment of the present disclosure; FIG. 5 is a schematic cross-sectional view of an antifuse array according to an embodiment of the present disclosure; FIG. 6 is a schematic structural diagram of a first active region according to an embodiment of the present disclosure; fig. 7 is a schematic cross-sectional structure of a first active region according to an embodiment of the disclosure; FIG. 8 is a schematic diagram of a structure of a second active region according to an embodiment of the present disclosure; fig. 9 is an antifuse circuit diagram of an antifuse array according to an embodiment of the present disclosure.

According to some embodiments of the present disclosure, referring to fig. 3-8, an aspect of embodiments of the present disclosure provides an antifuse array comprising: at least one column of first active regions 11 arranged along a first direction M, the first active regions 11 extending along a second direction X, ends of the first active regions 11 having first recesses 101, the first active regions 11 including first program regions 161 and second program regions 162 located at both sides of the first recesses 101 in a third direction Y; at least one column of second active regions 12 arranged along the first direction M, the second active regions 12 extending along the second direction X, the second active regions 12 having second recesses 102 at ends thereof, the second active regions 12 including third and fourth programming regions 163 and 164 located at both sides of the second recesses 102 in the third direction Y; the second programming region 162 is at least partially within the second recess 102 and the third programming region 163 is at least partially within the first recess 101; a program gate line 13, the program gate line 13 extending along the first direction M, the program gate line 13 covering each of the first programming region 161 and the second programming region 162 in a column of the first active regions 11, and the program gate line 13 also covering each of the third programming region 163 and the fourth programming region 164 in a column of the second active regions 12; the first direction M intersects with the second direction X and the third direction Y, and the second direction X is perpendicular to the third direction Y.

In some embodiments, the angle α between the first direction M and the third direction Y is in the range of [20 °,70 ° ], and optionally, the angle α between the first direction M and the third direction Y is in the range of [30 °,60 ° ]. The included angle α may be specifically 30 °, 42 °, 45 °, 51 °, 58 °, or the like. Since the first recess 101 of the first active region 11 and the second recess 102 of the second active region 12 are engaged with each other, and the second programming region 162 of the first active region 11 is at least partially located in the second recess 102, the third programming region 163 of the second active region 12 is located in the first recess 101, and the first programming region 161 is flush with a side surface of the second programming region 162, in order to achieve the maximum area of the first active region 11 and the second active region 12, a row of the first active regions 11 is arranged at intervals along the first direction M, i.e. two first active regions 11 are opposite to the same second active region 12, and in the second direction X, the offset spacing between adjacent first active regions 11 is equal to the width of the third programming region 163 located in the first recess 101. Similarly, the two second active regions 12 are opposite to each other with respect to the same first active region 11, and the offset pitch between the adjacent second active regions 12 is equal to the width of the second programming region 162 located in the second recess 102 along the second direction X. Thus, each first active region 11 can be mutually clamped with one second active region 12 along the first direction M, the proportion of shallow trench isolation structures for isolation is reduced, the number of the first active regions 11 and the second active regions 12 can be increased on a substrate with unit area, the number of antifuse units is increased, the antifuse structures in an antifuse array can be changed from 8F stacking to 6F stacking, the space utilization rate caused by dense stacking is greatly improved, more antifuse units can be placed under the same area, and the improvement of the integration degree of the memory and the miniaturization of the memory are realized. Where F refers to the minimum pattern size that can be obtained under a given process condition.

In some embodiments, the first active region 11 and the second active region 12 have the same shape and size. Thus, the processes for forming the first active region 11 and the second active region 12 can be prepared in the same process, the step difficulty of the whole production and preparation process is simplified, and the number of masks and devices for forming the first active region 11 and the second active region 12 can be reduced, so that the production cost is reduced. The first active region 11 and the second active region 12 have the same shape and size, i.e., the first active region 11 and the second active region 12 can be regarded as the same active region structure, and when the active regions are arranged, the reduction of space utilization rate caused by different shapes or sizes can be avoided, so that the number of antifuse units is increased, the integration level of the memory is further improved, and the miniaturization of the memory is realized. Having the same dimensions of the first active region 11 and the second active region 12 may include at least: along the third direction Y, the width of the first active region 11 is equal to the width of the second active region 12; along the second direction X, the length of the first active region 11 is equal to the length of the second active region 12; in the third direction Y, the width of the second programming region 162 is equal to the width of the third programming region 163; the width of the first program region 161 is equal to the width of the fourth program region 164. The first active region 11 and the second active region 12 having the same shape may include at least: the first active region 11 may overlap the second active region 12 after any rotation, or the front projection of the first active region 11 on the substrate 100 overlaps the front projection of the second active region 12 on the substrate 100.

In some embodiments, the first programming region 161 and the second programming region 162 of the first active region 11 are all programmed regions, and the programming gate line 13 is electrically connected to the first programming region 161 and the second programming region 162, and the gate dielectric layers on the first programming region 161 and the second programming region 162 can be formed as a gate oxide breakdown layer, so as to form a resistive connection, and form an on-resistance, i.e. data can be written through the first programming region 161 or the second programming region 162. The two programming regions (the first programming region 161 and the second programming region 162) may increase the programming success rate compared to only one programming region. When one programming area has a problem, the other programming area can play a role and continue to serve as the programming area, so that the writing and reading of data are ensured. The functions of the third programming region 163 and the fourth programming region 164 of the second active region 12 are the same as those of the first programming region 161 and the second programming region 162, and are not repeated here.

In some embodiments, the width of the first programming region 161 is greater than the width of the second programming region 162 along the third direction Y; in the third direction Y, the width of the fourth programming region 164 is greater than the width of the third programming region 163. Thus, the second programming region 162 and the third programming region 163 with smaller widths have smaller programming areas, and the areas of the gate dielectric layers on the second programming region 162 and the third programming region 163 are smaller, so that the gate dielectric layers can have smaller programming voltages, and the breakdown probability of the gate oxide layer is increased, so that the programming success rate is improved, and the larger first programming region 161 and the fourth programming region 164 and the smaller first programming region 161 and the smaller third programming region 163 can be used as programming regions, so that the programming area of the antifuse structure is increased, and the programming success rate is improved. In addition, the second programming region 162 with smaller width is located in the second recess 102, the third programming region 163 with smaller width is located in the first recess 101, and the areas or widths of the first recess 101 and the second recess 102 formed by etching are also smaller, so that the area of the remaining programming region is ensured to be larger, and the programming success rate is ensured. The area of the first active region 11 or the second active region 12 removed by etching is smaller, the time and cost required for etching are also reduced, and the purpose of reducing the cost of the memory is achieved. In other embodiments, the width of the first programming region 161 is greater than the width of the second programming region 162 along the third direction Y; in the third direction Y, the width of the fourth program is smaller than the width of the third program region 163. In still other embodiments, the width of the first programming region 161 is less than the width of the second programming region 162 along the third direction Y; in the third direction Y, the width of the fourth program is greater than the width of the third program region 163. In still other embodiments, the width of the first programming region 161 is less than the width of the second programming region 162 along the third direction Y; in the third direction Y, the width of the fourth programming region 164 is smaller than the width of the third programming region 163.

In some embodiments, the ratio of the width of the second programming region 162 to the width of the first active region 11 along the third direction Y ranges from 1/15 to 1/5. When the width of the first programming region 161 is set smaller, the programmable area of the second programming region 162 is smaller, and the area of the gate dielectric layer located on the second programming region 162 is smaller, so that smaller programming voltage can be obtained, the breakdown probability of the gate oxide layer is increased, and the programming success rate is improved, but when the width of the second programming region 162 is set smaller than 1/15 of the width of the first active region 11, on one hand, the process difficulty for preparing the second programming region 162 is higher; on the other hand, the second programming region 162 is too thin to collapse during use, thereby affecting the stability of the memory. When the width of the second programming region 162 is set to be larger, the area of the second recess 102 formed by etching is larger, which reduces the programming area, reduces the programming success rate, and further reduces the programming success rate due to the larger programming voltage.

In some embodiments, the first active region 11 further comprises: a first channel region 112, and a first source drain region 111 and a second source drain region located at both sides of the first channel region 112; the second active region 12 further includes: a second channel region 122, and third and fourth source-drain regions 121 and 121 located at both sides of the second channel region 122; the antifuse array further comprises: a first gate line 141, the first gate line 141 extending along the first direction M, the first gate line 141 covering each first channel region 112 in a column of the first active regions 11; the second gate line 142, the second gate line 142 extends along the first direction M, and the second gate line 142 covers each second channel region 122 in a column of the second active regions 12. The material of the first gate line 141 is a semiconductor material or a metal. The material of the second gate line 142 is a semiconductor material or a metal. The semiconductor material can be doped polysilicon, and the doping element is the same as that of the adjacent channel region; the metal material may be any of tungsten, titanium nitride, and the like.

In the first active region 11, the first channel region 112 and the first source drain region 111 and the second source drain region located at both sides of the first channel region 112 form a first selection transistor, and the first programming region 161 and the second programming region 162 are electrically connected to the first source drain region 111 and form a first antifuse memory cell together with the programming gate line 13. Specifically, in some embodiments, the first source drain region 111 may serve as a source region of the first selection transistor, and the second source drain region may serve as a drain region of the first selection transistor. The first select transistor and the first antifuse memory cell constitute a first antifuse cell.

In some embodiments, the dopant ion type in the first channel region 112 may be the same as the dopant ion type in the first source drain region 111 and the second source drain region, thereby constituting a junction-free transistor, and the dopant ion type in the first programming region 161 and the second programming region 162 may be the same as the dopant ion type in the first source drain region, thereby allowing carriers in the first channel region 112 to be transferred into the first programming region 161 when the first channel region 112 is turned on. In other embodiments, the doping ion type in the first channel region 112 may also be different from the doping ion type in the first source drain region 111 and the second source drain region, constituting a junction transistor.

Similarly, the second channel region 122 of the second active region 12 and the third source drain region 121 and the fourth source drain region located at two sides of the second channel region 122 form a second selection transistor, and the third programming region 163 and the fourth programming region 164 are electrically connected to the third source drain region 121 and form a second antifuse memory cell together with the programming gate line 13. The second select transistor and the second antifuse memory cell constitute a second antifuse cell.

In some embodiments, the antifuse array comprises a plurality of first and second antifuse cells, the antifuse cells further comprising a substrate 100 and shallow trench isolation structures 105, the first and second active regions 11, 12 being located on a surface of the substrate; the shallow trench isolation structures 105 are located between the first active regions 11 and the second active regions 12, and between adjacent first active regions 11, between adjacent second active regions 12. The material of the substrate 100 may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compounds, silicon carbide, etc. The material of the shallow trench isolation structure 105 may include an insulating material such as silicon oxide, silicon nitride or silicon oxynitride, so as to ensure isolation between the first active region 11 and the second active region 12, and isolation between adjacent first active regions 11 and between adjacent second active regions 12.

In some embodiments, the first active region 11 further comprises: a third channel region 114, fifth and sixth source-drain regions 115 on either side of the third channel region 114, and a third recess 103, the third recess 103 being located at an end of the first active region 11 opposite the first recess 101. The first active region 11 includes fifth programming regions 165 and sixth programming regions 166 located at both sides of the third recess 103 in the third direction Y, the fifth programming regions 165 being opposite to the second programming regions 162. In the third direction Y, the width of the fifth programming region 165 is smaller than the width of the sixth programming region 166. The third channel region 114, the sixth source-drain region 115 and the fifth source-drain region are arranged identically to the first channel region 112, the first source-drain region 111 and the second source-drain region, and the third channel region 114 and the fifth source-drain region and the sixth source-drain region 115 located at both sides of the third channel region 114 constitute a third selection transistor, and the fifth programming region 165 and the sixth programming region 166 are electrically connected to the sixth source-drain region 115 and together constitute a third antifuse memory cell with another programming gate line 13. The third select transistor and the second antifuse memory cell constitute a third antifuse cell.

In some embodiments, the planar shape of the first active region 11 is a centrosymmetric pattern. I.e. the first active region 11 is rotated through a plane by a certain angle, which may overlap the pattern of the original first active region 11. In this way, the second direction X may be set, and two sides of the first active area 11 may be respectively engaged with one second active area 12, thereby improving space utilization and improving integration of the memory device.

Similarly, the second active region 12 further includes: a fourth channel region 124, seventh and eighth source-drain regions 125 located on both sides of the fourth channel region 124, and a fourth recess 104; the planar shape of the second active region 12 is a center symmetrical pattern, thereby improving the integration of the memory device.

In some embodiments, in the first active region 11, an electrical connection is made between a second source-drain region and a fifth source-drain region between the first channel region 112 and the third channel region 114, the second source-drain region and the fifth source-drain region together forming a first bit line connection region 113; similarly, in the second active region 12, the fourth source-drain region and the seventh source-drain region between the second channel region 122 and the fourth channel region 124 together constitute a second bit line connection region 123. The antifuse array further includes a plurality of bit lines, each bit line being electrically connected to a corresponding one of the first bit line connection region 113 and the second bit line connection region 123 located in the same column. In the present disclosure, the ith first active region 11 (or the first bit line connection region 113) in a column of first active regions and the ith second active region 12 (or the second bit line connection region 123) in a column of second active regions are located in the same row, where i is a positive integer. For example, the bit line is electrically connected to the first bit line connection region 113 through the first bit line contact plug 151, and is electrically connected to the second bit line connection region 123 through the second bit line contact plug 152. The first and second selection transistors of the first active region 11 share a bit line, and the third and fourth selection transistors of the second active region 12 share a bit line, so that the integration of the memory device can be improved by sharing the bit line.

In some embodiments, the antifuse array further comprises: a third gate line 143, the third gate line 143 extending along the first direction M, the third gate line 143 covering each third channel region 114 in a column of the first active regions 11; the fourth gate line 144, the fourth gate line 144 extends along the first direction M, and the fourth gate line 144 covers each fourth channel region 124 in a column of the second active regions 12.

In some embodiments, the first active region 11 includes a central region O and a peripheral region P along a fourth direction N, where the first programming region 161 is located at the peripheral region P, the fourth direction N being parallel to the surface of the first active region 11 and perpendicular to the first direction M; in the third direction Y, the pitch between adjacent peripheral regions P is the same as the pitch between adjacent central regions O. In this way, the etching load effect of the formed anti-fuse array caused by the difference between the width of the concave between the adjacent programming regions and the width of the concave between the adjacent first active regions can be avoided, and the area of the first active regions is maximized.

The antifuse cell may be a diffusion/poly antifuse, poly/poly antifuse, metal/silicide antifuse, and metal/metal antifuse, depending on the electrode material of the gate line structure; the material of the gate dielectric layer may be a polysilicon antifuse, an ONO antifuse, an NO antifuse, an O antifuse, an amorphous silicon (a-Si) antifuse, or a gate oxide antifuse. Wherein O represents an oxide and N represents a nitride. In some embodiments, the antifuse cell is a gate oxide antifuse, working to store data "1" or "0" depending on whether the gate oxide dielectric layer is programmed (broken down).

In some embodiments, the first active region 11 further comprises: the first gate dielectric layer 106 and the second gate dielectric layer 107, the first gate dielectric layer 11 is located in the peripheral region P, the second gate dielectric layer 107 is located in the central region O, and the thickness of the first gate dielectric layer 106 is smaller than the thickness of the second gate dielectric layer 107 along the direction Z perpendicular to the surface of the substrate 100. The first gate dielectric layer 106 has a smaller thickness, so that the gate dielectric layer serving as a programming area can be easily programmed or broken down, and the programming success rate is improved. And the second gate dielectric layer 107 is thicker and is used for containing a gate dielectric layer with enough thickness as an isolation structure of the gate and the channel region, thereby reducing hot carrier effect, reducing leakage current, improving on/off sensitivity of the channel region and ensuring stability of the transistor. The second active region 12 likewise comprises: the first gate dielectric layer 106 and the second gate dielectric layer 107, the first gate dielectric layer 106 is located in the first peripheral area U of the second active area 12, and the second gate dielectric layer 107 is located in the second central area W of the second active area 12. And the first gate dielectric layer 106 located in the first active region 11 and the first gate dielectric layer 106 located in the second active region 12 are continuous film layers. The material of the first gate dielectric layer 106 is silicon oxide; the material of the second gate dielectric layer 107 is silicon oxide.

In some embodiments, the first gate dielectric layer 106 located in the first active region 11 is used to form a first capacitor, and the first gate dielectric layer 106 located in the second active region 12 is used to form a second capacitor. In the unprogrammed state of the first antifuse memory cell and the second antifuse memory cell, the first capacitor in the first antifuse memory cell and the second capacitor in the second antifuse memory cell are in a high-resistance state due to the presence of the first gate dielectric layer 106, and after programming, the first gate dielectric layer 106 is broken down, that is, the first capacitor and the second capacitor are broken down, so that the first capacitor and the second capacitor are in a low-resistance state, and by reading the change of the resistance states of the first antifuse memory cell and the second antifuse memory cell, the first antifuse memory cell and the second antifuse memory cell are subjected to writing operation.

In the antifuse array provided by the embodiment of the present disclosure, the first active region 11 includes the first programming region 161 and the second programming region 162 located at both sides of the first recess 101 in the third direction Y, and the second active region 12 includes the third programming region 163 and the fourth programming region 164 located at both sides of the second recess 102 in the third direction Y, so that the programming area of the programming regions can be increased compared to only one programming region of one active region, thereby improving the programming success rate. The second programming region 162 is at least partially located in the second recess 102, and the third programming region 163 is at least partially located in the first recess 101, that is, in the same device area, the first active region 11 and the second active region 12 are clamped with each other through the first recess 101 and the second recess 102, so that dense stacking can be realized, space utilization can be improved, and further, the number of antifuses in a unit area device can be increased, thereby improving a programming success rate, reducing or avoiding profile distortion (as shown in fig. 1-2) caused by etching load effect due to large difference of trench widths forming a shallow trench isolation structure, enlarging the first active region 11 and the second active region 12 to reach a target value, enlarging space utilization, and realizing miniaturization of the device.

FIG. 9 is a diagram of an antifuse circuit corresponding to that of FIG. 3, the antifuse circuit comprising: a first antifuse unit 21 and a second antifuse unit 22, the first antifuse unit 21 including: the first select transistor, the third select transistor, the first antifuse memory cell, and the third antifuse memory cell, and the second antifuse cell 22 includes: a second select transistor, a fourth select transistor, a second antifuse memory cell, and a fourth memory antifuse cell. The structures and connection relations of the first selection transistor and the third selection transistor, the first antifuse memory cell and the third antifuse memory cell, the second selection transistor and the fourth selection transistor, and the second antifuse memory cell and the fourth antifuse memory cell are the same or corresponding, so the first selection transistor, the second selection transistor, the first antifuse memory cell and the second antifuse memory cell are exemplified. The first antifuse memory cell is electrically connected to a programming gate FH of the second antifuse memory cell, one of a source or a drain of the first select transistor is electrically connected to the bit line BL, the other of the source or the drain of the first select transistor is electrically connected to one end of the first antifuse memory cell, and the first gate line 141 (WL 1) is electrically connected to the gate of the first select transistor; one of a source or a drain of the second selection transistor is electrically connected to the bit line BL, the other of the source or the drain of the second selection transistor is electrically connected to one end of the second antifuse memory cell, and the second gate line 142 (WL 2) is electrically connected to the gate of the second selection transistor.

In some embodiments, the first antifuse memory cell may include: the upper electrode of the first capacitor is electrically connected with the programming grid FH, and the lower electrode of the first capacitor is electrically connected with one of the source electrode or the drain electrode of the first selection transistor. The second antifuse memory cell may include: and the upper electrode of the second capacitor is electrically connected with the programming grid FH, and the lower electrode of the second capacitor is electrically connected with one of the source electrode or the drain electrode of the second selection transistor. When the first antifuse memory cell or the second antifuse memory cell is programmed, a programming voltage is applied to the programming gate FH, that is, a programming voltage is applied to the upper electrode of the first capacitor or the second capacitor, and a data voltage, for example, a low voltage, is applied to the lower electrode of the first capacitor or the second capacitor through the first selection transistor or the second selection transistor, so as to form a voltage difference between the upper electrode and the lower electrode, thereby breaking down the first capacitor or the second capacitor, so that the first capacitor or the second capacitor is converted from a high-resistance state to a low-resistance state, and writing of data is completed.

Specifically, in some embodiments, the source of the first select transistor is electrically connected to the bit line BL, the drain of the first select transistor is electrically connected to the lower electrode of the capacitor of the first antifuse memory cell, the source of the second select transistor is electrically connected to the bit line BL, the drain of the second select transistor is electrically connected to the lower electrode of the second antifuse memory cell, and the circuit principle of the antifuse circuit performing a programming operation is:

The process of writing data into the first antifuse memory cell is as follows: the first select transistor is turned on by applying a select voltage to the first gate line 141 (WL 1) of the first select transistor. The programming voltage may be applied to the programming gate FH of the first antifuse memory cell, for example, at a high voltage, i.e., to the upper electrode of the first capacitor. The data voltage is applied to the bit line BL connected to the source of the first selection transistor, for example, the voltage may be low (for example, ground), the drain level of the first selection transistor is pulled down to be identical to the level of the source of the first selection transistor (for example, ground voltage), the voltage of the lower electrode of the first capacitor in the first antifuse memory cell is pulled to the ground voltage, and thus a high voltage difference is formed between the upper electrode of the first capacitor and the lower electrode of the first capacitor, and the high voltage difference breaks down the first capacitor, thereby forming a low resistance path in the first antifuse cell, and completing the writing of data.

It will be appreciated that, since the first antifuse memory cell and the second antifuse memory cell share the same programming gate FH, in order to implement writing of data to the first antifuse cell 21 and the second antifuse cell 22, respectively, a turn-off voltage may be applied to the second gate line 142 (WL 2) of the second select transistor when writing of data to the first antifuse cell 21 (for example, the turn-off voltage may be a low voltage when the second select transistor is an NMOS transistor, for example, a ground voltage, and a high voltage when the second select transistor is a PMOS transistor, for example, a power supply voltage) to turn off the second select transistor. Therefore, the voltage difference between the upper electrode and the lower electrode of the second capacitor in the second anti-fuse memory cell can be prevented from being generated so as to cause the breakdown of the second capacitor.

The process of writing data into the second antifuse unit 22 is the same as the process of writing data into the first antifuse unit 21, and the description of the process of writing data into the first antifuse capacitor 21 is referred to above, and will not be repeated.

Accordingly, in accordance with some embodiments of the present disclosure, another aspect of embodiments of the present disclosure also provides a memory comprising an antifuse array as described in any of the above embodiments.

In some embodiments, the Memory may include RAM and ROM, and the RAM may specifically further include SRAM (Static Random-Access Memory), SSRAM (synchronous Static Random Access Memory ), DRAM (dynamic Random Access Memory, dynamic Random Access Memory), SDRAM (synchronous dynamic Random Access Memory ); the ROM may include MASK ROM (MASK ROM Mask Read Only Memory), OTP ROM, PROM (Programmable read-only memory), EPOM (erasable programmable ROM Erasable Programmable Read Only Memory), EEPROM (charged erasable programmable ROM Electrically Erasable Programmable Read Only Memory), FLASH ROM (FLASH memory), in particular.

Accordingly, according to some embodiments of the present disclosure, a further aspect of embodiments of the present disclosure provides a method for preparing an antifuse array, which may be used to prepare the antifuse arrays in the above embodiments (shown in fig. 3 to 8). Fig. 10 to 13 are schematic structural diagrams corresponding to each step of a method for manufacturing an antifuse array according to an embodiment of the present disclosure. The same elements as those of the above embodiment are not repeated here.

Referring to fig. 10, an initial substrate 109 is provided, the initial substrate 109 being used to form a first active region 11 and a second active region 12.

Referring to fig. 5 to 8 and 11, the initial substrate 109 (refer to fig. 10) is patterned to form at least one column of first active regions 11 arranged in a first direction M, the first active regions 11 extending in a second direction X, ends of the first active regions having first recesses 101, the first active regions 11 including first program regions 161 and second program regions 162 located at both sides of the first recesses 101 in a third direction Y; at least one column of second active regions 12 arranged along the first direction M, the second active regions 12 extending along the second direction X, the second active regions 12 having second recesses 102 at ends thereof, the second active regions 12 including third and fourth programming regions 163 and 164 located at both sides of the second recesses 102 in the third direction Y; the second programming region 162 is at least partially within the second recess 102 and the third programming region 163 is at least partially within the first recess 101; the first direction M intersects with the second direction X and the third direction Y, and the second direction X is perpendicular to the third direction Y.

In some embodiments, the recesses between adjacent first active regions 11, between adjacent second active regions 12, the recesses between the first active regions 11 and the second active regions 12 are filled with an isolation material for forming shallow trench isolation structures 105, and the isolation material is also located within the first recesses 101 and the second recesses 102.

In some embodiments, the first active region 11 and the second active region 12 are subjected to a first ion implantation process to form a P-well of an NMOS device or an N-well of a PMOS device. The first ion implantation process is used for implanting a first doping element, wherein the first doping element is an N-type doping element or a P-type doping element, the N-type doping element can be a V group element such As a phosphorus (P) element, a bismuth (Bi) element, an antimony (Sb) element or an arsenic (As) element, and the P-type doping element can be a III group element such As a boron (B) element, an aluminum (Al) element, a gallium (Ga) element or an indium (In) element.

Referring to fig. 5 to 8 and 12, in the fourth direction N, the first active region 11 includes a central region O and a peripheral region P, the second active region 12 includes a first central region W and a first peripheral region U, and the peripheral region P of the first active region 11 is adjacent to the first peripheral region U of the second active region 12. The peripheral region P of the first active region 11 and the first peripheral region U of the second active region 12 are subjected to a second ion implantation process to form programming regions having a high concentration, including, but not limited to, a first programming region 161, a second programming region 162, a third programming region 163, a fourth programming region 164, a fifth programming region 165, a sixth programming region 166, a seventh programming region 167, and an eighth programming region 168. The second ion implantation process is used for implanting a second doping element into the programming region, wherein the doping concentration of the second doping element is larger than that of the first doping element, and the doping element type of the second doping element is different from that of the first doping element. For example, the first doping element is an N-type doping element, and the second doping element is a P-type doping element; or the first doping element is a P-type doping element, and the second doping element is an N-type doping element.

In some embodiments, the fabrication process of the antifuse array further comprises: forming a gate dielectric film on the surfaces of the first active region 11 and the second active region 12; forming a protective layer on the surface of the first central region O of the first active region 11 and the first central region W of the second active region 12; removing the gate dielectric film on the surfaces of the peripheral region P of the first active region 11 and the first peripheral region U of the second active region 12; a first gate dielectric layer 106 is formed on the surface of the peripheral region P of the first active region 11 and the surface of the first peripheral region U of the second active region 12, the protective layer is removed, and the remaining gate dielectric film is used as a second gate dielectric layer 107.

In some embodiments, the gate dielectric film and the first gate dielectric layer 106 may be formed using an ISSG (In-Situ Steam Generation, in-situ moisture generation) process or a thermal oxidation process; the gate dielectric film is removed by adopting a wet etching process or a dry etching process, and the protective layer can be a photoresist layer.

Referring to fig. 13, a program gate line 13 is formed, the program gate line 13 extends along a first direction M, the program gate line 13 covers each of the first program region 161 and the second program region 162 in a column of the first active region 11, and the program gate line 13 also covers each of the third program region 163 and the fourth program region 164 in a column of the second active region 12; forming a first gate line 141 and a second gate line 142, the first gate line 141 extending along a first direction M, the first gate line 141 covering each first channel region 112 in a column of first active regions 11; the second gate line 142, the second gate line 142 extends along the first direction M, and the second gate line 142 covers each second channel region 122 in a column of the second active regions 12.

In some embodiments, the program gate line 13, the first gate line 141, and the second gate line 142 are formed simultaneously in the same process and apparatus. In other embodiments, the program gate line 13, the first gate line 141, the second gate line 142, the third gate line 143, and the fourth gate line 143 are formed simultaneously, and the third gate line 143 covers each third channel region 114 in a column of the first active region 11; the second gate line 142 covers each fourth channel region 124 in a column of the second active region 12.

Referring to fig. 3, a first bit line contact plug 151 is formed, the first bit line contact plug 151 being electrically connected to the bit line connection region 113 of the first active region 11; a second bit line contact plug 152 is formed, which is electrically connected to the second bit line connection region 123 of the second active region 12. The first bit line contact plug 151 of each column of the first active region 11 and the first second bit line contact plug 152 of the second active region 12 located in the third direction Y are electrically connected by the same bit line BL, and then different bit lines are provided to sequentially connect the ith first bit line contact plug 151 of each column of the first active region 11 and the ith second bit line contact plug 152 of the second active region 12 arranged in sequence (for example, i=2, 3, …).

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the disclosure, and the scope of the disclosure should be assessed accordingly to that of the appended claims.

Claims (17)

1. An antifuse array, comprising:

at least one column of first active regions arranged along a first direction, wherein the first active regions extend along a second direction, the end parts of the first active regions are provided with first pits, and the first active regions comprise first programming regions and second programming regions which are positioned at two sides of the first pits in a third direction;

at least one column of second active regions arranged along the first direction, the second active regions extending along the second direction, the ends of the second active regions having second recesses, the second active regions including third and fourth programming regions located on both sides of the second recesses in the third direction;

the second programming region is at least partially within the second recess, and the third programming region is at least partially within the first recess;

A program gate line extending along the first direction, the program gate line covering a column of each of the first and second programming regions in the first active region, and the program gate line also covering a column of each of the third and fourth programming regions in the second active region;

the first direction is intersected with the second direction and the third direction, and the second direction is perpendicular to the third direction.

2. The antifuse array of claim 1, wherein the angle between the first direction and the third direction is in the range of [20 °,70 ° ].

3. The antifuse array of claim 1, wherein a width of the first active region is equal to a width of the second active region along the third direction.

4. The antifuse array of claim 1, wherein, in the third direction, a width of the first programming region is greater than a width of the second programming region; the width of the fourth programming region is greater than the width of the third programming region along the third direction.

5. The antifuse array of claim 4, wherein the width of the second programming region is equal to the width of the third programming region; the width of the first programming region is equal to the width of the fourth programming region.

6. The antifuse array of claim 4, wherein a ratio of a width of the second programming region to a width of the first active region along the third direction ranges from 1/15 to 1/5.

7. The antifuse array of claim 1, wherein the first active region further comprises: the first channel region, and the first source drain region and the second source drain region which are positioned at two sides of the first channel region; the second active region further includes: the second channel region, the third source drain region and the fourth source drain region are positioned on two sides of the second channel region;

the antifuse array further comprises:

a first gate line extending along the first direction, the first gate line covering each of the first channel regions in a column of the first active regions;

and a second gate line extending along the first direction, the second gate line covering each of the second channel regions in a column of the second active regions.

8. The antifuse array of claim 7, wherein the first active region further comprises: the semiconductor device comprises a third channel region, a fifth source drain region, a sixth source drain region and a third recess, wherein the fifth source drain region and the sixth source drain region are positioned on two sides of the third channel region, and the third recess is positioned at the end part of the first active region opposite to the first recess.

9. The antifuse array of claim 8, wherein the first active region comprises a fifth programming region and a sixth programming region on opposite sides of the third recess in the third direction, the fifth programming region being opposite the second programming region.

10. The antifuse array of claim 9, wherein, in the third direction, the width of the fifth programming region is less than the width of the sixth programming region.

11. The antifuse array of claim 10, wherein the planar shape of the first active region is a centrally symmetric pattern.

12. The antifuse array of claim 7 or 11, wherein the second active region further comprises: the device comprises a fourth channel region, a seventh source drain region, an eighth source drain region and a fourth recess, wherein the seventh source drain region and the eighth source drain region are positioned at two sides of the fourth channel region; the plane shape of the second active area is a central symmetrical pattern.

13. The antifuse array of claim 12, wherein the first active region and the second active region have the same shape and size.

14. The antifuse array of claim 8, wherein a second source-drain region between the first channel region and the third channel region and the fifth source-drain region are electrically connected, the second source-drain region and the fifth source-drain region together forming a bit-line connection region.

15. The antifuse array of claim 1, wherein the first active region comprises a central region and a peripheral region in a fourth direction, the first programming region being located in the peripheral region, the fourth direction being parallel to the first active region surface and mutually perpendicular to the first direction; in the third direction, the spacing between adjacent peripheral regions is the same as the spacing between adjacent central regions.

16. The antifuse array of claim 15, wherein the first active region further comprises: the first gate dielectric layer is positioned in the peripheral area, the second gate dielectric layer is positioned in the central area, and the thickness of the first gate dielectric layer is smaller than that of the second gate dielectric layer.

17. A memory, comprising: an antifuse array according to any of claims 1 to 16.