CN117688878B

CN117688878B - Chip testing method and device, electronic equipment and readable storage medium

Info

Publication number: CN117688878B
Application number: CN202410145294.0A
Authority: CN
Inventors: 闫世显; 陈明宇; 李作骏; 唐丹; 包云岗
Original assignee: Beijing Open Source Chip Research Institute
Current assignee: Beijing Open Source Chip Research Institute
Priority date: 2024-02-01
Filing date: 2024-02-01
Publication date: 2024-04-26
Anticipated expiration: 2044-02-01
Also published as: CN117688878A

Abstract

The application provides a chip testing method, a device, electronic equipment and a readable storage medium, and relates to the technical field of chip development, wherein the method comprises the following steps: setting up a chip test system in the simulator, responding to a read operation instruction sent by the virtual processor to the virtual memory controller, carrying out protocol conversion on the read operation instruction through the virtual protocol converter according to a communication protocol of the virtual port physical layer, and sending the read operation instruction after the protocol conversion to the virtual port physical layer; reading data from the second virtual memory through the virtual port physical layer, performing signal conversion processing to obtain a read value of the signal conversion processing, and storing the read value into the first virtual memory; and extracting a read value from the first virtual memory through the virtual memory controller so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value. The method of the application can test the processor and the memory controller of the chip at the same time.

Description

Chip testing method and device, electronic equipment and readable storage medium

Technical Field

The present application relates to the field of chip testing technologies, and in particular, to a chip testing method, a device, an electronic apparatus, and a storage medium.

Background

The read operation function is an important function in the chip computing system, and when the chip computing system is designed, the read operation function of the chip computing system needs to be tested.

In the related art, the computing system of the chip can be tested through the field programmable gate array (Field Programmable GATE ARRAY, FPGA), and compared with a method using software simulation, the method using the FPGA to test the chip can shorten the iteration period. The chip computing system at least comprises a processor, a memory controller and a port physical layer, but because the FPGA lacks a virtual port physical layer with the same interface as the chip memory controller, the function test of the virtual memory controller and the function test of the memory processor can not be performed when the chip computing system is tested in the related technology.

That is, the related art method cannot perform a functional test on a memory controller in a chip computing system.

Disclosure of Invention

The embodiment of the application provides a chip testing method, a device, electronic equipment and a storage medium, which are used for solving the problem that a memory controller in a chip computing system cannot be tested in the prior art.

In a first aspect, an embodiment of the present application provides a method for testing a chip, including:

A chip test system is built in a simulator, wherein the chip test system comprises a virtual chip, a virtual protocol converter, a virtual port physical layer and a first virtual memory, and the virtual chip comprises a virtual processor, a virtual memory controller and a second virtual memory; the communication protocols of the virtual port physical layer and the virtual memory controller are different;

Responding to a read operation instruction sent by the virtual processor to the virtual memory controller, performing protocol conversion on the read operation instruction through the virtual protocol converter according to a communication protocol of the virtual port physical layer, and sending the read operation instruction after the protocol conversion to the virtual port physical layer;

reading data from the second virtual memory through the virtual port physical layer, performing signal conversion processing to obtain a reading value of the signal conversion processing, and storing the reading value into the first virtual memory;

And extracting the read value from the first virtual memory by the virtual memory controller so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value.

In a second aspect, an embodiment of the present application provides a chip test system, including a virtual chip, a virtual protocol converter, a virtual port physical layer, and a first virtual memory, where the virtual chip includes a virtual processor, a virtual memory controller, and a second virtual memory; the communication protocols of the virtual port physical layer and the virtual memory controller are different;

The virtual processor is configured to perform protocol conversion on a read operation instruction sent to the virtual memory controller through the virtual protocol converter by using a communication protocol of the virtual port physical layer, and send the read operation instruction after the protocol conversion to the virtual port physical layer;

The virtual port physical layer is used for reading data from the second virtual memory and performing signal conversion processing to obtain a reading value of the signal conversion processing and storing the reading value into the first virtual memory;

The virtual memory controller is configured to extract the read value from the first virtual memory, so as to determine whether the function of the virtual chip meets a preset chip function design requirement according to the read value.

In a third aspect, an embodiment of the present application further provides a chip testing apparatus, including:

The system comprises a construction module, a first virtual memory, a second virtual memory, a first virtual port physical layer and a second virtual port physical layer, wherein the construction module is used for constructing a chip test system in the simulator, the chip test system comprises a virtual chip, a virtual protocol converter, a virtual port physical layer and the first virtual memory, and the virtual chip comprises a virtual processor, a virtual memory controller and the second virtual memory; the communication protocols of the virtual port physical layer and the virtual memory controller are different;

The first sending module is used for responding to a read operation instruction sent by the virtual processor to the virtual memory controller, carrying out protocol conversion on the read operation instruction through the virtual protocol converter according to a communication protocol of the virtual port physical layer, and sending the read operation instruction after the protocol conversion to the virtual port physical layer;

the first acquisition module is used for reading data from the second virtual memory through the virtual port physical layer and performing signal conversion processing to obtain a reading value of the signal conversion processing and storing the reading value into the first virtual memory;

The first determining module is configured to extract, by using the virtual memory controller, the read value from the first virtual memory, so as to determine, according to the read value, whether a function of the virtual chip meets a preset chip function design requirement.

In a fourth aspect, an embodiment of the present application further provides an electronic device, including a processor;

a memory for storing the processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the method of the first aspect.

In a fifth aspect, embodiments of the present application also provide a computer-readable storage medium, which when executed by a processor of an electronic device, causes the electronic device to perform the method of the first aspect.

In the embodiment of the application, the virtual processor sends the read operation instruction to the virtual memory controller, and the virtual protocol converter converts the read operation instruction according to the communication protocol of the virtual port physical layer instead of directly sending the read operation instruction to the virtual port physical layer, and sends the read operation instruction after the protocol conversion to the virtual port physical layer. After the read value is obtained from the second virtual memory through the virtual port physical layer, the read value is not directly returned to the virtual memory controller, but is stored into the first virtual memory, and the virtual memory controller obtains the read value from the first virtual memory so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value. The test process is completed through the virtual processor and the virtual memory controller, and the obtained test result of the read operation can reflect whether the virtual processor and the virtual memory controller meet the chip design requirement, so that the problem that in the related technology, the virtual memory controller cannot be tested due to the fact that a virtual port physical layer with the same interface as the chip memory controller is lacking in the simulator, and the communication protocol between the virtual port physical layer and the virtual memory controller in the virtual chip is different is solved.

The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 is a schematic diagram of an application scenario of a chip testing method according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a chip computing system according to an embodiment of the present application;

FIG. 3 is a flowchart illustrating steps of a method for testing a chip according to an embodiment of the present application;

FIG. 4 is a flowchart illustrating steps of another method for testing a chip according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a chip test system according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another chip test system according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a chip test system according to another embodiment of the present application;

FIG. 8 is a flowchart illustrating steps of another method for testing a chip according to an embodiment of the present application;

FIG. 9 is a flowchart illustrating steps of another method for testing a chip according to an embodiment of the present application;

FIG. 10 is a block diagram of a chip test apparatus according to an embodiment of the present invention;

FIG. 11 is a block diagram of an electronic device provided by an embodiment of the present invention;

fig. 12 is a block diagram of another electronic device in accordance with another embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type, and are not limited to the number of objects, such as the first object may be one or more. Furthermore, the term "and/or" as used in the specification and claims to describe an association of associated objects means that there may be three relationships, e.g., a and/or B, may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The term "plurality" in embodiments of the present application means two or more, and other adjectives are similar.

Fig. 1 is a schematic view of an application scenario of a chip testing method according to an embodiment of the present application, and referring to fig. 1, the application scenario includes at least an emulator, in which a chip testing system is built, the chip testing system includes a virtual chip, and the virtual chip includes a virtual processor, a virtual memory controller, and a second virtual memory. The chip test system also comprises a virtual port physical layer and a time sequence control module, wherein the time sequence control module at least comprises a first virtual memory and a virtual protocol converter.

In the development process of the chip, the virtual chip needs to be tested, and after the chip development is completed, the physical chip can be obtained through streaming processing according to the virtual chip. Further, in the chip development process, it is necessary to design a computing system of the chip and test the computing system of the chip. Wherein the testing includes at least a read operation test of the chip. Specifically, the portion to be tested is a System on Chip (SoC) of a Chip, wherein, referring to fig. 2, the minimum SoC System includes at least: processor, memory controller, port physical layer and storage medium.

In the related art, when a chip test can be performed using an emulator (e.g., FPGA), but the kind of the emulator with its own virtual module is limited, it is difficult to deploy a processor, a memory controller, a port physical layer, and a storage medium for designing the chip in the emulator. For example, the emulator interfaces from the ported physical layer (PHYSICAL LAYER, PHY) differently than the memory controller that was designed when the chip was designed. Illustratively, when designing a chip, the downward interfaces of the memory controller are Double Data Rate (DDR) and PHY interfaces (DDR PHY INTERFACE, DFI), while the virtual port physical layer of the emulator itself does not have a DFI interface. This may result in the emulator having a virtual memory controller corresponding to the designed memory controller that differs from the communication protocol between the virtual port physical layer. Because the communication protocols between the virtual memory controller and the virtual port physical layer are different, the related art only can test the processor in the chip, but cannot test the memory control.

In order to solve the problems in the related art, the application provides a chip method, which comprises the steps that a virtual processor sends a read operation instruction to a virtual memory controller (Memory Controller, MC), a virtual protocol converter carries out protocol conversion on the read operation instruction according to a communication protocol of a virtual port physical layer, and the read operation instruction after the protocol conversion is sent to the virtual port physical layer; reading data from the second virtual memory through the virtual port physical layer, performing signal conversion processing to obtain a read value of the signal conversion processing, and storing the read value into the first virtual memory; and extracting a read value from the first virtual memory through the virtual memory controller so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value.

The chip testing method provided by the embodiment of the application is described in detail below by means of a specific embodiment with reference to fig. 3.

Step 101, a chip test system is built in a simulator.

Specifically, the chip test system comprises a virtual chip, a virtual protocol converter, a virtual port physical layer and a first virtual memory, wherein the virtual chip comprises a virtual processor, a virtual memory controller and a second virtual memory.

Wherein the communication protocols of the virtual port physical layer and the virtual memory controller are different. The communication protocol between the virtual port physical layer and the virtual memory controller is different. Further, the downward interfaces of the virtual port physical layer and the virtual memory controller are different, resulting in different communication protocols between the virtual port physical layer and the virtual memory controller. For example, the interface of the virtual port physical layer is an advanced extensible interface (Advanced eXtensible Interface, AXI 4), and the downward interface of the virtual memory controller is DFI.

The communication protocols between the virtual port physical layer and the virtual memory controller are different, so that the virtual port physical layer and the virtual memory controller cannot directly perform data interaction and cannot directly perform instruction transmission.

The virtual memory controller, the virtual port physical layer, the first virtual memory, the second virtual memory, and the virtual processor are all virtual modules in the emulator. For example, the simulator may be a simulator provided for an FPGA.

By way of example, a virtual chip is a chip designed by a virtual module in an emulator in the process of developing the chip. The chip development process comprises a test process of the chip, and after the chip development is completed, the physical chip can be obtained through streaming processing according to the virtual chip. For example, after the chip development is completed, the physical chip is obtained by stream processing according to the designed virtual chip, and the virtual processor in the virtual chip corresponds to the physical processor in the physical chip, and the processing logic of the virtual processor is the same as that of the physical processor. The virtual memory controller in the virtual chip corresponds to the memory controller in the physical chip, and the processing logic between the virtual memory controller and the memory controller is the same.

Further, the virtual memory corresponds to the designed memory. The memory may be of various types, for example, a double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR4 SDRAM) chip, a DDR3 chip, or other types of memory.

In particular, the DDR memory is a common memory, and is suitable for various computing systems and electronic devices, and DDR can be used as a memory to improve the data storage performance and the data access performance of the computing system. For example, DDR may be applied to personal computers, servers, embedded systems, graphics processing systems, multimedia processing systems, network devices, large-scale data centers, scientific computing systems, artificial intelligence devices, internet of things devices, and various high-performance computing systems. DDR has high speed performance, high bandwidth and low power consumption characteristics, making it an integral part of modern computing systems.

Step 102, responding to a read operation instruction sent by the virtual processor to the virtual memory controller, performing protocol conversion on the read operation instruction through the virtual protocol converter according to a communication protocol of the virtual port physical layer, and sending the read operation instruction after the protocol conversion to the virtual port physical layer.

For example, the virtual memory controller schedules the read operation instruction sent by the virtual processor with the maximum bandwidth and/or the minimum latency as a scheduling policy. And then, carrying out protocol conversion on the scheduled read operation instruction through a command virtual protocol converter in the chip test system, and converting the scheduled read operation instruction into a read operation instruction which accords with the communication protocol requirement of the virtual port physical layer. And then sending the read operation instruction after protocol conversion to the virtual port physical layer.

The virtual protocol converter is a self-contained virtual module in the simulator, and the virtual protocol converter is a read data protocol converter for carrying out protocol conversion on read data.

And 103, reading data from the second virtual memory through the virtual port physical layer, performing signal conversion processing, obtaining a reading value of the signal conversion processing, and storing the reading value into the first virtual memory.

For example, the read operation instruction has a physical address, and after the virtual port physical layer receives the read operation instruction, the virtual port physical layer reads data from the physical address in the second virtual memory according to the physical address in the operation instruction. Wherein the physical address is an address where data to be read is loaded in the second virtual memory. After the virtual port physical layer reads data from the second virtual memory, the virtual port physical layer converts the data of the analog signal into the data of the digital signal, and stores the converted data into the first virtual memory as a read value.

For example, the data in the second virtual memory is a write operation instruction sent to the virtual memory controller by the virtual processor, and the data in the second virtual memory is written.

Step 104, extracting a read value from the first virtual memory by the virtual memory controller, so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value.

For example, the preset chip function design requirements include: the read value obtained from the read operation is correct. And under the condition that the read value is correct, determining that the function of the virtual chip meets the preset chip function design requirement.

In the related technology, the performance of the chip can be tested through a software simulation environment, but the common software simulation environment has the problem of low simulation speed, and the chip with a complex system and a large test load cannot be completely and accurately accessed and stored in a short time by using the software simulation environment.

In some applications, an emulator such as an FPGA is used to test a chip, but for an FPGA with a fast emulation speed, there is a virtual port physical layer in the emulator, which is different from an interface of a designed virtual memory controller of a designed chip, so that in a chip test system built in the emulator, the virtual memory controller of the virtual chip and the virtual port physical layer cannot directly perform data interaction, which results in that a method in related technologies can only test a virtual processor, but cannot test the virtual memory controller.

In the embodiment of the application, the read operation instruction is sent to the virtual memory controller through the virtual processor, and is not directly sent to the virtual port physical layer, but is subjected to protocol conversion according to the communication protocol of the virtual port physical layer through the virtual protocol converter, and the read operation instruction after the protocol conversion is sent to the virtual port physical layer. After the read value is obtained from the second virtual memory through the virtual port physical layer, the read value is not directly returned to the virtual memory controller, but is stored into the first virtual memory, and the virtual memory controller obtains the read value from the first virtual memory so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value. The testing process is completed through the virtual processor and the virtual memory controller, so that the finally obtained testing result of the read operation can reach the preset chip function design requirement only under the condition that the read operation functions of the virtual processor and the virtual memory controller reach the preset chip function design requirement. Therefore, based on the test result of the read operation obtained by the method of the embodiment, the read operation functions of the virtual processor and the virtual memory controller can be reflected at the same time, and the problem that in the related art, the virtual memory controller cannot be tested because the virtual port physical layer with the same interface as the chip memory controller is lacking in the simulator, so that the communication protocols between the virtual port physical layer and the virtual memory controller in the virtual chip are different is solved.

Fig. 4 is a flowchart illustrating steps of another method for testing a chip according to the present application, and referring to fig. 4, the method may include the following steps:

step 201, a chip test system is built in a simulator.

Specifically, the chip test system comprises a virtual chip, a virtual protocol converter, a virtual port physical layer and a first virtual memory, wherein the virtual chip comprises a virtual processor, a virtual memory controller and a second virtual memory; the virtual port physical layer and the virtual memory controller differ in communication protocol.

The method of this step is described in the foregoing step 101, and will not be described here again.

Step 202, responding to a read operation instruction sent by the virtual processor to the virtual memory controller, performing protocol conversion on the read operation instruction through the virtual protocol converter according to a communication protocol of the virtual port physical layer, and sending the read operation instruction after the protocol conversion to the virtual port physical layer.

In one embodiment, the chip test system further comprises a fourth virtual memory; step 202 may comprise the following sub-steps:

Sub-step 2021, in response to the read operation instruction sent by the virtual processor to the virtual memory controller, stores the read operation instruction in the fourth virtual memory.

The fourth virtual memory is a virtual memory set in the chip test system in the process of developing the chip. And after the chip development is completed, the entity memory corresponding to the fourth virtual memory is not included in the entity chip obtained through the streaming processing.

Sub-step 2022, after receiving, by the virtual port physical layer, an instruction for the second virtual memory to complete the function guarantee operation, performing protocol conversion on the read operation instruction stored in the fourth virtual memory according to the communication protocol of the virtual port physical layer, and sending the read operation instruction after the protocol conversion to the virtual port physical layer.

Specifically, the function guarantee operation is used for enabling the second virtual memory to perform correct read-write operation. The function assurance operations may include refresh operations, and/or calibration operations, among others.

Illustratively, the refresh complete instruction is configured to indicate that the refresh operation is complete for the second virtual memory, and the calibration complete instruction is configured to indicate that the calibration operation is complete for the second virtual memory. The calibration operation may include, among other things, region qualifier (Zone Qualifier, ZQ) resistance calibration.

For example, by the virtual processor, instructions to refresh, and/or calibrate the virtual memory controller are sent to the virtual memory controller, which, based on the instructions, controls the second virtual memory to refresh, and/or calibrate. After the refresh is complete, and/or the calibration is complete, an instruction is issued indicating that the corresponding operation is complete.

In this embodiment, after receiving the instruction of the function guarantee operation of the second virtual memory through the virtual port physical layer, according to the communication protocol of the virtual port physical layer, the read operation instruction stored in the fourth virtual memory is subjected to protocol conversion and then sent to the virtual port physical layer, instead of immediately carrying out protocol conversion on the read operation instruction in response to the read operation instruction sent by the virtual processor, and then sent to the virtual port physical layer, thereby avoiding the problem that the second virtual memory sends the read operation instruction in the process of executing the function guarantee operation, and the data transmission bus is blocked because the read operation cannot be executed.

sub-step 2023, in response to the read operation instruction sent by the virtual processor to the virtual memory controller, stores the read operation instruction in the fourth virtual memory.

The method of this step is described in the foregoing step 2021, and will not be described here again.

Sub-step 2024 obtains a second design timing parameter of the virtual memory controller when the virtual memory controller is designed.

The second design time sequence parameter is used for determining the instruction sending time matched with the second design time sequence parameter when the read-write operation instruction is sent subsequently.

The second design time sequence parameter refers to the time sequence parameter used by the designed chip when sending the read-write operation instruction in the process of developing the chip. According to the second design time sequence parameter, the time interval when the read-write operation instruction is sent again after the read-write operation instruction is sent can be determined, and therefore the instruction sending time of the next read-write operation instruction can be determined based on the second design time sequence parameter and the time of sending the last read-write operation instruction, and the read-write operation instruction can be sent at the instruction sending time.

Sub-step 2025, according to the second design timing parameter, performing protocol conversion on the read operation instruction stored in the fourth virtual memory according to the communication protocol of the virtual port physical layer, and sending the read operation instruction after the protocol conversion to the virtual port physical layer;

Determining an instruction sending time for sending the read-write operation instruction according to the second design time sequence parameter, and at the instruction sending time, performing protocol conversion on the read operation instruction stored in the fourth virtual memory according to a communication protocol of the virtual port physical layer through a virtual protocol converter (such as a command converter), and sending the read operation instruction after the protocol conversion to the virtual port physical layer.

In step 203, the data is read from the second virtual memory through the virtual port physical layer, and the signal conversion processing is performed, so as to obtain a read value of the signal conversion processing, and the read value is stored in the first virtual memory.

The method of this step is described in the foregoing step 103, and will not be described here again.

In one embodiment, the clock frequency at which the virtual processor is run in the emulator is less than the design frequency at which the virtual processor is designed.

Step 204, obtaining a first design timing parameter of the virtual memory controller when designing the virtual memory controller.

Specifically, the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and acquiring the read-write data at the read-write time.

Further, the first design timing parameter refers to a timing parameter used when the designed chip performs the read-write operation in the process of developing the chip. For example, the first design timing parameter is a memory timing used during a chip read and write operation, for example, the first design timing parameter may include a column address strobe delay (ColumnAddress Strobe Latency, CL), which is a column address strobe (ColumnAddress Strobe, CAS) delay time, representing the time required to issue a command to read data, which may be expressed in cycles.

In step 205, a read value is obtained from the first virtual memory according to the first design timing parameter by the virtual memory controller, so as to determine whether the performance of the virtual chip meets the preset chip performance design requirement according to the time of obtaining the read value.

Illustratively, the preset chip performance design requirements include: the response time of the virtual chip is smaller than or equal to a preset response time threshold. Further, according to the moment of acquiring the read value, the response time of acquiring the virtual chip is calculated.

And determining whether the performance of the virtual chip meets the preset chip performance design requirement or not under the condition that the calculated response time is smaller than or equal to the preset response time threshold value according to the moment of acquiring the read value.

For example, in the case that the virtual processor issues a plurality of read operation instructions, or a plurality of read and write operation instructions, the time when the first instruction is issued is acquired, and the time when the read value is read according to the last read operation instruction, the duration between the two times is determined as the response time of the virtual chip.

The virtual processor sends a read operation instruction to the virtual memory controller, the virtual memory controller sends the read operation instruction, the virtual memory controller determines that the read operation instruction is sent from the virtual memory controller according to the first design time sequence parameter, obtains the time delay of reading data, determines the time of extracting the read value from the first virtual memory according to the time and the time delay of the virtual memory controller sending the read operation instruction, and extracts the read value from the first virtual memory at the time.

Illustratively, step 205 may include the sub-steps of:

sub-step 2051, performing protocol conversion on the read value according to the communication protocol of the virtual memory controller, to obtain a read value after the protocol conversion.

And the communication protocols of the virtual memory controller and the virtual port physical layer are different, and the read value is subjected to protocol conversion according to the communication protocol of the virtual memory controller, so that the converted read value is obtained, and the communication protocol requirements of the virtual memory controller are met.

In step 2052, the converted read value is sent to the virtual processor by the virtual memory controller.

Illustratively, the virtual memory controller and the virtual processor have the same communication protocol, and the virtual memory controller sends the read value after the protocol conversion to the virtual processor through the same communication protocol as the virtual processor.

In step 2053, it is determined, by the virtual processor, whether the function of the virtual chip meets the preset chip function design requirement according to the read value after the protocol conversion.

For example, the chip function reaching the preset chip function design requirement means that the read value read from the second virtual memory is correct when the read operation is performed.

For example, the virtual processor stores an expected read value corresponding to the read value, compares the read value with the expected read value, and determines that the read operation meets the preset test requirement when the read value and the expected read value are the same. Further, the expected read value is data written into the second virtual memory for the virtual processor to read from the second virtual memory according to the first read operation instruction.

And carrying out protocol conversion on the read value according to the communication protocol of the virtual memory controller, so that the converted read value can be received and identified by the virtual memory controller, and the virtual memory controller can obtain the data in the second virtual memory, so that in the subsequent processing process, whether the read operation of the virtual chip reaches the preset test requirement is judged according to the received and identified read value.

In the chip development process, it is necessary to design a chip and test the performance of the designed chip. Specifically, virtual chips are built and run in an emulator (e.g., FPGA) to test chip performance. However, when designing a chip, the clock frequency of some design modules (such as a design processor) in the design chip is relatively high, and the clock frequency of the system operation of the simulator is generally limited, for example, the clock frequency of the design processor may be higher than 3GHz, and the clock frequency of the simulator system operation can only reach hundreds of MHz. Therefore, in order to run the design chip in the emulator, it is necessary to perform down-conversion processing on a module having a higher clock frequency in the design chip so that the emulator can successfully run the virtual chip constructed for the design chip. For example, it is desirable to reduce the clock frequency of the design processor to the range of clock frequencies in which the system operates in the emulator.

After the design processor in the design chip computing system is subjected to frequency reduction processing, the obtained virtual processor can normally operate according to the data processing logic of the design processor, but after some design modules (such as storage media) in the design chip are subjected to frequency reduction processing according to the frequency reduction proportion of the design processor, the modules may have abnormal operation, so that the chip test result is inaccurate. For example, for a storage medium in a design chip computing system, the storage medium needs to operate at a particular higher frequency because of its own performance. For example, the storage medium is an SDRAM chip, when the SDRAM is operated in Delay-Locked Loop (DLL off) mode, a PHY supporting the DLL off mode is required, and the SDRAM chip needs to be refreshed periodically to ensure the correctness of data. Because of the limitation of the SDRAM refresh interval, in the DLL mode, although the SDRAM and the processor (e.g., CPU) can perform equal-scale frequency down, the refresh frequency difference may cause inaccurate access test of the chip.

After the down conversion processing is performed on each module, the behavior of part of the modules changes, so that the performance (such as access capability) of the chip computing system is tested inaccurately. Therefore, when a virtual chip is built in the simulator, it is difficult to perform equal-scale down-conversion on each module in the virtual chip. However, if only some of the design modules in the design chip are down-converted, the test result will be inaccurate. For example, when only the design processor performs the down-conversion process, but not the design storage medium, the clock frequency of the virtual storage medium is equal to the clock frequency of the design virtual storage medium, and the clock frequency of the virtual processor is lower than the clock frequency of the design processor, which may result in higher test performance of the CPU.

In the related art, the access delay can be simulated by adding a simple fixed delay, but the fixed delay is not necessarily suitable for designing a chip, so that a method for adding the fixed delay cannot simulate the actual access behavior of the designed chip, and the test result of the chip is inaccurate. The clock gating can be utilized to decouple the timing dependency of the processor and the storage medium to test the chip performance at the emulator, but the timing model does not support the DFI protocol, the memory controller of the DFI interface cannot be verified, and the timing provided by the timing model can reduce the emulation speed of the entire computing system during read and write operations.

In this embodiment, the virtual processor and the virtual memory controller cooperatively process to obtain a read value, and determine whether the performance of the virtual chip meets the preset chip performance design requirement according to the read value. The test result obtained by the method can reflect the performances of the virtual processor and the virtual memory controller at the same time, and solves the problem that the performance of the virtual memory controller cannot be tested due to different communication protocols between the physical layer of the virtual port in the simulator and the virtual memory controller in the virtual chip in the related technology. The first design time sequence parameter according to which the read value is obtained from the virtual memory controller is that the read value can be obtained at the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, so that the time sequence of the read value is obtained and the time sequence of the read value obtained from the design chip is consistent. Therefore, under the condition that the clock frequency of the virtual processor running in the simulator is smaller than the design frequency when the virtual processor is designed, the virtual chip can acquire the read value at the read-write time matched with the first design time sequence parameter, and whether the performance of the virtual chip meets the preset chip performance design requirement can be accurately determined according to the time of acquiring the read value. Based on the method of the embodiment, the accuracy of the virtual chip test result is improved.

In one embodiment, the clock frequency of the second virtual memory is greater than the clock frequency of the virtual memory controller to store data in the first virtual memory prior to fetching the read value from the first virtual memory by the virtual memory controller. Therefore, the virtual memory controller can timely acquire the read value from the first virtual memory so as to ensure the accuracy of the obtained judgment result when judging the read operation performance of the virtual chip according to the read value.

In one embodiment, the chip test system further comprises a third virtual memory. Prior to step 202, further comprising:

And step 206, responding to the write operation instruction sent by the virtual processor to the virtual memory controller, storing write data in the write operation instruction into a third virtual memory, performing protocol conversion on the write operation instruction through the virtual protocol converter according to the communication protocol of the virtual port physical layer, and sending the write operation instruction after the protocol conversion to the virtual port physical layer.

The third virtual memory is, for example, a virtual module for testing chip performance during the chip development phase. And after the chip development is completed, the streaming processing is carried out to obtain the entity chip, wherein the entity chip does not comprise a memory entity corresponding to the third virtual memory.

Step 207, obtaining write data from the third virtual memory through the virtual port physical layer, and writing the write data into the second virtual memory for subsequent reading of the data from the second virtual memory through the virtual port physical layer.

Illustratively, the data read from the second virtual memory in steps 201 through 205 is the data written into the second virtual memory in this step.

Further, when the chip test is performed, a series of read-write operation instructions can be sent out through the virtual processor, data is written in the second virtual memory through the write operation instructions, the previously written data is read from the second virtual memory through the read operation instructions, and whether the functions of the virtual chip meet the preset chip function design requirements is determined according to the read data.

In this embodiment, after the virtual processor sends the write operation instruction to the virtual memory controller, the virtual memory controller does not directly send the write operation instruction to the virtual port physical layer, but sends the write operation instruction to the virtual port physical layer after performing protocol conversion according to the communication protocol of the virtual port physical layer. Therefore, under the condition that the communication protocols of the virtual port physical layer and the virtual memory controller are different, the virtual port physical layer can acquire data from the third virtual memory according to a write operation instruction sent by the virtual memory controller and write the data into the second virtual memory. The process of writing the data into the second virtual memory is completed by the virtual processor and the virtual memory controller together, and the writing operation performance of the virtual processor and the virtual memory controller can be reflected simultaneously, so that the problem that the virtual memory controller cannot be tested due to different communication protocols between a virtual port physical layer in the simulator and the virtual memory controller in the virtual chip in the related technology is solved.

Correspondingly, step 206 may comprise the following sub-steps:

Sub-step 2061, obtaining a first design timing parameter of the virtual memory controller when designing the virtual memory controller.

Specifically, the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and acquiring read-write data at the read-write time.

The first design timing parameter is described in the foregoing step 204, and is not described herein.

Sub-step 2062, storing the write data in the write operation instruction in the third virtual memory according to the first design timing parameter.

For example, the virtual memory controller issues a write operation instruction, determines a time delay for writing data according to the design timing parameter, and determines a time for writing data according to the time delay, so as to store the write data in the write operation instruction into the third virtual memory at the time.

According to the first design time sequence parameter, writing data in a writing operation instruction into a third virtual memory, therefore, under the condition that the clock frequency of a running virtual processor in an emulator is smaller than the first design frequency of the design virtual processor, the writing data can be obtained at the reading and writing time matched with the first design time sequence parameter according to the first design time sequence parameter, the writing data is written into the third virtual memory, the writing data in the third virtual memory is written into a second virtual memory, and then whether the performance of a virtual chip meets the preset chip performance design requirement is judged according to the time of reading the writing data from the second virtual memory.

In one embodiment, the clock frequency of the virtual memory is greater than a second design frequency at which the virtual memory controller is designed. Correspondingly, after step 201, the method further includes:

Step 208, obtaining a third design timing parameter of the virtual memory controller when designing the virtual memory controller.

Specifically, the third design timing parameter is used to determine a time when the function guarantee operation instruction is sent. Further, when the chip is designed, the third design timing parameter is a parameter designed to determine the function guarantee operation instruction sending timing.

The function guarantee operation instruction is used for indicating the second virtual memory to perform function guarantee operation, and the function guarantee operation is used for enabling the second virtual memory to acquire correct read-write data. For example, the function assurance operations may include refresh, and/or calibration operations.

Step 209, according to the third design timing parameter, sending a function guarantee operation instruction to the second virtual memory, so as to perform a function guarantee operation on the second virtual memory.

Under the condition that the clock frequency of the virtual memory is larger than the second design frequency when the virtual memory controller is designed, the frequency is equivalent to the frequency reduction of the designed virtual memory controller, which can lead to the time interval of the virtual memory controller for sending the function guarantee operation instruction to be larger than the design time interval of the virtual memory controller for sending the function guarantee operation instruction. In this embodiment, according to the third design timing parameter, the function guarantee operation instruction is sent to the second virtual memory to perform the function guarantee operation on the second virtual memory, so that the time of sending the function guarantee operation instruction can be ensured, the design requirement of the chip is met, and the problem that the second virtual memory cannot work normally due to the fact that the time interval for sending the function guarantee operation instruction is increased is avoided.

In one embodiment, referring to FIG. 5, a chip test system includes a virtual processor, a virtual memory controller, a timing control module, a memory interface generator, and a second virtual memory.

Wherein the memory interface generator is a memory interface generator (Memory Interface Generator, MIG) provided by Xilinx, the MIG includes a PHY, and in the embodiment shown in fig. 5, the MIG includes a PHY that corresponds to the virtual port physical layer in the previous embodiment. Wherein the second virtual memory is DDR4 SDRAM.

Further, in the embodiment shown in fig. 5, the up interface of the MC (virtual memory controller in the foregoing embodiment) in the central processing unit (Central Processing Unit, CPU) minimum computing system is an on-chip bus interface, for example, the on-chip bus interface may be AXI4, and the down interface of the MC is a DFI interface. Correspondingly, in the embodiment shown in fig. 5, the interface of the virtual memory controller to the virtual processor is a first interface, the first interface is an AXI4 interface, the interface of the virtual memory controller to the timing control module is a second interface, and the second interface is a DFI interface.

Further, the interface of the timing control module to the memory interface generator is the same interface as the PHY.

The downward interface of the virtual memory controller is a DFI interface, which is different from the interface of the memory interface generator, and the interface between the virtual memory controller and the memory interface generator is different, and correspondingly, the communication protocol between the two is also different. Specifically, the downward interface of the virtual memory controller is different from the interface of the virtual port physical layer in the memory interface generator, and the communication protocol between the downward interface and the interface is different. Therefore, the instruction cannot be directly sent to the memory interface generator through the virtual memory controller, and the data read from the second virtual memory through the memory interface generator cannot be directly returned to the virtual memory controller.

Specifically, referring to fig. 6, the chip test system includes a virtual processor, a timing control module, a virtual memory controller, a virtual port physical layer, and a second virtual memory.

Referring to fig. 6, the timing control module includes a timing parameter register, a read data controller, a read data protocol converter, a read data memory, a write data controller, a write data protocol converter, a write data memory, a command protocol converter, a command memory, a command controller, and a function guarantee module.

The read data memory corresponds to the first virtual memory in the foregoing embodiment, the write data memory corresponds to the third virtual memory in the foregoing embodiment, and the command memory corresponds to the fourth virtual memory in the foregoing embodiment.

The virtual processor may be a CPU, a graphics processor (graphics processing unit, GPU), a special purpose processor, or other processor, and is configured to issue memory test instructions.

Wherein the test system further comprises an on-chip bus (not shown in the figures). In transmitting data or commands over an on-chip bus, the communication protocols used include, but are not limited to: AXI3, AXI4, a coherence extension protocol (AMBA AXI Coherency Extension, ACE) based on advanced microcontroller bus architecture (Advanced Microcontroller Bus Architecture, AMBA), a coherence hub interface (CoherentHubInterface, CHI) communication protocol.

The virtual memory controller is a memory controller in a System on Chip (SoC) to be tested, and is mainly responsible for prefetching, scheduling and the like of access commands. In order to improve the access performance of the computing system, the Host MC generally reorders the access command sequence according to the media status, so as to achieve the purposes of high bandwidth and low latency. In addition, the virtual memory controller may also convert the bus interface protocol commands into commands conforming to the physical layer communication protocol of the memory controller and the port, which in practical applications is typically the DFI protocol.

The timing control module is used for carrying out protocol conversion on data and instructions, controlling commands and data timing control so as to ensure that the memory access behavior timing sequence of a chip computing system (such as an SoC system) in the simulator FPGA is consistent with the actual memory access behavior timing sequence.

The functions of each of the timing control modules are further described below.

The command memory is used for storing commands sent by the virtual memory controller, and the commands comprise a read operation command and a write operation command. The communication protocols between the virtual memory controller and the virtual port physical layer are different. Therefore, after the virtual memory controller issues the instruction, the virtual port physical layer does not necessarily respond in time, and therefore the instruction needs to be cached in the command memory. That is, the command memory has the functions of buffering instructions and processing data across clock domains.

The command protocol converter is used for converting the command and the data to solve the problem that in the related art, the virtual memory controller performance cannot be verified because the physical layer of the virtual port in the simulator is not matched with the interface protocol of the virtual memory controller designed when the chip is designed. For example, the command protocol converter may convert the DFI protocol of the virtual memory controller into a communication protocol that meets the interface requirements of the virtual port physical layer.

The function guarantee module is used for generating read-write commands and function guarantee commands. The function assurance command may include a refresh instruction, and/or a ZQ calibration instruction, among others. In this embodiment, the designed virtual memory controller is down-converted, which results in a time interval for the virtual memory controller to issue a function command greater than a design time interval when the virtual memory controller is designed, so that normal operation of the second virtual memory cannot be maintained. By adding a function guarantee module in the timing control module, necessary function guarantee commands can be generated. For example, when the second virtual memory is a DDR4 DRAM, the virtual memory controller needs to send a refresh command and a ZQ calibration command periodically, and an excessive command interval may cause abnormal data reading and writing, so that a function guarantee command may be generated by the function guarantee module to solve the problem. In addition, the function guarantee module may also generate other commands for ensuring the normal operation of the virtual port physical layer, which will not be described in detail herein.

The command controller is used for scheduling the read-write command and the function guarantee command according to the design time sequence parameters in the time sequence parameter register so as to ensure that the command is sent to the virtual port physical layer at a reasonable time sequence, and simultaneously, the command sending information is synchronously sent to the write data controller and the read data controller, so that the write data controller and the read data controller send write data at proper time or receive read data. In addition, the command controller can also be used for splitting and merging read and write commands.

The write data storage is used for sending out a write operation instruction when the virtual memory controller fails to process in time, and caching the write operation instruction when the virtual port physical layer fails to process in time.

The write data controller is used for synchronizing the write operation instruction to the write data controller when the command controller sends the write operation instruction to the virtual port physical layer, so that the write data controller controls the write data memory, and data in the write data memory is transmitted to the virtual port physical layer according to the design time sequence parameters after protocol conversion.

The write data protocol converter is used for converting the format of write data. For example, write data is converted from an interface protocol of the virtual memory controller to an interface protocol of the virtual port physical layer.

The read data memory is used for caching data read from the first virtual memory through the virtual port physical layer. Because the virtual port physical layer operates at a higher frequency, the time delay of returning read data is lower than that of the virtual memory controller, and the read data is cached in the read data memory, so that the virtual memory controller can be ensured to acquire a read value from the read data memory in time.

The read data controller is used for synchronizing read operation instruction information to the read data controller when the command controller sends a read operation instruction to the virtual port physical layer, so that the read data controller controls the read data memory, and the read value after protocol conversion is sent to the virtual memory controller according to the design time sequence parameters. The read data controller obtains the design timing parameters from the timing parameter registers.

The read data protocol converter is used for converting the format of read data from the interface protocol of the virtual port physical layer to the interface protocol of the virtual port physical layer.

The virtual port physical layer is a high-speed PHY of an emulator FPGA, and is used for converting data signals between the memory controller and the first virtual memory into analog signals and providing proper time sequence, voltage and interface control.

The first virtual memory is used for storing data.

Illustratively, SPECint provided by the standard performance assessment organization (Standard Performance Evaluation Corporation, SPEC) is one of the most common benchmark tests for CPU performance tests. However, the test method is complex, the simulation software is slow, and the quick iteration of the CPU test is difficult to realize.

Memory controllers commonly used for chip streaming are often connected to the PHY through a DFI interface. The PHY commonly used for streaming typically comprises a digital part and an analog part, the analog part is not common on FPGAs, and the PHY lacks a DFI interface on FPGAs. In addition, because the performance of the FPGA chip itself is limited, the virtual processor cannot operate at a high frequency, and therefore, when the FPGA emulates the virtual chip and operates, it is necessary to perform equal-scale down-conversion processing on each module in the virtual chip. But due to performance limitations of the storage medium in the virtual chip, it may have an operation error after the down conversion process.

For example, in the case where the storage medium is a DDR4 chip, the storage medium must be operated in a high frequency mode to ensure that the storage medium operates normally. Specifically, the storage medium is a DDR4 chip, when the DDR4 operates in a Delay-Locked Loop off (DLL off) mode, a PHY supporting the DLL off mode is required, and the DDR4 chip needs to be periodically refreshed and ZQ calibrated to ensure accuracy of data. Because the DDR4 refresh and ZQ calibration interval is limited, in the DLL mode, although the DDR4 and a processor (such as a CPU) can achieve equal proportion frequency reduction, the chip access test is inaccurate due to the difference of refresh and ZQ calibration frequency.

The equal proportion frequency reduction of each module in the chip can cause abnormal operation, but if only the processor is subjected to frequency reduction, but the storage medium is not subjected to frequency reduction, frequency inversion phenomenon can be caused, and the situation can cause high performance test of the processor.

In one embodiment, referring to fig. 7, a chip test system includes a virtual chip including a virtual processor, a virtual memory controller, and a second virtual memory, a virtual protocol converter (not shown), a virtual port physical layer, and a first virtual memory.

Wherein, the communication protocols of the virtual port physical layer and the virtual memory controller are different;

The virtual processor is used for transmitting a read operation instruction to the virtual memory controller, carrying out protocol conversion on the read operation instruction through the virtual protocol converter according to a communication protocol of the virtual port physical layer, and transmitting the read operation instruction after the protocol conversion to the virtual port physical layer;

And the virtual memory controller is used for extracting a read value from the first virtual memory so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value.

Fig. 8 is a flowchart illustrating specific steps of a method for testing a chip according to an embodiment of the present application. In the illustration of fig. 8, the virtual processor and virtual memory controller are subjected to an equal scale down process. As shown in fig. 8, the method may include:

step S1, a chip test system is built in the simulator.

Wherein, the simulator is FPGA.

The method of this step is described in the foregoing step 201, and will not be described here again.

And S2, sending a read-write operation instruction to the virtual memory controller through the virtual processor.

Specifically, a read operation instruction is sent to the memory controller through an on-chip bus between the virtual processor and the virtual memory controller.

And step S3, sending the read-write operation instruction to the time sequence control module through the virtual memory controller.

Specifically, the virtual memory controller performs protocol conversion, scheduling and prefetching on the read-write operation instruction, and sends the processed read-write operation instruction to the time sequence control module.

Wherein, the protocol conversion includes: the read-write operation instruction is converted from an on-chip bus interface protocol to a virtual memory controller downward interface protocol, for example, the on-chip bus interface protocol is converted to a DFI interface protocol.

And S4, performing protocol conversion on the read-write operation instruction through the time sequence control module to obtain the read-write operation instruction meeting the communication protocol requirements of the physical layer of the virtual port.

For example, if the downward interface of the virtual memory controller is a DFI interface, the read-write operation instruction is converted from a DFI interface protocol to a communication protocol conforming to the interface requirement of the PHY through protocol conversion.

And S5, transmitting the read-write operation instruction after protocol conversion to the virtual port physical layer through the time sequence control module.

Specifically, the time sequence control module sends read-write operation instructions subjected to protocol conversion processing and function guarantee commands for ensuring normal operation of the virtual port physical layer and the storage medium to the virtual port physical layer according to design time sequence parameters.

Illustratively, the clock frequencies of the timing control module, the virtual port physical layer, and the second virtual memory are all higher than the clock frequency of the virtual memory controller. Therefore, the read-write operation instruction can be timely completed, and the data obtained by executing the read-write operation instruction is stored in the time sequence control module in advance before the virtual memory controller acquires the data from the time sequence control module.

For example, the virtual port physical layer operates at a higher clock frequency, and when executing the read operation instruction, the read value can be cached in the time sequence control module in advance, so that the virtual memory controller can obtain the read value from the time sequence control module according to the design clock parameter, further, the simulation precision of the virtual chip is ensured, and the accuracy of the chip performance test is improved.

For example, when executing the write operation instruction, the write data also needs to be cached and converted in protocol in advance, and the write data is sent to the virtual port physical layer according to the design timing parameter, so that the write data is written into the second virtual memory through the virtual port physical layer. By caching and protocol conversion, writing the write data into the second virtual memory according to the design time sequence parameters, the simulation precision is ensured, and the accuracy of the chip performance test is improved.

And S6, performing read-write operation through the virtual port physical layer, obtaining a read-write operation result according to the first design time sequence parameter stored in the time sequence control module, determining whether the function of the chip meets the preset chip function design requirement according to the read-write operation result, and determining whether the performance of the chip meets the preset chip performance design requirement according to the moment of acquiring the read-write operation result.

Specifically, when the read operation is executed, the read operation instruction is a read operation instruction, and the virtual port physical layer responds to the read operation instruction to read data from the first virtual memory and send the data to the time sequence control module.

The time sequence control module carries out protocol conversion on the read value and returns the read value to the memory controller, and the memory controller returns the read value to the virtual processor.

The virtual processor determines whether the function of the chip reaches the preset chip function design requirement according to the read value, and determines whether the performance of the chip reaches the preset chip performance design requirement according to the moment of acquiring the read value.

The chip testing method of the present application will be further exemplarily described with reference to fig. 6 and 9 by taking a read operation as an example. In this embodiment, the chip testing method may include the following steps:

and step M1, sending a read command to the virtual memory controller through the virtual processor.

Specifically, the virtual processor sends a command to the virtual memory controller via the on-chip bus, where the command in this step is a command indicating that the virtual memory controller reads data from the first virtual memory.

Step M2, send the read command to the command memory through the virtual memory controller, the command memory stores the read command.

In the write test, the command sent by the virtual processor is a write command, and the virtual memory control sends the write command to the command memory to store the write command.

And step M3, responding to the function guarantee command sent by the function guarantee module through the command controller, and sending the function guarantee command to the first virtual memory through the virtual port physical layer according to the designed time interval so as to enable the first virtual memory to execute the function guarantee command.

Illustratively, the function assurance command includes a refresh instruction, and/or a ZQ calibration instruction.

The problem that the second virtual memory cannot work normally due to overlarge time interval of the functional instruction sent by the virtual memory controller caused by the fact that the clock frequency of the virtual memory controller is lower than the design frequency of the virtual memory controller can be solved through the function guarantee command.

In addition, through the function guarantee module, a function guarantee command is also sent to the virtual port physical layer according to the designed time interval, so that the normal operation of the virtual port physical layer is ensured.

And step M4, responding to the instruction which indicates that the first virtual memory has executed the function guarantee command and is fed back by the virtual port physical layer through the command controller, acquiring a read command from the command memory, performing protocol conversion on the read command through the command protocol converter, and sending the converted read command to the virtual port physical layer and the read data controller.

Because of the function limitation of the first virtual memory, the virtual processor, the virtual memory controller and the first virtual memory in the virtual chip cannot be subjected to equal-proportion frequency reduction, which can cause abnormal time interval of a function guarantee command sent by the virtual memory controller, so that the first virtual memory medium works abnormally, and the simulation result is inaccurate. The function guarantee command may include instructions that instruct the first virtual memory refresh, and/or the ZQ resistance calibration.

The function guarantee module is added in the time sequence control module to generate a function guarantee command, and the command controller coordinates the sending time of various commands to ensure the normal functions of the virtual port physical layer and the first virtual memory and ensure the simulation precision.

Illustratively, the downward interface of the virtual memory controller is a DFI interface and the interface of the virtual port physical layer is a MIG interface. The command protocol converter is used for converting the read command into the read command conforming to the interface protocol of the virtual port physical layer, so that the virtual port physical layer can receive and recognize the command and further execute the read operation. The problem that in the related art, the performance of a chip memory controller cannot be tested because the PHY with a DFI interface is lacking in the FPGA is solved.

Responding to the feedback of the virtual port physical layer to indicate that the first virtual memory has executed the function guarantee command, acquiring a read command from the command memory, performing protocol conversion on the read command through the command protocol converter, and sending the converted read command to the virtual port physical layer, so that the problem of bus blocking caused by operation due to the fact that the read command is sent in the process of executing refreshing and/or ZQ calibration of the first virtual memory can be avoided.

And M5, reading data from the second virtual memory through the virtual port physical layer, performing signal conversion processing on the read data, and storing the data into the read data memory.

The read value stored in the read data memory accords with the communication protocol required by the interface of the virtual port physical layer.

Specifically, both the first virtual memory and the virtual port physical layer operate at higher clock frequencies to ensure that the return latency of the read values is sufficiently small. Furthermore, the clock frequency of the physical layer of the first virtual memory and the virtual port is higher than that of the virtual memory controller, so that the data read from the second virtual memory can be stored into the read data memory before the virtual memory controller reads the data from the read data memory, the virtual memory controller can acquire the read value from the read data memory in time, and the read command sent by the virtual memory controller can respond in time.

And step M6, acquiring design time sequence parameters from the time sequence parameter register through the read data controller, and reading data from the read data memory according to the read command and the design time sequence parameters sent by the command controller.

Illustratively, the data is read from the read data store is determined based on the design timing parameters, relative to the latency of receiving the read command, and the data is read from the read data store.

In this embodiment, the clock frequency of the virtual processor is lower than the design frequency when the virtual processor is designed, and if the read operation is not delayed, the finally obtained read operation performance test result will be higher than the actual read operation performance of the design chip. The read value is stored in the read value memory, and then the data is read from the read value memory according to the design time sequence parameter, so that the read value is returned to the virtual memory controller, the accuracy of the time sequence of the read data is ensured, the accuracy of the read operation performance test result is improved, and the problem of low accuracy of the test result caused by frequency hanging is solved.

And step M7, performing protocol conversion on the read value read from the read data memory through the read data protocol converter, and returning the converted read value to the virtual memory controller.

Specifically, the read value of the communication protocol of the interface conforming to the physical layer of the virtual port is converted into the read value of the DFI interface protocol conforming to the virtual memory controller by the read data protocol converter.

And M8, performing protocol conversion on the read value through the virtual memory controller, and returning the converted read value to the virtual processor.

Specifically, the read value of the DFI interface protocol conforming to the virtual memory controller is converted into the read value conforming to the on-chip bus protocol, and sent to the virtual processor through the on-chip bus.

And step M9, determining whether the read operation reaches the preset test requirement or not according to the read value by the virtual processor.

For example, the virtual processor compares the read value and writes the write value into the first virtual memory for the virtual memory controller to read, and determines that the read operation test meets the preset test requirement under the condition that the read value and the write value are the same.

Referring to fig. 10, which shows a chip testing apparatus provided in an embodiment of the present application, a chip testing apparatus 30 includes:

A building module 301, configured to build a chip test system in the simulator, where the chip test system includes a virtual chip, a virtual protocol converter, a virtual port physical layer, and a first virtual memory, and the virtual chip includes a virtual processor, a virtual memory controller, and a second virtual memory; the communication protocols of the virtual port physical layer and the virtual memory controller are different;

The first sending module 302 is configured to respond to a read operation instruction sent by the virtual processor to the virtual memory controller, perform protocol conversion on the read operation instruction through the virtual protocol converter according to a communication protocol of the virtual port physical layer, and send the read operation instruction after the protocol conversion to the virtual port physical layer;

a first obtaining module 303, configured to read data from the second virtual memory through the virtual port physical layer and perform signal conversion processing, obtain a read value of the signal conversion processing, and store the read value into the first virtual memory;

the first determining module 304 is configured to extract, by the virtual memory controller, a read value from the first virtual memory, so as to determine whether the function of the virtual chip meets a preset chip function design requirement according to the read value.

Optionally, a clock frequency at which the virtual processor runs in the emulator is less than a first design frequency at which the virtual processor is designed;

the first determining module 304 includes:

the first acquisition sub-module is used for acquiring a first design time sequence parameter of the virtual memory controller when the virtual memory controller is designed; the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and acquiring read-write data at the read-write time;

The second obtaining sub-module is used for obtaining the reading value from the first virtual memory according to the first design time sequence parameter through the virtual memory controller.

Optionally, the chip testing apparatus 30 further includes:

The second determining module is configured to, after reading data from the second virtual memory through the virtual port physical layer and performing signal conversion processing, obtain a read value of the signal conversion processing, and store the read value into the first virtual memory, obtain, by using the virtual memory controller, the read value from the first virtual memory according to the first design timing sequence parameter, so as to determine whether the performance of the virtual chip meets a preset chip performance design requirement according to the time when the read value is obtained.

Optionally, the chip test system further includes a third virtual memory, and the chip test apparatus 30 further includes:

The first writing module is used for responding to the writing operation instruction sent by the virtual processor to the virtual memory controller, carrying out protocol conversion on the writing operation instruction according to the communication protocol of the virtual port physical layer, responding to the writing operation instruction sent by the virtual processor to the virtual memory controller before the reading operation instruction after the protocol conversion is sent to the virtual port physical layer, storing the writing data in the writing operation instruction into the third virtual memory, carrying out protocol conversion on the writing operation instruction through the virtual protocol converter according to the communication protocol of the virtual port physical layer, and sending the writing operation instruction after the protocol conversion to the virtual port physical layer;

The second obtaining module is used for obtaining the write data from the third virtual memory through the virtual port physical layer and writing the write data into the second virtual memory so as to read the data from the second virtual memory through the virtual port physical layer later.

Optionally, the clock frequency at which the virtual processor runs in the emulator is less than the design frequency at which the virtual processor is designed;

a second acquisition module comprising:

The third acquisition sub-module is used for acquiring a first design time sequence parameter of the virtual memory controller when the virtual memory controller is designed; the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and reading and writing data at the read-write time;

And the fourth acquisition sub-module is used for storing the write data in the write operation instruction into the third virtual memory according to the first design time sequence parameter.

Optionally, the chip test system further includes a fourth virtual memory; the first transmitting module 302 may include:

The first storage sub-module is used for responding to a read operation instruction sent by the virtual processor to the virtual memory controller and storing the read operation instruction in the fourth virtual memory;

And the first sending submodule is used for carrying out protocol conversion on the read operation instruction stored in the fourth virtual memory according to the communication protocol of the virtual port physical layer after receiving the instruction of the second virtual memory for completing the function guarantee operation through the virtual port physical layer, and sending the read operation instruction after the protocol conversion to the virtual port physical layer. And the function guarantee operation is used for enabling the second virtual memory to perform correct read-write operation.

the second storage sub-module is used for responding to a read operation instruction sent by the virtual processor to the virtual memory controller and storing the read operation instruction in the fourth virtual memory;

A fifth obtaining sub-module, configured to obtain a second design timing parameter of the virtual memory controller when the virtual memory controller is designed; the second design time sequence parameter is used for determining the instruction sending time matched with the second design time sequence parameter when the read-write operation instruction is sent subsequently;

And the second sending submodule is used for carrying out protocol conversion on the read operation instruction stored in the fourth virtual memory according to the communication protocol of the virtual port physical layer and sending the read operation instruction after the protocol conversion to the virtual port physical layer.

Optionally, the first determining module 304 includes:

a sixth obtaining sub-module, configured to perform protocol conversion on the read value according to a communication protocol of the virtual memory controller, to obtain a read value after the protocol conversion;

The third sending submodule is used for sending the read value after the protocol conversion to the virtual processor through the virtual memory controller;

the first determining submodule is used for determining whether the function of the virtual chip reaches the preset chip function design requirement or not according to the read value after protocol conversion through the virtual processor.

Optionally, the clock frequency of the virtual memory is greater than a second design frequency when designing the virtual memory controller; the chip testing apparatus 30 further includes:

the third acquisition module is used for acquiring a third design time sequence parameter of the virtual memory controller when the virtual memory controller is designed; the third design time sequence parameter is used for determining the time for sending the function guarantee operation instruction;

And the second sending module is used for sending a function guarantee operation instruction to the second virtual memory according to the third design time sequence parameter so as to perform the function guarantee operation on the second virtual memory. The function guarantees the operation, is used for making the second virtual memory obtain the correct read-write data.

Optionally, the second virtual memory has a clock frequency greater than the clock frequency of the virtual memory controller to store data in the first virtual memory before the read value is fetched from the first virtual memory by the virtual memory controller.

In the embodiment of the application, the virtual processor sends the read operation instruction to the virtual memory controller, and the read operation instruction is not directly sent to the virtual port physical layer, but is subjected to protocol conversion according to the communication protocol of the virtual port physical layer, and the read operation instruction after the protocol conversion is sent to the virtual port physical layer. After the read value is obtained from the second virtual memory through the virtual port physical layer, the read value is not directly returned to the virtual memory controller, but is stored into the first virtual memory, and the virtual memory controller obtains the read value from the first virtual memory so as to determine whether the read operation performance of the virtual chip meets the preset requirement according to the read value. The test process needs to be completed by the virtual processor and the virtual memory controller together. Based on the test result of the read operation obtained by the method of the embodiment, the read operation performance of the virtual processor and the virtual memory controller can be reflected at the same time, and the problem that in the related art, the performance of the virtual memory controller cannot be tested because the virtual port physical layer with the same interface as the chip memory controller is lacking in the simulator, so that the communication protocols between the virtual port physical layer and the virtual memory controller in the virtual chip are different is solved.

Fig. 11 is a block diagram of an electronic device 400, according to an example embodiment. For example, electronic device 400 may be a mobile phone, computer, digital broadcast terminal, messaging device, game console, tablet device, medical device, exercise device, personal digital assistant, or the like.

Referring to fig. 11, an electronic device 400 may include one or more of the following components: a processing component 402, a memory 404, a power supply component 406, a multimedia component 408, an audio component 410, an input/output (I/O) interface 412, a sensor component 414, and a communication component 416.

The processing component 402 generally controls overall operation of the electronic device 400, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 402 can include one or more modules that facilitate interaction between the processing component 402 and other components. For example, the processing component 402 may include a multimedia module to facilitate interaction between the multimedia component 408 and the processing component 402.

Memory 404 is used to store various types of data to support operations at electronic device 400. Examples of such data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, multimedia, and so forth. The memory 404 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power supply component 406 provides power to the various components of the electronic device 400. The power components 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 400.

The multimedia component 408 includes a screen between the electronic device 400 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may not only sense demarcations of touch or sliding actions, but also detect durations and pressures associated with touch or sliding operations. In some embodiments, the multimedia component 408 includes a front camera and/or a rear camera. When the electronic device 400 is in an operational mode, such as a photographing mode or a multimedia mode, the front-facing camera and/or the rear-facing camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

The audio component 410 is for outputting and/or inputting audio signals. For example, the audio component 410 includes a Microphone (MIC) for receiving external audio signals when the electronic device 400 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 404 or transmitted via the communication component 416. In some embodiments, audio component 410 further includes a speaker for outputting audio signals.

The I/O interface 412 provides an interface between the processing component 402 and peripheral interface modules, which may be a keyboard, click wheel, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.

The sensor assembly 414 includes one or more sensors for providing status assessment of various aspects of the electronic device 400. For example, the sensor assembly 414 may detect an on/off state of the electronic device 400, a relative positioning of the components, such as a display and keypad of the electronic device 400, the sensor assembly 414 may also detect a change in position of the electronic device 400 or a component of the electronic device 400, the presence or absence of a user's contact with the electronic device 400, an orientation or acceleration/deceleration of the electronic device 400, and a change in temperature of the electronic device 400. The sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 414 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 416 is used to facilitate communication between the electronic device 400 and other devices, either wired or wireless. The electronic device 400 may access a wireless network based on a communication standard, such as WiFi, an operator network (e.g., 2G, 3G, 4G, or 5G), or a combination thereof. In one exemplary embodiment, the communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 416 further includes a Near Field Communication (NFC) module to facilitate short range communications. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 400 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for implementing a chip testing method as provided by an embodiment of the application.

In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as memory 404, that includes instructions executable by processor 420 of electronic device 400 to perform the above-described method. For example, the non-transitory storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

Fig. 12 is a block diagram of an electronic device 500, according to an example embodiment. For example, electronic device 500 may be provided as a server. Referring to fig. 12, electronic device 500 includes a processing component 522 that further includes one or more processors and memory resources represented by memory 532 for storing instructions, such as applications, executable by processing component 522. The application programs stored in the memory 532 may include one or more modules each corresponding to a set of instructions. In addition, the processing component 522 is configured to execute instructions to perform a chip testing method provided by an embodiment of the present application.

The electronic device 500 may also include a power component 526 configured to perform power management of the electronic device 500, a wired or wireless network interface 550 configured to connect the electronic device 500 to a network, and an input output (I/O) interface 558. The electronic device 500 may operate based on an operating system stored in the memory 532, such as Windows Server, mac OS XTM, unixTM, linuxTM, freeBSDTM, or the like.

The embodiment of the application also provides a computer program product, which comprises a computer program, and a chip testing method realized when the computer program is executed by a processor.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

The foregoing is only illustrative of the present application and is not to be construed as limiting thereof, but rather as various modifications, equivalent arrangements, improvements, etc., within the spirit and principles of the present application.

The above detailed description of the chip testing method, the device, the electronic equipment and the readable storage medium provided by the application applies specific examples to illustrate the principle and the implementation of the application, and the above description of the examples is only used for helping to understand the method and the core idea of the application; meanwhile, as those skilled in the art will vary in the specific embodiments and application scope according to the idea of the present application, the present disclosure should not be construed as limiting the present application in summary.

Claims

1. A method of testing a chip, comprising:

And acquiring the read value from the first virtual memory according to a first design time sequence parameter through the virtual memory controller so as to determine whether the function of the virtual chip meets the preset chip function design requirement according to the read value.

2. The method of claim 1, wherein a clock frequency at which the virtual processor is run in the emulator is less than a first design frequency at which the virtual processor is designed;

The retrieving, by the virtual memory controller, the read value from the first virtual memory includes:

Acquiring a first design time sequence parameter of the virtual memory controller when the virtual memory controller is designed; the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and acquiring read-write data at the read-write time;

and acquiring the reading value from the first virtual memory according to the first design time sequence parameter through the virtual memory controller.

3. The method according to claim 2, further comprising, after reading data from the second virtual memory through the virtual port physical layer and performing signal conversion processing, obtaining a read value of the signal conversion processing and storing the read value in the first virtual memory:

And acquiring the read value from the first virtual memory according to the first design time sequence parameter through the virtual memory controller so as to determine whether the performance of the virtual chip meets the preset chip performance design requirement according to the moment of acquiring the read value.

4. The method of claim 1, wherein the chip test system further comprises a third virtual memory that, before responding to a read operation instruction sent by the virtual processor to the virtual memory controller, performs a protocol conversion on the read operation instruction according to a communication protocol of the virtual port physical layer, and sends the read operation instruction after the protocol conversion to the virtual port physical layer, comprises:

Responding to a write operation instruction sent by the virtual processor to the virtual memory controller, storing write data in the write operation instruction into the third virtual memory, carrying out protocol conversion on the write operation instruction through the virtual protocol converter according to a communication protocol of the virtual port physical layer, and sending the write operation instruction after the protocol conversion to the virtual port physical layer;

And acquiring write data from the third virtual memory through the virtual port physical layer, and writing the write data into the second virtual memory so as to read data from the second virtual memory through the virtual port physical layer later.

5. The method of claim 4, wherein a clock frequency at which the virtual processor is run in the emulator is less than a design frequency at which the virtual processor is designed;

The responding to the writing operation instruction sent by the virtual processor to the virtual memory controller, storing the writing data in the writing operation instruction into the third virtual memory, comprising:

acquiring a first design time sequence parameter of the virtual memory controller when the virtual memory controller is designed; the first design time sequence parameter is used for determining the read-write time matched with the first design time sequence parameter when the read-write operation is executed subsequently, and reading and writing data at the read-write time;

and storing the write data in the write operation instruction into the third virtual memory according to the first design time sequence parameter.

6. The method of claim 1, wherein the chip test system further comprises a fourth virtual memory;

The responding to the read operation instruction sent by the virtual processor to the virtual memory controller, performing protocol conversion on the read operation instruction according to the communication protocol of the virtual port physical layer, and sending the read operation instruction after the protocol conversion to the virtual port physical layer, including:

Responding to a read operation instruction sent by the virtual processor to the virtual memory controller, and storing the read operation instruction in the fourth virtual memory;

After receiving an instruction of the second virtual memory to finish function guarantee operation through the virtual port physical layer, performing protocol conversion on the read operation instruction stored in the fourth virtual memory according to a communication protocol of the virtual port physical layer, and sending the read operation instruction after protocol conversion to the virtual port physical layer;

the function guarantee operation is used for enabling the second virtual memory to perform correct read-write operation.

7. The method of claim 1, wherein the chip test system further comprises a fourth virtual memory;

Acquiring a second design time sequence parameter of the virtual memory controller when the virtual memory controller is designed; the second design time sequence parameter is used for determining the instruction sending time matched with the second design time sequence parameter when the read-write operation instruction is sent subsequently;

And according to the second design time sequence parameter, according to the communication protocol of the virtual port physical layer, carrying out protocol conversion on the read operation instruction stored in the fourth virtual memory, and sending the read operation instruction after protocol conversion to the virtual port physical layer.

8. The method of claim 1, wherein the retrieving, by the virtual memory controller, the read value from the first virtual memory to determine whether the function of the virtual chip meets a preset chip function design requirement based on the read value, comprises:

According to the communication protocol of the virtual memory controller, carrying out protocol conversion on the read value to obtain a read value after protocol conversion;

Transmitting the read value after protocol conversion to the virtual processor through the virtual memory controller;

And determining whether the function of the virtual chip reaches the preset chip function design requirement or not according to the read value after protocol conversion by the virtual processor.

9. The method of claim 1, wherein a clock frequency of the second virtual memory is greater than a second design frequency when designing the virtual memory controller; the method further comprises the steps of:

Acquiring a third design time sequence parameter of the virtual memory controller when the virtual memory controller is designed; the third design time sequence parameter is used for determining the moment of sending the function guarantee operation instruction;

According to the third design time sequence parameter, a function guarantee operation instruction is sent to the second virtual memory so as to perform function guarantee operation on the second virtual memory;

The function guarantee operation is used for enabling the second virtual memory to acquire correct read-write data.

10. The method of claim 1, wherein a clock frequency of the second virtual memory is greater than a clock frequency of the virtual memory controller to store the read value in the first virtual memory prior to the read value being extracted from the first virtual memory by the virtual memory controller.

11. The chip test system is characterized by comprising a virtual chip, a virtual protocol converter, a virtual port physical layer and a first virtual memory, wherein the virtual chip comprises a virtual processor, a virtual memory controller and a second virtual memory; the communication protocols of the virtual port physical layer and the virtual memory controller are different;

The virtual processor is configured to send a read operation instruction to the virtual memory controller, so that the virtual protocol converter performs protocol conversion on the read operation instruction through a communication protocol of the virtual port physical layer, and sends the read operation instruction after the protocol conversion to the virtual port physical layer;

The virtual memory controller is configured to extract the read value from the first virtual memory according to a first design timing parameter, so as to determine whether the function of the virtual chip meets a preset chip function design requirement according to the read value.

12. A chip testing apparatus, comprising:

The first determining module is configured to obtain, by using the virtual memory controller, the read value from the first virtual memory according to a first design timing parameter, so as to determine, according to the read value, whether a function of the virtual chip meets a preset chip function design requirement.

13. An electronic device, comprising: a processor;

a memory for storing the processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the method of any one of claims 1 to 10.

14. A computer readable storage medium, characterized in that instructions in the computer readable storage medium, when executed by a processor of an electronic device, enable the electronic device to perform the method of any one of claims 1 to 10.