CN115048308A - Chip simulation method and system based on automobile software test - Google Patents
Chip simulation method and system based on automobile software test Download PDFInfo
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Abstract
The application provides a chip simulation method and a chip simulation system based on automobile software testing, which relate to the field of automobile software testing, wherein the method comprises the following steps: virtualization and execution of compiled ECU software (HEX/S19) on a personal computer, real-time or super-real-time simulation are realized based on a virtual ECU platform, software function test and fault injection test are directly carried out on the personal computer, and better safety test and more effective test process on the ECU are realized. The software development period can be shortened, the software quality is improved, hardware-in-loop rack resources are saved, and the reuse of testers and developers can be facilitated. The technical problems that in the prior art, high-precision signal requirements, safety of large voltage and large current, and abnormal related functions of tested controller hardware and chips cannot be tested are solved. The technical effects of high safety and high precision in software testing, capability of testing the abnormal functions of the hardware of the tested controller and improvement of test coverage are achieved.
Description
Technical Field
The application relates to the field of automobile software testing, in particular to a chip simulation method and system based on automobile software testing.
Background
At present, the HIL (Hardware-in-the-Loop) is widely applied to automobile software testing due to the advantages of shortening the development period, reducing the cost, being convenient and the like, but the problems of high-precision signal requirements, safety of large voltage and large current, incapability of testing functions related to abnormality of Hardware and chips of a tested controller and the like still cannot be solved by the HIL system, so that the expansion of a new testing mode is very important.
Based on the problems, the chip simulation method based on the automobile software test is provided, compared with the chip-level simulation test technology, the chip-level simulation test method is low in cost, safe and reliable, supports boundary and fault injection test, and easily finds hidden problems in software, so that the method is a good choice for constructing a full-digital simulation test framework for embedded software.
Disclosure of Invention
The technical purpose to be achieved by the embodiment of the application is to provide a chip simulation method and system based on automobile software testing, which are used for solving the technical problems that in the prior art, high-precision signal requirements, safety of large voltage and large current, hardware of a tested controller and functions related to chip abnormity cannot be tested. The safety and the precision in software testing are high, the abnormal functions of the hardware of the tested controller can be tested, and the test coverage is improved; the method is simple, visual and convenient to operate; the method can be used for debugging by developers, so that the debugging work is advanced, the development period is shortened, the software quality is improved, and the hardware-in-loop rack resource is saved.
In order to solve the technical problem, the embodiment of the application provides a chip simulation method and system based on an automobile software test.
In a first aspect of the present application, a chip simulation method based on an automobile software test is provided, where the method includes: based on Eclipse, acquiring a graphical modeling framework; simulating and developing a virtual controller by utilizing the graphical modeling framework and the configuration parameters, wherein the virtual controller is used for performing functional modeling simulation on embedded system hardware; building a test environment model based on a User Datagram Protocol (UDP), wherein the test environment is used for meeting the functional requirements of the virtual controller to perform target software test; acquiring a test data set of the target software, wherein the test data set comprises a function requirement document, a hard wire pin definition and a communication data protocol; establishing a target test environment model of the target software based on the test data set and the test environment model; and executing a test function on the target software by using the virtual controller through the target test environment model, and generating a target test report.
In a second aspect of the present application, a chip simulation system based on an automobile software test is provided, the system including: the framework obtaining module is used for obtaining a graphical modeling framework based on Eclipse; the virtual controller development module is used for simulating and developing a virtual controller by utilizing the graphical modeling framework and the configuration parameters, wherein the virtual controller is used for performing functional modeling simulation on embedded system hardware; the virtual controller comprises a test environment model building module, a virtual controller building module and a virtual controller testing module, wherein the test environment model building module is used for building a test environment model based on UDP (user Datagram protocol), and the test environment is used for meeting the functional requirements of the virtual controller and carrying out target software test; the test data acquisition module is used for acquiring a test data set of the target software, wherein the test data set comprises a function requirement document, a hard wire pin definition and a communication data protocol; the target environment model establishing module is used for establishing a target test environment model of the target software based on the test data set and the test environment model; and the software testing module is used for executing a testing function on the target software by utilizing the virtual controller through the target testing environment model and generating a target testing report.
In a third aspect of the present application, a terminal is provided, which is characterized by comprising a processor, a memory and a computer program stored on the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of the chip simulation method based on the automobile software test as described above.
In a fourth aspect of the present application, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and when being executed by a processor, the computer program implements the steps of the chip simulation method based on the automobile software test as described above.
Compared with the prior art, the chip simulation method and system based on the automobile software test provided by the embodiment of the application have at least the following beneficial effects:
virtualization and execution of compiled ECU (Electronic Control Unit) software (HEX/S19) on a Personal Computer (PC) are realized based on a virtual ECU platform, real-time or super-real-time simulation is realized, software function test and fault injection test are directly carried out on the PC, and better safety test and more effective test process on the ECU are realized. The software development period can be shortened, the software quality is improved, hardware-in-loop rack resources are saved, and the reuse of testers and developers can be facilitated.
Drawings
Fig. 1 is a schematic flow chart of a chip simulation method based on an automobile software test provided in the present application;
FIG. 2 is a schematic diagram illustrating a graphical modeling principle in a chip simulation method based on an automobile software test according to the present application;
fig. 3 is a schematic diagram illustrating a principle of converting a CAN signal into a UDP signal in the chip simulation method based on the automobile software test provided by the present application;
fig. 4 is a schematic diagram of a UDP sending model in a chip simulation method based on an automobile software test according to the present application;
fig. 5 is a schematic flow chart illustrating a test function executed on the target software in the chip simulation method based on the automobile software test according to the present application;
FIG. 6 is a schematic diagram illustrating a testing process of a chip simulation testing platform in the chip simulation method based on the automobile software testing provided by the present application;
fig. 7 is a schematic structural diagram of a chip simulation system based on an automobile software test according to the present application.
Detailed Description
To make the technical problems, technical solutions and advantages to be solved by the present application clearer, the following detailed description is made with reference to the accompanying drawings and specific embodiments. In the following description, specific details such as specific configurations and components are provided only to help the embodiments of the present application be fully understood. Accordingly, it will be apparent to those skilled in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, descriptions of well-known functions and constructions are omitted for clarity and conciseness.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In various embodiments of the present application, it should be understood that the sequence numbers of the following processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
It should be understood that the term "and/or" herein is merely one type of association relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In the embodiments provided herein, it should be understood that "B corresponding to a" means that B is associated with a from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.
Example one
As shown in fig. 1, the present application provides a chip simulation method based on an automobile software test, the method includes:
step S100: based on Eclipse, acquiring a graphical modeling framework;
step S200: simulating and developing a virtual controller by utilizing the graphical modeling framework and the configuration parameters, wherein the virtual controller is used for performing functional modeling simulation on embedded system hardware;
further, step S200 includes:
step S210: acquiring a software architecture set based on the graphical modeling framework, wherein the software architecture set comprises a project resource list, model attribute configuration, a virtual controller model, a model library and a control view;
step S220: and carrying out self-defined parameter configuration on various graphical models by utilizing the configuration parameters and the software architecture set so as to simulate the virtual controller.
Particularly, the chip simulation method based on the automobile software test is provided, compared with the chip-level simulation test technology, the chip-level simulation test method is low in cost, safe and reliable, supports boundary and fault injection test, and easily finds hidden problems in software, so that the method is a good choice for constructing a full-digital simulation test framework for embedded software. The chip simulation test technology platform can carry out complete digital simulation on a hardware environment in which the embedded software operates, and provides functions of automatic test, fault simulation and injection, coverage analysis, single-step debugging and the like. A user can operate the embedded software on the platform without hardware, and the embedded software can be tested and verified without corresponding hardware equipment and a hardware simulation rack.
Virtualization and execution of compiled ECU software (HEX/S19) on a personal computer, real-time or super-real-time simulation are realized based on a virtual ECU platform, software function test and fault injection test are directly carried out on the personal computer, and better safety test and more effective test process on the ECU are realized. The software development period can be shortened, the software quality is improved, hardware-in-loop rack resources are saved, and the reuse of testers and developers can be facilitated. The chip simulation platform mainly comprises three parts: chip simulation, environment model, test case and execution. Compared with the HIL, the chip simulation platform has no real hardware, and the tested controller and the environment model are both operated on the personal computer, so that the HIL equipment can be avoided from being limited by the chip simulation platform to realize the transmission of high-precision signals, the safety concern of large voltage and large current can be eliminated, and meanwhile, the test of the function of the tested controller related to the bottom layer drive abnormity processing can be carried out.
Meanwhile, the chip simulation platform has multiple functions, including supporting TC277 and TC387 chip simulation functions and supporting an English-flying related chip, and besides, the platform needs to have an expansion function so as to simulate other chips on the same platform; the platform CAN simulate the simulation of Communication buses such as TC277 and TC387 chips CAN, IO (Input Output), SSC (Spread Spectrum Communication), LIN (Local Interconnect Network) and the like; support all emulation of EEPROM (Electrically Erasable Programmable Read-Only Memory), AD (analog-to-Digital), high-low side chip, AD on chip and other devices; the fault injection of registers and memories of all 0, all 1 and data errors is supported; supporting the use of an instruction set simulator, some low-level driven program functions can be skipped or replaced through the libraries during the construction of the chip simulation environment. For example: NVM (Non-volatile Memory) simulation, CAN simulation, ADC (analog-to-Digital Conversion) simulation, etc.; a static analysis tool of hex/s19 can be provided, a good assembly code document can be generated from the hex/s19 file, and a calling relation tree of functions can be generated; supporting the simulation function of the operating system, such as the scheduling of function tasks and interrupt processing programs; step-by-step simulation is supported, and the real-time performance of simulation is guaranteed or is faster than that of real-time simulation; the method supports extracting relevant functions from the hex/s19 file, analyzing input and output of the functions, and executing the functions only by taking the relevant input/output as an interface to realize execution of the functions or module testing; the program debugger can be provided and has the functions of step by step, execution tracking, register view and online diagnosis; the platform should provide a friendly graphical user interface and a virtual dashboard including common driver inputs, graphical and curvilinear displays, calibration tables, etc.; the fault injection test between the chip simulation environment and the controlled model is supported and can be controlled by a small part of an interface or a test script; support commonly used automotive protocols and related standards, such as: CAN bus, CAN-FD (CAN with Flexible Data rate, variable rate controller area network), Flexray, LIN (support multiple channels); XCP (Universal measurement and Calibration Protocol) for Calibration, interpretation and use A2L (where third party tools such as CANape, INCA can be connected); and flashing or storing the calibration parameters.
First, a simulation development of the virtual controller is required. The virtual controller performs functional modeling on the embedded system hardware, simulates and simulates the hardware architecture and behavior thereof, and application software (including an embedded operating system and a driver) can run on the embedded system hardware without any modification. A development environment is built based on Eclipse, a general graphical modeling framework is provided, the modeling framework comprises a processor, a timer, an interrupt controller, a memory, an internal bus, an external bus, an interface and the like, parameters can be configured for each type of model, a user can conveniently adjust the behavior and the running performance of the model, a plurality of measured controllers can be simulated, and the virtual controller comprises the following structures in software: item resource lists, model attribute configurations, virtual controller models, model libraries, control views, and the like. As shown in fig. 2, a configuration file may be generated by the model editor, so that the formal device information is obtained by the interpreter, and at the same time, the device management is performed on each virtual machine by using the formal device information and the control view, thereby implementing graphical modeling. The architecture of the virtual controller in software comprises: item resource lists, model attribute configurations, virtual controller models, model libraries, control views, and the like. Illustratively, in performing attribute port setting, as shown in table 1, attribute port setting is performed for the main chip TC 234.
Table 1 main chip TC234 attribute port settings
Step S300: building a test environment model based on UDP, wherein the test environment is used for meeting the functional requirements of the virtual controller and carrying out target software test;
step S400: acquiring a test data set of the target software, wherein the test data set comprises a function requirement document, a hard wire pin definition and a communication data protocol;
further, step S300 includes:
step S310: obtaining a standard CAN protocol;
step S320: extracting data of the standard CAN protocol by using CAN Pack and Unpack to obtain CAN ID and CAN data;
step S330: performing byte decomposition on the CAN ID, and recombining decomposed byte data and the CAN data to determine new data;
step S340: and connecting the new data to a UDP sending module, and carrying out ID analysis on the received data based on a UDP Receive module so as to analyze and obtain a message signal.
Specifically, after the virtual controller simulation is completed, a test environment needs to be set up to meet the functional requirements of the controller to implement the software test. How to test the driver without hardware is the key to complete the development of the platform test environment model. In order to ensure that the test case CAN be compatible with the HIL platform, the test environment model is inherited to the HIL, but because no hardware equipment exists in the chip simulation platform, the hard line interface and the CAN interface CAN not interact through hardware connection. This is achieved using the User Datagram Protocol (UDP). UDP is a connectionless transport layer protocol that provides transaction-oriented simple unreliable messaging service, uses port numbers to reserve their respective data transmission channels for different applications, and can transmit 1472 bytes at most each time for UDP packets.
Taking the standard CAN protocol as an example, in order to convert it into UDP communication, it needs to extract its CAN ID and CAN Data, where ID is defined as 4 bytes (considering the case of extension frame), and Data constitutes a new 12-byte Data transmission, when receiving this Data, Data [0:31] is resolved into ID, Data [32:95] is resolved into Data, and the principle is shown in fig. 3. The principle of transmission of the hard wire signal through the UDP is the same as that of the CAN signal, and the hard wire signal does not have the ID, so the UDP formed by the hard wire signal only consists of a data part, and the length, the position and other information of each signal are defined by a user. The test environment model is realized by Matlab/Simulink 2013 b. The UDP transmission model is shown in fig. 4, in which extracting CAN ID and data is implemented using CAN Pack and upnp ack, outputting ID and 8 bytes of data, decomposing the ID into 4 bytes, and composing new data with the extracted 8 bytes of data to be connected to a UDP transmission module, the transmission cycle of UDP being determined by the CAN protocol cycle. And further, analyzing each frame of message signals by using the data received by the UDP Receive module according to the ID.
Step S500: establishing a target test environment model of the target software based on the test data set and the test environment model;
step S600: and executing a test function on the target software by using the virtual controller through the target test environment model, and generating a target test report.
Further, as shown in fig. 5, step S600 includes:
step S610: determining a test target, wherein the test target comprises the target software;
step S620: formulating a test requirement based on the test target, wherein the test requirement comprises establishing an interaction environment model and a to-be-tested software model;
step S630: performing test design based on the test requirement, wherein the test design comprises a test environment, a test case and a test strategy;
step S640: executing the test target through the test design and generating the target test report;
step S650: generating a standard time delay format file from the interactive environment model based on dSPACE VEOS;
step S660: and executing the standard delay format file of the driver by starting the virtual controller, and synchronously loading the standard delay format file.
Specifically, in order to verify the correctness of theoretical analysis and the rationality of a chip simulation platform, an experimental platform with dSPACE software as a core is established by taking a virtual BMS (Battery Management System) as a tested object, and a test flow is shown in fig. 6, specifically, a test target needs to be determined, wherein the test target includes the target software, namely, a virtual Battery Management System; further formulating a test requirement, wherein the test requirement comprises establishing an interaction environment model and a to-be-tested software model, the interaction environment model comprises an input and output interface definition and data protocol conversion, and the to-be-tested software model comprises an executable program and a software system requirement; after the test requirement formulation is finished, a test design is required, wherein the test design comprises a test environment, a test case and a test strategy, the test environment comprises an IO and a vehicle model, and the test strategy comprises an interface test, a global variable test and a combined test; and further executing the test target and generating the target test report, wherein the executing test comprises virtual machine starting, debugging parameters, virtual port starting, test case executing and the like.
Before testing, functional requirement document, hard wire pin definition and communication data protocol are input, a testing environment model is established, and the virtual controller and the environment model run on the same personal computer and communicate through UDP. The chip simulation test is a system level test and mainly tests the accuracy of the integration of application layer software and bottom layer software. In the experimental process, an environment model in Simulink generates a standard time delay format file (. sdf file) through dSPACE VEOS software. The method comprises the steps of starting a virtual controller, executing a driver, loading a standard delay format file in dSPACE control desk software, sending UDP data by the virtual controller after a key is set to be in an open state on an interface of an upper computer, and displaying that the upper computer is electrified normally to show that an environment model and the virtual controller can communicate normally.
Fault injection can test equipment faults of a processor (computing errors, cache errors and the like), a register (fixed, turnover, read-write faults and the like), a memory (read-write, fixed, turnover, positive faults and the like), a general-purpose peripheral and the like; LRU board level faults (interference, short circuit, open circuit, etc.); computer system level failures (reset, dead halt, connector short, open, etc.).
Further, step S640 includes:
step S641: testing the functional module of the target software by using an automatic testing tool so as to generate a testing result of the chip simulation platform;
step S642: obtaining the test result of the inherent functional module of the target software;
step S643: and comparing the test results of the chip simulation platform based on the test results of the inherent functional modules.
Specifically, when the target test report is generated, the target test report needs to be analyzed, specifically, an automatic test tool may be used to perform a function module test on the target software to generate a test result of the chip simulation platform, and at the same time, a test result of an inherent function module of the target software is obtained, where the test result of the inherent function module, that is, a result obtained by testing 8 function modules of the BMS through the HIL, is shown in table 2:
table 2 comparison of test results of 8 functional modules of BMS
The method can be used for normally realizing the test functions of battery signal acquisition and monitoring, battery electric quantity estimation, fast/slow charging, balance control, charging and discharging power and the like, and is safe, accurate and comprehensive. Therefore, the safety is high, the precision is high, the abnormal function of the tested controller hardware can be tested, and the test requirement of the test coverage is improved.
Example two
Based on the same application concept as the chip simulation method based on the automobile software test in the foregoing embodiment, as shown in fig. 7, the present application provides a chip simulation system based on the automobile software test, wherein the system includes:
the framework obtaining module is used for obtaining a graphical modeling framework based on Eclipse;
the virtual controller development module is used for simulating and developing a virtual controller by utilizing the graphical modeling framework and the configuration parameters, wherein the virtual controller is used for performing functional modeling simulation on embedded system hardware;
the virtual controller comprises a test environment model building module, a virtual controller building module and a virtual controller testing module, wherein the test environment model building module is used for building a test environment model based on UDP (user Datagram protocol), and the test environment is used for meeting the functional requirements of the virtual controller and carrying out target software test;
the test data acquisition module is used for acquiring a test data set of the target software, wherein the test data set comprises a function requirement document, a hard wire pin definition and a communication data protocol;
the target environment model establishing module is used for establishing a target test environment model of the target software based on the test data set and the test environment model;
and the software testing module is used for executing a testing function on the target software by utilizing the virtual controller through the target testing environment model and generating a target testing report.
Further, the system further comprises:
the software architecture acquisition unit is used for acquiring a software architecture set based on the graphical modeling framework, wherein the software architecture set comprises a project resource list, model attribute configuration, a virtual controller model, a model library and a control view;
and the parameter configuration unit is used for carrying out self-defined parameter configuration on a plurality of graphical models by utilizing the configuration parameters and the software architecture set so as to simulate the virtual controller.
Further, the system further comprises:
the protocol acquisition unit is used for acquiring a standard CAN protocol;
the data extraction unit is used for extracting data of the standard CAN protocol by using CAN Pack and Unpack to obtain CAN ID and CAN data;
the data recombination unit is used for carrying out byte decomposition on the CAN ID and recombining the decomposed byte data and the CAN data so as to determine new data;
and the data analysis unit is used for connecting the new data to the UDP sending module, and carrying out ID analysis on the received data based on the UDP Receive module so as to analyze and obtain the message signal.
Further, the system further comprises:
a test target determination unit for determining a test target, wherein the test target comprises the target software;
the requirement formulating unit is used for formulating a testing requirement based on the testing target, wherein the testing requirement comprises the establishment of an interaction environment model and a to-be-tested software model;
the test design unit is used for carrying out test design based on the test requirement, wherein the test design comprises a test environment, a test case and a test strategy;
and the test execution unit is used for executing the test target through the test design and generating the target test report.
Further, the system further comprises:
the file generating unit is used for generating the interaction environment model into a standard time delay format file based on dSPACE VEOS;
and the file loading unit is used for executing the driver standard delay format file by starting the virtual controller and synchronously loading the standard delay format file.
Further, the system further comprises:
the module testing unit is used for testing the functional module of the target software by utilizing an automatic testing tool so as to generate a testing result of the chip simulation platform;
the test result acquisition unit is used for acquiring the test result of the inherent functional module of the target software;
and the result comparison unit is used for comparing the test results of the chip simulation platform based on the test results of the inherent functional modules.
The system embodiment of the present application is a system corresponding to the embodiment of the method, and all implementation means in the method embodiment are applicable to the embodiment of the system, and the same technical effect can be achieved.
In a third aspect of the present application, a terminal is provided, which is characterized by comprising a processor, a memory and a computer program stored on the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of the chip simulation method based on the automobile software test as described above.
In a fourth aspect of the present application, a computer-readable storage medium is provided, wherein a computer program is stored on the computer-readable storage medium, and when being executed by a processor, the computer program implements the steps of the chip simulation method based on the automobile software test as described above.
In summary, the chip simulation method and system based on the automobile software test have the following advantages:
1. by constructing a full-digital simulation test framework for the embedded software, the chip simulation test technology platform can carry out complete digital simulation on a hardware environment in which the embedded software operates, and provides functions of automatic test, fault simulation and injection, coverage analysis, single-step debugging and the like. A user can operate the embedded software on the platform without hardware, and the embedded software can be tested and verified without corresponding hardware equipment and a hardware simulation rack. The technical problems that in the prior art, high-precision signal requirements, safety of large voltage and large current, and abnormal related functions of tested controller hardware and chips cannot be tested are solved. The safety and the precision in software testing are high, the abnormal functions of the hardware of the tested controller can be tested, and the test coverage is improved; the method is simple, visual and convenient to operate; the method can be used for debugging by developers, so that the debugging work is advanced, the development period is shortened, the software quality is improved, and the hardware-in-loop rack resource is saved.
2. The building and test case execution tool of the test environment is modified based on the HIL test platform, the model structure is not changed, the test case can be multiplexed with the HIL, the test period is shortened, and the test efficiency is improved.
Further, the present application may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion.
The foregoing is a preferred embodiment of the present application, and it should be noted that, for those skilled in the art, several modifications and refinements can be made without departing from the principle described in the present application, and these modifications and refinements should be regarded as the protection scope of the present application.
Claims (9)
1. A chip simulation method based on automobile software testing is characterized by comprising the following steps:
based on Eclipse, acquiring a graphical modeling framework;
simulating and developing a virtual controller by utilizing the graphical modeling framework and the configuration parameters, wherein the virtual controller is used for performing functional modeling simulation on embedded system hardware;
building a test environment model based on a User Datagram Protocol (UDP), wherein the test environment is used for meeting the functional requirements of the virtual controller to perform target software test;
acquiring a test data set of the target software, wherein the test data set comprises a function requirement document, a hard wire pin definition and a communication data protocol;
establishing a target test environment model of the target software based on the test data set and the test environment model;
and executing a test function on the target software by using the virtual controller through the target test environment model, and generating a target test report.
2. The method of claim 1, wherein the simulating the development of the virtual controller comprises:
acquiring a software architecture set based on the graphical modeling framework, wherein the software architecture set comprises a project resource list, model attribute configuration, a virtual controller model, a model library and a control view;
and carrying out self-defined parameter configuration on various graphical models by utilizing the configuration parameters and the software architecture set so as to simulate the virtual controller.
3. The method of claim 2, wherein building a test environment model comprises:
obtaining a CAN protocol of a standard controller area network;
extracting data of the standard CAN protocol by using CAN Pack and Unpack to obtain CAN ID and CAN data;
performing byte decomposition on the CAN ID, and recombining decomposed byte data and the CAN data to determine new data;
and connecting the new data to a UDP sending module, and carrying out ID analysis on the received data based on a UDP Receive module so as to analyze and obtain a message signal.
4. The method of claim 3, wherein said performing a test function on said target software comprises:
determining a test target, wherein the test target comprises the target software;
formulating a test requirement based on the test target, wherein the test requirement comprises establishing an interaction environment model and a to-be-tested software model;
performing test design based on the test requirement, wherein the test design comprises a test environment, a test case and a test strategy;
executing the test target through the test design, and generating the target test report.
5. The method of claim 4, wherein the method comprises:
generating a standard time delay format file from the interactive environment model based on dSPACE VEOS;
and executing the standard delay format file of the driver by starting the virtual controller, and synchronously loading the standard delay format file.
6. The method of claim 5, wherein the method comprises:
testing the functional module of the target software by using an automatic testing tool so as to generate a testing result of the chip simulation platform;
obtaining the test result of the inherent functional module of the target software;
and comparing the test results of the chip simulation platform based on the test results of the inherent functional modules.
7. A chip simulation system based on automobile software testing is characterized in that the system comprises:
the framework obtaining module is used for obtaining a graphical modeling framework based on Eclipse;
the virtual controller development module is used for simulating and developing a virtual controller by utilizing the graphical modeling framework and the configuration parameters, wherein the virtual controller is used for performing functional modeling simulation on embedded system hardware;
the virtual controller comprises a test environment model building module, a virtual controller building module and a virtual controller testing module, wherein the test environment model building module is used for building a test environment model based on UDP (user Datagram protocol), and the test environment is used for meeting the functional requirements of the virtual controller and carrying out target software test;
the test data acquisition module is used for acquiring a test data set of the target software, wherein the test data set comprises a function requirement document, a hard wire pin definition and a communication data protocol;
the target environment model establishing module is used for establishing a target test environment model of the target software based on the test data set and the test environment model;
and the software testing module is used for executing a testing function on the target software by utilizing the virtual controller through the target testing environment model and generating a target testing report.
8. A terminal, characterized in that it comprises a processor, a memory and a computer program stored on the memory and executable on the processor, the computer program, when executed by the processor, implementing the steps of the chip simulation method based on automotive software testing according to any one of claims 1 to 6.
9. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the chip simulation method based on automotive software testing according to any one of claims 1 to 6.
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| CN117688878B (en) * | 2024-02-01 | 2024-04-26 | 北京开源芯片研究院 | Chip testing method and device, electronic equipment and readable storage medium |
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