CN115981636A - Chip simulation platform based on automobile software test and construction method - Google Patents
Chip simulation platform based on automobile software test and construction method Download PDFInfo
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Abstract
The invention provides a chip simulation platform based on automobile software testing and a construction method, and relates to the technical field of simulation. The chip simulation platform comprises: the device model is used for translating and executing instructions of binary code input data of a target chip, providing a kernel reference clock, responding to an abnormal function and an interrupt function; and the equipment manager is connected with the equipment models and used for analyzing a preset configuration file, loading and initializing the equipment models and configuring the connection relation between the pins and the virtual ports among the equipment models according to the ports and the pins of the target chip. The scheme of the invention provides a simulation platform for automobile software testing, which can shorten the software development period, improve the software quality, save hardware-in-loop rack resources and facilitate the reuse of testers and developers.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a scheduling method, apparatus, and device.
Background
At present, hardware-in-the-Loop (HIL) is widely applied to automobile software testing due to the advantages of shortening development period, reducing cost, being convenient and the like, but the problems of high-precision signal requirement, safety of large voltage and large current, incapability of testing functions related to abnormality of Hardware and chips of a tested controller and the like still cannot be solved by the HIL system, and therefore, the expansion of a new testing mode is very important.
Disclosure of Invention
The invention aims to provide a chip simulation platform based on automobile software testing and a construction method thereof, so as to provide the simulation platform for the automobile software testing, shorten the software development period, improve the software quality, save hardware-in-the-loop rack resources and facilitate the reuse of testers and developers.
In order to achieve the above object, an embodiment of the present invention provides a chip simulation platform based on an automobile software test, including:
the device model is used for translating and executing instructions of binary code input data of a target chip, providing a kernel reference clock, responding to an abnormal function and an interrupt function;
and the equipment manager is connected with the equipment models and used for analyzing a preset configuration file, loading and initializing the equipment models and configuring the connection relation between the pins and the virtual ports among the equipment models according to the ports and the pins of the target chip.
Optionally, the device manager comprises:
the system calling interface is used for analyzing the preset configuration file;
and the model development interface is used for realizing at least one of a timer management function, a function of acquiring the state of the current equipment manager, a log output function, a memory read-write function, a memory creation function and a simulator control function.
Optionally, the device manager is further configured to:
analyzing the preset configuration file according to an equipment manager, and loading a chip dynamic library;
and calling a main process function to transfer the interface pointer and the attribute data of the target chip to the chip dynamic library to complete the initialization of the equipment model.
Optionally, the device model comprises a kernel translation model, the kernel translation model being configured to:
acquiring binary code input data of a target chip;
translating the binary code input data into intermediate data, and translating the intermediate data into target data of a virtual controller;
and determining a target instruction corresponding to the binary code input data according to the target data.
Optionally, the device model comprises a peripheral model for handling at least one of the following operations;
when the preset processor accesses the register space of the virtual chip of the equipment model, informing the virtual chip of the equipment model to carry out access logic processing;
when a timer established by a virtual chip of the equipment model expires, informing the virtual chip of the equipment model of expiration processing;
and the virtual chip of the equipment model is connected with the virtual port through the pin of the equipment model to transmit level signals and data.
In order to achieve the above object, an embodiment of the present invention provides a method for constructing a chip simulation platform, which is used for constructing the chip simulation platform based on an automobile software test, and includes:
obtaining a chip manual of a target chip;
establishing an equipment model according to the chip manual of the target chip; the device model at least comprises a kernel translation model used for instruction translation of binary code input data of a target chip and a peripheral model used for providing a kernel reference clock, responding to an abnormal function and an interrupt function;
setting a device manager connected with the device model; the device manager is used for analyzing a preset configuration file, loading and initializing the device models, and configuring the connection relation between the pins and the virtual ports between the device models according to the ports and the pins of the target chip.
Optionally, the method further comprises:
setting a system calling interface and a model development interface for the equipment manager;
the system calling interface is used for analyzing the preset configuration file; the model development interface is used for realizing at least one of a timer management function, a function of acquiring the state of the current equipment manager, a log output function, a memory read-write function, a memory creation function and a simulator control function.
Optionally, establishing an equipment model according to the chip manual of the target chip, including:
constructing a kernel translation model of the target chip according to the chip manual and a preset binary translation algorithm;
constructing a peripheral model of the target chip according to the register and the functional logic of the chip manual;
and taking the kernel translation model and the peripheral model as the equipment model.
Optionally, an analysis file format for analyzing the preset configuration file is set in the device manager;
the analysis file format at least comprises the attribute, meaning, value format and the analyzed execution instruction of the pre-execution instruction.
The technical scheme of the invention has the following beneficial effects:
in the above technical solution, the chip simulation platform includes: the device model is used for translating and executing instructions of binary code input data of a target chip, providing a kernel reference clock, responding to an abnormal function and an interrupt function; the device manager is connected with the device models and used for analyzing preset configuration files, loading and initializing the device models, and configuring the connection relation between pins and virtual ports among the device models according to the ports and pins of the target chip.
Drawings
FIG. 1 is a structural diagram of a chip simulation platform based on automobile software testing according to an embodiment of the present invention;
FIG. 2 is a schematic application diagram of a chip simulation platform based on automobile software testing according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for constructing a chip simulation platform according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In various embodiments of the present invention, it should be understood that the sequence numbers of the following processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
Additionally, the terms "system" and "network" are often used interchangeably herein.
In the embodiments provided herein, it should be understood that "B corresponding to a" means that B is associated with a from which B can be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may be determined from a and/or other information.
As shown in fig. 1, a chip simulation platform based on an automobile software test according to an embodiment of the present invention includes:
a device model 10 for instruction translation and execution of binary input data of a target chip, and providing a core reference clock, responding to an exception function and an interrupt function;
and the device manager 20 is connected with the device models, and is configured to parse a preset configuration file, load and initialize the device models, and configure connection relationships between pins and virtual ports between the device models according to the ports and the pins of the target chip.
In the embodiment, compared with the chip-level simulation testing technology, the chip-level simulation testing technology has the advantages of low price, safety, reliability, support of boundary and fault injection testing and easiness in finding hidden problems in software, so that the chip-level simulation testing technology is a good choice for the embedded software to construct a full-digital simulation chip simulation platform. The invention can carry out complete digital simulation on the hardware environment of the operation of the embedded software and provides the functions of automatic test, fault simulation and injection, coverage analysis, single step debugging and the like. A user can operate the embedded software on the platform without hardware, and the embedded software can be tested and verified without corresponding hardware equipment and a hardware simulation rack. The research on how to use the simulation test technology to construct the embedded full-digital simulation test environment can bring remarkable effects to the quality, development cost and development period of the embedded three-electric control software developed based on the model.
The device model 10 of the invention is modeled according to the chip manual of the target chip, the processor core completes the instruction translation and execution of the target binary system, provides the core reference clock, and responds to the abnormity and the interruption. The device model is finally presented in the form of a dynamically linked library. The device manager 20 is a "DevMgr library" and can complete parsing of a preset configuration file, the preset configuration file is a file with a suffix name of ". Vte", load and initialize device models, and configure connection relationships between pins and virtual ports between the device models according to ports and pins of a target chip.
It should be noted that the chip simulation platform is further connected with a preset operation environment, and the preset operation environment may be a Windows operation environment, and the like.
Meanwhile, the chip simulation platform has multiple functions, including supporting TC277 and TC387 chip simulation functions and supporting an English-flying related chip, and besides, the platform needs to have an expansion function so as to simulate other chips on the same platform; the platform CAN simulate the simulation of Communication buses such as TC277 and TC387 chips CAN, IO (Input Output), SSC (spread spectrum Communication), LIN (Local Interconnect Network) and the like; the method supports all simulation of devices such as EEPROM (Electrically Erasable Programmable Read-only memory), AD (analog-to-Digital), high-low side chips, AD on chips and the like; the fault injection of registers and memories of all 0, all 1 and data errors is supported; supporting the use of an instruction set simulator, some low-level driven program functions can be skipped or replaced through the libraries during the construction of the chip simulation environment. For example: NVM (Non-volatile Memory) simulation, CAN simulation, ADC (analog-to-Digital Conversion) simulation, etc.; a static analysis tool of the hex/s19 can be provided, a good assembly code document can be generated from the hex/s19 file, and a calling relation tree of a function can be generated; supporting the simulation function of the operating system, such as the scheduling of function tasks and interrupt processing programs; step-by-step simulation is supported, and the real-time performance of simulation is guaranteed or is faster than that of real-time simulation; the method supports the extraction of relevant functions from the hex/s19 file, analyzes the input and output of the function, and executes the function only by taking the relevant input/output as an interface to realize the execution of the function or the module test; a program debugger can be provided and has the functions of stepping, execution tracking, register view and online diagnosis; the platform should provide a friendly graphical user interface and a virtual dashboard including common driver inputs, graphical and curvilinear displays, calibration tables, etc.; the fault injection test between the chip simulation environment and the controlled model is supported and can be controlled by a small part of an interface or a test script; support commonly used automotive protocols and related standards such as: CAN bus, CAN-FD (CAN with Flexible Data rate, variable rate controller area network), flexray, LIN (support multiple channels); XCP (Universal measurement and Calibration Protocol) for Calibration, interpretation and use of A2L (where third party tools such as CANape, INCA can be connected); and flashing or storing the calibration parameters.
Optionally, the device manager 20 includes:
the system calling interface is used for analyzing the preset configuration file;
and the model development interface is used for realizing at least one of a timer management function, a function of acquiring the state of the current equipment manager, a log output function, a memory read-write function, a memory creation function and a simulator control function.
In this embodiment, the preset configuration file may be analyzed and the functions of the device model 10 may be developed according to a system call interface and a model development interface. The system call interface analyzes that the preset configuration file is in accordance with the preset configuration file format.
The format of the preset configuration file is shown in table 1 below.
Table 1 preset configuration file format:
further, the system call interface and the model development interface described above may be as shown in table 2 below.
TABLE 2 System Call interface and model development interface
Optionally, the device manager is further configured to:
analyzing the preset configuration file according to an equipment manager, and loading a chip dynamic library;
and calling a main process function to transfer the interface pointer and the attribute data of the target chip to the chip dynamic library to complete the initialization of the equipment model.
In this embodiment, the device manager is started, and analyzes the preset configuration file of the virtual board card through the device manager, loads the chip dynamic library, calls a main process function, that is, a preset MainProc function, transfers the interface pointer and attribute data of the target chip to the chip dynamic library, completes initialization of the device model, and notifies the target chip of completing initialization work
Optionally, the device model comprises a kernel translation model, the kernel translation model being configured to:
acquiring binary code input data of a target chip;
translating the binary code input data into intermediate data, and translating the intermediate data into target data of a virtual controller;
and determining a target instruction corresponding to the binary code input data according to the target data.
In the embodiment, a dynamic binary translation technology is adopted for instruction translation, in terms of a macro structure of binary translation, a dynamic binary translation system is divided into a front end and a rear end, binary code input data of a target chip is used, the binary code input data is translated into intermediate code belonging to the front end, the intermediate code is translated into local machine binary code belonging to the rear end, the rear end translation can be multiplexed, target data of a virtual controller can be determined according to the local machine binary code, and a target instruction corresponding to the binary code input data can be determined through the target data.
In a specific implementation manner, as shown in fig. 2, an embedded programming language (binary input data of a target chip) is compiled and linked to determine an assembly language of target hardware (a target chip), a machine language of the target hardware is determined by the assembly language loading of the target hardware (the target chip), the embedded programming language (binary input data of the target chip) is translated into an intermediate language according to the machine language of the target hardware, the intermediate language is translated into a PC machine language (machine language used by a platform), and instruction information corresponding to the embedded programming language (binary input data of the target chip), that is, a PC machine instruction, can be determined by the PC machine language (machine language used by the platform).
Optionally, the device model comprises a peripheral model for handling at least one of the following operations;
when a preset processor accesses the register space of the virtual chip of the equipment model, informing the virtual chip of the equipment model to carry out access logic processing;
when a timer established by a virtual chip of the equipment model expires, informing the virtual chip of the equipment model of expiration processing;
and the virtual chip of the equipment model is connected with the virtual port through the pin of the equipment model to transmit level signals and data.
In the embodiment, chip port and pin definitions are obtained, a pin and virtual port connection relationship is established, and when a preset processor (a preset central processing unit CPU) reads an OPORT port on a virtual chip, a main process function MainProc is called to notify the chip to perform read access logic operation; when a CPU writes in an IOPORT port (IO port configuration) on a virtual chip, a MainProc notification chip is called to perform write access logic conversion, a level signal is transmitted to an IOPIN pin, and the chip at the other connected end transmits a data stream to a VIOPORT virtual port; when the timing clock created by the virtual chip expires, the system calls a main process function MainProc to inform the chip of timing clock expiration processing, and when the system exits, the main process function MainProc is called to inform the chip of exiting processing.
As described above, the chip simulation platform for testing the automobile software provided by the invention can be used for providing simulation test for testing the automobile software, can shorten the software development period, improve the software quality, save hardware in-loop rack resources and facilitate the reuse of testers and developers.
As shown in fig. 3, the present invention further provides a method for constructing a chip simulation platform, which is used for constructing the chip simulation platform based on the automobile software test, and includes:
301, obtaining a chip manual of a target chip;
step 302, establishing an equipment model according to the chip manual of the target chip; the device model at least comprises a kernel translation model used for instruction translation of binary code input data of a target chip and a peripheral model used for providing a kernel reference clock, responding to an abnormal function and an interrupt function;
The invention can determine the specification of the target chip through the chip manual of the target chip, and can be obtained through various modes such as preset database downloading, preset link downloading, manufacturer providing and the like, and the key parameters of the target chip can be determined through the chip manual, wherein the key parameters are parameters which are easy to damage devices or parameters which influence the performance of the devices, such as key parameters of resistors: package (power): the packaging is selected to be too small, and the power is burnt after exceeding; precision: the accuracy is low, and the accuracy is inaccurate (for example, the voltage is inaccurate when the sampling is performed); pressure resistance value: the voltage cannot be used in an over-rated mode, otherwise, the LED lamp can be burnt out; for another example, the capacitance: types (X5R, X7R, etc.), which are associated with the temperature of the capacitor, are different in temperature, and have a large characteristic variation; the filtering performance parameters are as follows: influence filtering performance, heat generation, etc.; frequency characteristic curve: different frequencies have different impedances; DC bias voltage: under different voltages, the capacitance capacity is different; pressure resistance value: over time, the capacitor breakdown burns, and so on. Establishing an equipment model through a chip manual; the device model at least comprises a kernel translation model used for instruction translation of binary code input data of a target chip and a peripheral model used for providing a kernel reference clock, responding to an abnormal function and an interrupt function; and then setting an equipment manager connected with the equipment model to complete the construction of the chip simulation platform.
The scheme of the invention can establish a chip simulation platform based on automobile software testing, and can carry out simulation testing on a target chip through the chip simulation platform, namely, a full-digital simulation testing frame is established for embedded software, and the chip simulation testing technology platform can carry out complete digital simulation on a hardware environment in which the embedded software runs, and provides functions of automatic testing, fault simulation and injection, coverage analysis, single-step debugging and the like. A user can operate the embedded software on the platform without hardware, and the embedded software can be tested and verified without corresponding hardware equipment and a hardware simulation rack. The technical problems that in the prior art, high-precision signal requirements, safety of large voltage and large current, and abnormal related functions of tested controller hardware and chips cannot be tested are solved.
Further, optionally, the step 302 includes:
constructing a kernel translation model of the target chip according to the chip manual and a preset binary translation algorithm;
constructing a peripheral model of the target chip according to the register and the functional logic of the chip manual;
and taking the kernel translation model and the peripheral model as the equipment model.
In this embodiment, the device model is modeled according to an official chip manual, and the processor core completes instruction translation and execution of the target binary system, provides a core reference clock, and responds to exceptions and interrupts. The kernel translation model is established through a chip manual and a preset binary translation algorithm. The peripheral model is modeled according to registers and functional logics in a chip user manual, and the main work of the peripheral model is to respond to the access of a processor to the registers by completing the mapping of a register area on the processor and triggering the corresponding functional logics. The device model is ultimately presented in the form of a dynamically linked library.
Specifically, the peripheral model analyzes the configuration file through the device manager when the system is started, and initialization of the chip model and establishment of the pin port connection relation are completed. When the processor accesses the chip register space, the chip is informed to perform access logic processing; when the timer established by the virtual chip expires, informing the chip of expiration processing; the virtual chip is connected with the virtual port through the pin to transmit level signals and data.
The equipment model of the invention can be used for debugging by developers, thus leading the debugging work to move forward, shortening the development period, improving the software quality and saving the hardware-in-the-loop rack resources.
Optionally, the method further includes:
setting a system calling interface and a model development interface for the equipment manager;
the system calling interface is used for analyzing the preset configuration file; the model development interface comprises a model message inlet and a virtual peripheral port and is used for realizing at least one of a timer management function, a function of acquiring the state of the current equipment manager, a log output function, a memory read-write function, a memory creation function and a simulator control function.
Here, the function of decoding the preset configuration file and developing the device model can be achieved by setting an external system call interface and a model development interface on the device manager.
Further, the system call interface analyzes that the preset configuration file is in accordance with the preset configuration file format. Optionally, an analysis file format for analyzing the preset configuration file is set in the device manager;
the analysis file format at least comprises the attribute, meaning, value format and the analyzed execution instruction of the pre-execution instruction.
Specifically, the parsing file format may be as shown in table 1 or table 2 above. Specifically, in order to verify the correctness of theoretical analysis and the rationality of a chip simulation platform, an experimental platform with target software as a core is established by taking a virtual BMS (Battery Management System) as a measured object.
Specifically, a test target needs to be determined, where the test target includes the target software, i.e., a virtual battery management system; further formulating a test requirement, wherein the test requirement comprises establishing an interactive environment model and a to-be-tested software model, the interactive environment model comprises an input and output interface definition and data protocol conversion, and the to-be-tested software model comprises an executable program and a software system requirement; after the test requirement formulation is finished, a test design is required, wherein the test design comprises a test environment, a test case and a test strategy, the test environment comprises an input/output (IO) and a vehicle model, and the test strategy comprises an interface test, a global variable test and a combined test; and further executing the test target and generating the target test report, wherein the executing test comprises virtual machine starting, debugging parameters, virtual port starting, test case executing and the like.
In summary, the invention provides a simulation platform for automobile software testing and a construction method thereof, which can provide testing through the chip simulation platform, shorten the software development period, improve the software quality, save hardware-in-the-loop rack resources, and facilitate the reuse of testers and developers.
The exemplary embodiments described above are described with reference to the drawings, and many different forms and embodiments of the invention may be made without departing from the spirit and teaching of the invention, therefore, the invention is not to be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of elements may be exaggerated for clarity. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise indicated, a range of values, when stated, includes the upper and lower limits of the range and any subranges therebetween.
While the foregoing is directed to the preferred embodiment of the present invention, it will be appreciated by those skilled in the art that various changes and modifications may be made therein without departing from the principles of the invention as set forth in the appended claims.
Claims (9)
1. A chip simulation platform based on automobile software testing is characterized by comprising:
the device model is used for translating and executing instructions of binary code input data of a target chip, providing a kernel reference clock, responding to an abnormal function and an interrupt function;
and the equipment manager is connected with the equipment models and used for analyzing a preset configuration file, loading and initializing the equipment models and configuring the connection relation between the pins and the virtual ports among the equipment models according to the ports and the pins of the target chip.
2. The chip emulation platform of claim 1, wherein the device manager comprises:
the system calling interface is used for analyzing the preset configuration file;
and the model development interface is used for realizing at least one of a timer management function, a function of acquiring the state of the current equipment manager, a log output function, a memory reading and writing function, a memory creating function and a simulator control function.
3. The chip emulation platform of claim 1, wherein the device manager is further configured to:
analyzing the preset configuration file according to an equipment manager, and loading a chip dynamic library;
and calling a main process function to transfer the interface pointer and the attribute data of the target chip to the chip dynamic library to complete the initialization of the equipment model.
4. The chip emulation platform of claim 1, wherein the device model comprises a kernel translation model to:
acquiring binary code input data of a target chip;
translating the binary code input data into intermediate data, and translating the intermediate data into target data of a virtual controller;
and determining a target instruction corresponding to the binary code input data according to the target data.
5. The chip emulation platform of claim 1, in which the device model comprises a peripheral model, the peripheral model being configured to handle at least one of;
when the preset processor accesses the register space of the virtual chip of the equipment model, informing the virtual chip of the equipment model to carry out access logic processing;
when a timer established by a virtual chip of the equipment model expires, informing the virtual chip of the equipment model of expiration processing;
and the virtual chip of the equipment model is connected with the virtual port through the pin of the equipment model to transmit level signals and data.
6. A method for constructing a chip simulation platform based on automobile software testing according to any one of claims 1 to 5, comprising:
obtaining a chip manual of a target chip;
establishing an equipment model according to the chip manual of the target chip; the device model at least comprises a kernel translation model used for instruction translation of binary code input data of a target chip and a peripheral model used for providing a kernel reference clock, responding to an abnormal function and an interrupt function;
setting a device manager connected with the device model; the device manager is used for analyzing a preset configuration file, loading and initializing the device model, and configuring the connection relation between the pins and the virtual ports between the device models according to the ports and the pins of the target chip.
7. The method of claim 6, further comprising:
setting a system calling interface and a model development interface for the equipment manager;
the system calling interface is used for analyzing the preset configuration file; the model development interface is used for realizing at least one of a timer management function, a function of acquiring the state of the current equipment manager, a log output function, a memory read-write function, a memory creation function and a simulator control function.
8. The method of claim 6, wherein building a device model from a chip manual of the target chip comprises:
constructing a kernel translation model of the target chip according to the chip manual and a preset binary translation algorithm;
constructing a peripheral model of the target chip according to the register and the functional logic of the chip manual;
and taking the kernel translation model and the peripheral model as the equipment model.
9. The method according to claim 6, wherein a parsing file format for parsing the preset configuration file is set in the device manager;
the analysis file format at least comprises the attribute, meaning, value format and the analyzed execution instruction of the pre-execution instruction.
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