CN117675159A - Cascading synchronization method and cascading system for millimeter wave radar receiving and transmitting front-end chip - Google Patents

Cascading synchronization method and cascading system for millimeter wave radar receiving and transmitting front-end chip Download PDF

Info

Publication number
CN117675159A
CN117675159A CN202311395973.5A CN202311395973A CN117675159A CN 117675159 A CN117675159 A CN 117675159A CN 202311395973 A CN202311395973 A CN 202311395973A CN 117675159 A CN117675159 A CN 117675159A
Authority
CN
China
Prior art keywords
chip
reference clock
signal
clock signal
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311395973.5A
Other languages
Chinese (zh)
Inventor
龙勇军
邹毅
王彦杰
张义军
夏鑫淋
王志鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Huajie Zhitong Technology Co ltd
Original Assignee
Shenzhen Huajie Zhitong Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Huajie Zhitong Technology Co ltd filed Critical Shenzhen Huajie Zhitong Technology Co ltd
Priority to CN202311395973.5A priority Critical patent/CN117675159A/en
Publication of CN117675159A publication Critical patent/CN117675159A/en
Pending legal-status Critical Current

Links

Abstract

The disclosure provides a cascading synchronization method and a cascading system for millimeter wave radar receiving and transmitting front end chips, relates to the technical field of radars, and can be applied to a multi-radar cascading scene. The specific implementation scheme comprises the following steps: the first chip receives an external reference clock signal; the first chip generates a first reference clock signal according to an external reference clock signal; the first off-chip equal-length power dividing module equally divides the first reference clock signal into at least two paths of second reference clock signals, outputs one path of the at least two paths of second reference clock signals to the first chip, and outputs the other paths of second reference clock signals to the second chip in a one-to-one correspondence manner, wherein the difference of the time lengths of any two paths of second reference clock signals in the at least two paths of second reference clock signals reaching the corresponding chips is smaller than a first preset threshold value; the first chip and the second chip respectively use the received second reference clock signals as the internal reference clock signals. The method and the device can improve the consistency of cascading of the multi-millimeter wave receiving and transmitting front-end chips.

Description

Cascading synchronization method and cascading system for millimeter wave radar receiving and transmitting front-end chip
Technical Field
The disclosure relates to the technical field of radars, and in particular relates to a cascade synchronization method and a cascade system of millimeter wave radar receiving and transmitting front-end chips, which can be applied to a multi-radar cascade scene.
Background
The 4-Dimensional (4D) millimeter wave radar refers to a millimeter wave radar that can acquire four Dimensional information of a distance, a relative radial velocity, an azimuth angle, and a pitch angle of a target. The millimeter wave receiving and transmitting front-end Chip is one of core components of the 4-dimensional millimeter wave radar, and integrates a multi-channel receiving module, a multi-channel transmitting module, a frequency modulation continuous wave local vibration source, an analog-to-digital converter, a digital interface and other core functional modules into a single System on Chip (SoC) Chip.
Because of the requirements of high-resolution direction finding and high-density point cloud data of the 4D millimeter wave imaging radar, the 4D millimeter wave radar needs to integrate large-scale receiving and transmitting channels, such as 16 receiving/16 transmitting, 32 receiving/32 transmitting, 64 receiving/64 transmitting and the like. However, due to the influence of factors such as heat dissipation, power consumption, cost and yield of the chip, the current chip technology level is difficult to support the number of transceiver channels required by the single transceiver front-end chip for integrating the 4D millimeter wave radar, so that the plurality of millimeter wave transceiver front-end chips are required to be cascaded, and the number of the transceiver channels of the radar is expanded.
However, in the existing scheme of cascading a plurality of millimeter wave transceiver front-end chips, consistency of each millimeter wave transceiver front-end chip after cascading is poor.
Disclosure of Invention
The invention provides a cascading synchronization method and a cascading system for millimeter wave radar receiving and transmitting front-end chips, which can improve cascading consistency of multiple millimeter wave receiving and transmitting front-end chips.
According to a first aspect of the present disclosure, there is provided a cascade synchronization method for a millimeter wave radar transceiver front-end chip, including:
the first chip receives an external reference clock signal and is in a main chip working mode; the first chip generates a first reference clock signal according to an external reference clock signal; the first off-chip equal-length power dividing module equally divides a first reference clock signal into at least two paths of second reference clock signals, outputs one path of the at least two paths of second reference clock signals to the first chip, outputs the other paths of second reference clock signals to the second chip in a one-to-one correspondence manner, and the second chip is in a slave chip working mode, wherein the time difference between the time of reaching the corresponding chip of any two paths of second reference clock signals in the at least two paths of second reference clock signals is smaller than a first preset threshold value; the first chip uses the received second reference clock signal as an internal reference clock signal of the first chip; the second chip uses the received second reference clock signal as an internal reference clock signal of the second chip.
Further, before the first chip receives the external reference clock signal, the method further comprises:
the first chip receives a first instruction, wherein the first instruction is used for indicating the first chip to enter a main chip working mode; the second chip receives a second instruction, and the second instruction is used for indicating the second chip to enter the working mode of the slave chip.
Further, the first chip and the second chip both comprise a reference clock output control module and a master clock phase-locked loop reference clock control module; the chip entering the working mode of the main chip is used for generating a first reference clock signal according to an external reference clock signal through the reference clock output control module, and taking a received second reference clock signal as an internal reference clock signal through the reference clock phase-locked loop reference clock control module; the chip entering the working mode of the slave chip is used for taking the received second reference clock signal as an internal reference clock signal through the reference clock control module of the master clock phase-locked loop.
Further, the method further comprises:
the first chip generates a sequential logic control digital clock signal of the first chip according to an internal reference clock signal of the first chip; the second chip generates a sequential logic control digital clock signal of the second chip according to the internal reference clock signal of the second chip; the first chip receives a waveform modulation trigger signal; the first chip controls the digital clock signal according to the sequential logic of the first chip, samples the waveform modulation trigger signal and generates a first waveform trigger synchronous signal; the second off-chip equal-length power dividing module generates at least two paths of second waveform trigger synchronous signals according to the first waveform trigger synchronous signals, outputs one path of the at least two paths of second waveform trigger synchronous signals to the first chip, outputs the other paths of second waveform trigger synchronous signals to the second chip in a one-to-one correspondence manner, and the time length of the at least two paths of second waveform trigger synchronous signals reaching the corresponding chips is the same; the first chip controls the digital clock signal according to the sequential logic of the first chip, samples the received second waveform triggering synchronous signal, and generates an internal waveform modulation and processing indication signal of the first chip; the second chip controls the digital clock signal according to the time sequence logic of the second chip, samples the received second waveform triggering synchronous signal, and generates an internal waveform modulation and processing indication signal of the second chip.
Further, the first chip and the second chip both comprise a master clock phase-locked loop module, a first integer frequency divider, a second integer frequency divider, a clock synchronization calibration control module and a first controllable time delay module; the first chip is used for generating a high-frequency reference clock signal according to the obtained internal reference clock signal through the master clock phase-locked loop module, and generating a frequency modulation local vibration source reference clock signal according to the high-frequency reference clock signal through the first integer frequency divider; the first integer frequency divider is used for generating an initial sequential logic control digital clock signal according to the generated high-frequency reference clock signal; the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated initial sequential logic control digital clock signal through the first controllable time delay module according to the obtained internal reference clock signal and the output signal of the first controllable time delay module to obtain a sequential logic control digital clock signal; the second chip is used for generating a high-frequency reference clock signal according to the obtained internal reference clock signal through the master clock phase-locked loop module, and generating an initial sequential logic control digital clock signal according to the generated high-frequency reference clock signal through the second integer frequency divider; and the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated initial sequential logic control digital clock signal through the first controllable time delay module according to the obtained internal reference clock signal and the output signal of the first controllable time delay module to obtain the sequential logic control digital clock signal.
Further, the first chip and the second chip each further comprise a third integer divider and a second controllable time delay module; the first chip and the second chip are also used for generating an initial analog-to-digital converter sampling clock signal according to the high-frequency reference clock signal generated by the master clock phase-locked loop module through the third integer frequency divider; and the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated sampling clock signal of the initial analog-to-digital converter through the second controllable time delay module according to the obtained internal reference clock signal and the output signal of the second controllable time delay module so as to obtain the sampling clock signal of the analog-to-digital converter.
Further, the first chip and the second chip each further comprise a fourth integer divider and a third controllable time delay module; the first chip and the second chip are also used for generating an initial data interface clock signal according to a high-frequency reference clock signal generated by the master clock phase-locked loop module through a fourth integer frequency divider; and the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated initial data interface clock signal through the third controllable time delay module according to the obtained internal reference clock signal and the output signal of the third controllable time delay module to obtain the data interface clock signal.
Further, the method further comprises:
the first chip generates a frequency modulation local vibration source reference clock signal according to an internal reference clock signal of the first chip; generating a first frequency modulation continuous wave local oscillation signal according to the frequency modulation local oscillation source reference clock signal; the third off-chip equal-length power dividing module generates at least two paths of second frequency-modulated continuous wave local oscillation signals according to the first frequency-modulated continuous wave local oscillation signals, outputs one path of the at least two paths of second frequency-modulated continuous wave local oscillation signals to the first chip, outputs the other paths of second frequency-modulated continuous wave local oscillation signals to the second chip in a one-to-one correspondence manner, and the time length of the at least two paths of second frequency-modulated continuous wave local oscillation signals reaching the corresponding chips is the same; the first chip generates a radio frequency signal of the first chip from the received second frequency modulation continuous wave local oscillation signal; and the second chip generates a radio frequency signal of the second chip from the received second frequency modulation continuous wave local oscillation signal.
Further, the first chip and the second chip also comprise a frequency modulation local oscillation source module, a frequency modulation local oscillation signal output control module, a local oscillation signal selection control module, a frequency multiplier and a power divider; the first chip is used for generating a frequency-modulated local oscillation signal according to a frequency-modulated local oscillation source reference clock signal through the frequency-modulated local oscillation source module, and generating a first frequency-modulated continuous wave local oscillation signal through the frequency-modulated local oscillation signal output control module according to the frequency-modulated local oscillation signal obtained by the frequency-modulated local oscillation source module; the local oscillator signal selection control module is also used for taking the received second frequency modulation continuous wave local oscillator signal as an input signal of the frequency multiplier, generating a radio frequency signal according to the received second frequency modulation continuous wave local oscillator signal through the frequency multiplier, and performing power division on the radio frequency signal through the power divider and outputting the radio frequency signal to the receiving and transmitting channel; the second chip is used for using the received second frequency-modulated continuous wave local oscillation signal as an input signal of the frequency multiplier through the local oscillation signal selection control module, generating a radio frequency signal according to the received second frequency-modulated continuous wave local oscillation signal through the frequency multiplier, and performing power division on the radio frequency signal through the power divider and outputting the radio frequency signal to the receiving and transmitting channel.
According to a second aspect of the present disclosure, there is provided a millimeter wave radar transceiver front-end chip cascade system, the system comprising:
at least two chips and a first off-chip equal-length power dividing module; the first outer equal-length power dividing module is respectively connected with each chip, and at least two chips comprise a first chip in a main chip working mode and a second chip in a main chip working mode; the difference between the distances between the first off-chip equal-length power dividing module and the connecting wires of any two chips is smaller than a second preset threshold value; the system is for implementing the method as in the first aspect. The first chip is used for generating a first reference clock signal according to an external reference clock signal, and the first off-chip equal-length power dividing module is used for generating at least two paths of second reference clock signals according to the first reference clock signal and outputting the at least two paths of second reference clock signals to the at least two chips in a one-to-one correspondence mode.
Further, the first outer equal-length power dividing module is connected with equal-length wires of each chip respectively.
Further, at least two chips comprise a reference clock output control module and a master clock phase-locked loop reference clock control module; the reference clock output control module is connected with the first external equal-length power dividing module, and the first external equal-length power dividing module is connected with the reference clock control module of the master clock phase-locked loop. The reference clock output control module is used for generating a first reference clock signal according to an external reference clock signal; the master clock phase-locked loop reference clock control module is used for receiving a second reference clock signal and taking the second reference clock signal as an internal reference clock signal.
Further, the system also comprises a second off-chip equal-length power dividing module, and the second off-chip equal-length power dividing module is respectively connected with each chip. The first chip is also used for generating a first waveform trigger synchronous signal, the second off-chip equal-length power dividing module is used for generating at least two paths of second waveform trigger synchronous signals according to the first waveform trigger synchronous signal, and outputting the at least two paths of second waveform trigger synchronous signals to the at least two chips in a one-to-one correspondence mode.
Further, the at least two chips comprise a main clock phase-locked loop module, a first integer frequency divider, a second integer frequency divider, a clock synchronization calibration control module and a first controllable time delay module; the master clock phase-locked loop module is respectively connected with the first integer frequency divider and the second integer frequency divider, the second integer frequency divider is connected with the first controllable time delay module, and the clock synchronization calibration control module is connected with the first controllable time delay module.
The main clock phase-locked loop module is used for generating a high-frequency reference clock signal according to the internal reference clock signal; the first integer divider is used for generating a frequency modulation local oscillator source reference clock signal according to the high-frequency reference clock signal; the second integer frequency divider is used for generating an initial sequential logic control digital clock signal according to the high-frequency reference clock signal; the clock synchronization calibration control module is used for controlling the first controllable time delay module to perform time delay adjustment on the initial sequential logic control digital clock signal according to the internal reference clock signal and the output signal of the first controllable time delay module so as to obtain the sequential logic control digital clock signal; the first controllable time delay module is used for performing time delay adjustment on the initial sequential logic control digital clock signal.
Further, the at least two chips each further comprise a third integer divider and a second controllable time delay module; the master clock phase-locked loop module is also connected with a third integer frequency divider, the third integer frequency divider is connected with a second controllable time delay module, and the clock synchronization calibration control module is also connected with the second controllable time delay module.
The third integer frequency divider is used for generating an initial analog-to-digital converter sampling clock signal according to the high-frequency reference clock signal; the clock synchronous calibration control module is also used for controlling the second controllable time delay module to perform time delay adjustment on the initial analog-to-digital converter sampling clock signal according to the internal reference clock signal and the output signal of the second controllable time delay module so as to obtain the analog-to-digital converter sampling clock signal; the second controllable time delay module is used for performing time delay adjustment on the sampling clock signal of the initial analog-to-digital converter.
Further, the at least two chips also comprise a fourth integer frequency divider and a third controllable time delay module; the master clock phase-locked loop module is also connected with a fourth integer frequency divider, the fourth integer frequency divider is connected with a third controllable time delay module, and the clock synchronization calibration control module is also connected with the third controllable time delay module.
The fourth integer frequency divider is used for generating an initial data interface clock signal number according to the high-frequency reference clock signal; the clock synchronous calibration control module is also used for controlling the third controllable time delay module to perform time delay adjustment on the initial data interface clock signal according to the internal reference clock signal and the output signal of the third controllable time delay module so as to obtain the data interface clock signal; the third controllable time delay module is used for performing time delay adjustment on the initial data interface clock signal.
Further, the system also comprises a third outer equal length power dividing module which is respectively connected with each chip. The first chip is also used for generating a first frequency-modulated continuous wave local oscillation signal, the second off-chip equal-length power dividing module is used for generating at least two paths of second frequency-modulated continuous wave local oscillation signals according to the first frequency-modulated continuous wave local oscillation signal, and outputting the at least two paths of second frequency-modulated continuous wave local oscillation signals to the at least two chips in a one-to-one correspondence mode.
Further, the at least two chips also comprise a frequency modulation local oscillation source module, a frequency modulation local oscillation signal output control module, a local oscillation signal selection control module, a frequency multiplier and a power divider;
The frequency modulation local oscillation source module is connected with the frequency modulation local oscillation signal output control module, the frequency modulation local oscillation signal output control module is connected with the third external equal-length power dividing module, the third external equal-length power dividing module is connected with the local oscillation signal selection control module, the local oscillation signal selection control module is connected with the frequency multiplier, and the frequency multiplier is connected with the power divider.
The frequency modulation local oscillation source module is used for generating a frequency modulation local oscillation signal according to a frequency modulation local oscillation source reference clock signal; the frequency modulation local oscillation signal output control module is used for generating a first frequency modulation continuous wave local oscillation signal according to the frequency modulation local oscillation signal; the local oscillation signal selection control module is used for taking the second frequency modulation continuous wave local oscillation signal as an input signal of the frequency multiplier; the frequency multiplier is used for generating a radio frequency signal according to the received second frequency modulation continuous wave local oscillation signal; the power divider is used for performing power processing on the radio frequency signal.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:
Fig. 1 is a schematic diagram of a cascaded system of millimeter wave radar transceiver front-end chips provided in an embodiment of the disclosure;
fig. 2 is a schematic flow chart of a cascade synchronization method of millimeter wave radar transceiver front-end chips provided in an embodiment of the disclosure;
fig. 3 is a schematic diagram of a cascaded system of millimeter wave radar transceiver front-end chips cascaded with four chips;
fig. 4 is a schematic diagram of the components of chips in a cascaded system of millimeter wave radar transceiver front-end chips provided in an embodiment of the disclosure;
fig. 5 is another flow chart of a cascading synchronization method of a millimeter wave radar transceiver front-end chip provided in an embodiment of the disclosure;
fig. 6 is a schematic diagram of another composition of a millimeter wave radar transmit-receive front-end chip cascade system with four chips cascaded;
fig. 7 is another schematic diagram of a chip in a cascaded system of millimeter wave radar transceiver front-end chips according to an embodiment of the disclosure;
fig. 8 is a schematic diagram of another composition of chips in a cascaded system of millimeter wave radar transceiver front-end chips according to an embodiment of the disclosure;
fig. 9 is a schematic diagram of another composition of chips in a cascaded system of millimeter wave radar transceiver front-end chips according to an embodiment of the disclosure;
fig. 10 is a schematic flow chart of another cascade synchronization method of a millimeter wave radar transceiver front-end chip according to an embodiment of the disclosure;
FIG. 11 is a schematic diagram of another configuration of a millimeter wave radar transmit-receive front-end chip cascade system with four chips cascaded;
fig. 12 is a schematic diagram of another composition of chips in a cascaded system of millimeter wave radar transceiver front-end chips according to an embodiment of the disclosure;
FIG. 13 is a timing diagram of a timing logic control digital clock signal synchronization error versus a sampling time of a synchronization trigger signal;
fig. 14 is a schematic diagram of waveform triggering and subsequent processing sequences of a millimeter wave rf front-end chip;
FIG. 15 is a timing diagram illustrating the effect of the second waveform trigger synchronization signal on waveform trigger synchronization when the time error of the second waveform trigger synchronization signal reaching each cascaded chip does not exceed one sampling clock cycle;
FIG. 16 is a timing diagram illustrating the effect of the second waveform trigger synchronization signal on waveform trigger synchronization when the time error of the second waveform trigger synchronization signal reaching each cascaded chip exceeds one sampling clock cycle;
fig. 17 is a timing diagram of internal waveform modulation and processing instruction signals generated inside a chip of a millimeter wave radar transmit-receive front-end chip cascade and synchronization system according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
It should be appreciated that in embodiments of the present disclosure, the character "/" generally indicates that the context associated object is an "or" relationship. The terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.
The 4D millimeter wave radar is a millimeter wave radar capable of acquiring four dimensional information of the distance, the relative radial speed, the azimuth angle and the elevation angle of a target.
Compared with a 3-Dimensional (3D) millimeter wave radar, the 4D millimeter wave radar can obtain information of the 4 th dimension of the target, namely the pitching angle of the target, besides the information of the 3 dimensions such as the distance, the relative radial speed and the azimuth angle of the target, and can solve the problem that the 3D millimeter wave radar cannot process a static target and a transverse moving target. In addition, compared with a 3D millimeter wave radar, the 4D millimeter wave radar has the advantages that the distance resolution and precision, the angle resolution and precision, the speed resolution and precision and the like are greatly improved, particularly, the ultra-high resolution direction finding serving as a core competitiveness index can greatly improve the point cloud data density of the 4D millimeter wave radar, and the 4D millimeter wave radar is gradually becoming an environment situation sensing sensor which is key to intelligent network-connected automobiles and automatic driving technologies.
The millimeter wave receiving and transmitting front-end chip is one of core components of the 4D millimeter wave radar, and integrates a multi-channel receiving module, a multi-channel transmitting module, a frequency modulation continuous wave local vibration source, an analog-digital converter, a digital interface and other core functional modules into a single SoC chip.
Because of the requirements of high-resolution direction finding and high-density point cloud data of the 4D millimeter wave imaging radar, the 4D millimeter wave radar needs to integrate large-scale receiving and transmitting channels, such as 16 receiving/16 transmitting, 32 receiving/32 transmitting, 64 receiving/64 transmitting and the like. However, due to the influence of factors such as heat dissipation, power consumption, cost and yield of the chip, the current chip technology level is difficult to support the number of transceiver channels required by the single transceiver front-end chip to integrate the 4D millimeter wave radar, so that the number of transceiver channels of the multiple millimeter wave transceiver front-end chips needs to be cascaded, and the number of transceiver channels of the real radar is expanded.
However, in the existing scheme of cascading a plurality of millimeter wave transceiver front-end chips, consistency of each millimeter wave transceiver front-end chip after cascading is poor.
The consistency refers to synchronization performance among a plurality of cascaded chips, such as waveform triggering synchronization, digital processing time sequence synchronization and the like.
The technical difficulty of waveform triggering synchronization and digital processing clock synchronization is relatively high, and the currently disclosed synchronization scheme mainly comprises the following two types:
1. Waveform trigger signals among the cascade chips are strictly synchronous, but digital processing clocks are not synchronous, and errors of sampling waveform trigger signals of the digital processing clocks of the master chip and the slave chip are reduced by a method of greatly improving the frequency of the digital processing clocks. The scheme has a synchronous error in principle, and the larger the intermediate frequency bandwidth is, the larger the influence of the synchronous error on the speed measurement and angle measurement performance of the 4D radar system is.
2. The waveform trigger signals among the cascade chips are not synchronous, but the digital processing clocks are synchronous, so that the waveform trigger signals are ensured to be synchronously sampled by the digital processing clocks of the master chip and the slave chip, the time difference of the waveform trigger signals reaching each cascade chip must be ensured not to exceed one digital processing clock, and at the moment, the low-frequency digital processing clock is required to be used, or the design boundary and the application boundary of the 4D radar system are limited.
The two synchronization schemes mainly have the following defects:
1. the waveform triggering synchronization and the digital processing clock synchronization are not realized simultaneously in principle, and in order to ensure the synchronization performance or reduce the influence of the synchronization error on the performance of the 4D radar system, the design boundary and the use boundary of the 4D millimeter wave radar system are required to be limited, such as the bandwidth of an intermediate frequency signal or the wiring length of a PCB;
2. The synchronization error has uncertainty in principle, which affects the use of the 4D millimeter wave radar system;
3. the synchronization error is larger, the synchronization error is required to be compensated by a system level calibration function, and the use complexity of the 4D millimeter wave radar system is increased;
4. the synchronization scheme has a disadvantage in principle, and the defect of the synchronization scheme needs to be overcome by reducing the performance of other aspects of the chip, such as reducing the frequency of a digital processing clock, which affects the response speed and the time control precision of the chip.
Under the background technology, the present disclosure provides a cascade synchronization method for millimeter wave radar receiving and transmitting front end chips, which can improve the consistency of cascade of multiple millimeter wave receiving and transmitting front end chips.
The cascade synchronization method for the millimeter wave radar receiving and transmitting front end chip provided by the embodiment of the disclosure can be applied to a cascade system of the millimeter wave radar receiving and transmitting front end chip. Fig. 1 is a schematic diagram of a cascaded system of millimeter wave radar transceiver front-end chips according to an embodiment of the disclosure. As shown in fig. 1, the system may include:
n chips and the first off-chip equal-length power dividing module;
the first outer equal-length power dividing module is respectively connected with each chip, and at least two chips comprise a first chip in a main chip working mode and a second chip in the main chip working mode.
The first external equal-length power dividing module may include N input ends and N output ends, where the N input ends of the first external equal-length power dividing module are respectively connected with the N chips in a one-to-one correspondence manner, and the N output ends of the first external equal-length power dividing module are respectively connected with the N chips in a one-to-one correspondence manner.
The first chip may be any one of the N chips, and the second chip may be the remaining chips other than the first chip among the N chips. For example, when the chip 1 is a first chip, the chips 2, 3 to N are all second chips.
The following describes an exemplary method for synchronizing the cascade of the millimeter wave radar transmit-receive front-end chips, which can be applied to the millimeter wave radar transmit-receive front-end chip cascade system, by taking the millimeter wave radar transmit-receive front-end chip cascade system as an example with reference to the accompanying drawings.
Fig. 2 is a schematic flow chart of a cascade synchronization method of millimeter wave radar transceiver front-end chips according to an embodiment of the disclosure. As shown in fig. 2, the method may include:
s201, the first chip receives an external reference clock signal.
Wherein the first chip is in a master chip mode of operation.
The operation mode of the chip may be preset, or the chip may enter a corresponding operation mode according to an instruction.
For example, the external reference clock signal may be represented by Ref_CLK.
Illustratively, fig. 3 is a schematic diagram of a cascaded system of millimeter wave radar transmit-receive front-end chips cascaded with four chips. As shown in fig. 3, taking the first chip as the chip a, the chip a receives the external reference clock signal ref_clk.
The external reference clock signal may be from an off-chip crystal oscillator or clock source, for example.
Illustratively, the first chip may perform S202 after receiving the external reference clock signal.
S202, the first chip generates a first reference clock signal according to an external reference clock signal.
The first chip may generate the first reference clock signal from an external reference clock signal by means of an associated functional module internal to the first chip.
The first reference clock signal may be represented by ref_clk_out, for example.
For example, after the first chip generates the first reference clock signal, the first reference clock signal may be output to the first off-chip equal-length power dividing module. As shown In fig. 3, the chip a generates a first reference clock signal ref_clk_in and outputs the first reference clock signal ref_clk_out to the first off-chip equal-length power division module.
S203, the first off-chip equal-length power dividing module equally divides the first reference clock signal into at least two paths of second reference clock signals, outputs one path of the at least two paths of second reference clock signals to the first chip, and outputs the other paths of second reference clock signals to the second chip in a one-to-one correspondence manner.
The second chip is in a slave chip working mode, and the time difference between any two paths of second reference clock signals in at least two paths of second reference clock signals and the corresponding chip is smaller than a first preset threshold value.
The operation mode of the chip may be preset, or the chip may enter a corresponding operation mode according to an instruction.
The second reference clock signal may be represented by ref_clk_in, for example.
As shown In fig. 3, the first off-chip equal-length power dividing module outputs a path of second reference clock signal ref_clk_in to the chip a, the chip B, the chip C and the chip D, respectively.
Illustratively, the moments of the second reference clock signals received by the first chip and the second chip differ by a first preset threshold.
Illustratively, the first preset threshold may be 1 microsecond, 1/10 microsecond, or the like.
S204, the first chip uses the received second reference clock signal as an internal reference clock signal of the first chip.
S205, the second chip uses the received second reference clock signal as an internal reference clock signal of the second chip.
The internal reference clock signal is used for generating various clock signals required by the work of the chip, such as a time sequence logic control digital clock signal, an analog-to-digital converter sampling clock signal, a data interface clock signal and the like, so that the chip can complete the work task.
The embodiment of the disclosure receives an external reference clock signal through a first chip, and generates a first reference clock signal according to the external reference clock signal; the first off-chip equal-length power dividing module equally divides the first reference clock signal into at least two paths of second reference clock signals, outputs one path of the at least two paths of second reference clock signals to the first chip, and outputs the other paths of second reference clock signals to the second chip in a one-to-one correspondence manner, so that the first chip and the second chip can simultaneously receive the second reference clock signals, the first chip and the second chip take the received second reference clock signals as respective internal reference clock signals, the first chip and the second chip can use completely synchronous internal reference clock signals, and the cascade consistency of millimeter wave receiving and transmitting front-end chips is improved.
It should be understood that when there is only one chip, the chip is the first chip, and there is no cascade synchronization problem between the chips. At this time, the first chip may directly use the external reference clock signal as the internal reference clock signal.
In a possible embodiment, before the first chip receives the external reference clock signal, the method may further include:
the first chip receives a first instruction, wherein the first instruction is used for indicating the first chip to enter a main chip working mode; the second chip receives a second instruction, and the second instruction is used for indicating the second chip to enter the working mode of the slave chip.
For example, only the chip that received the first instruction or the second instruction may enter the corresponding operation mode. For example, taking a cascade system including a chip 1, a chip 2, a chip 3 and a chip 4 as an example, the chip 1 receives a first instruction, enters a master chip working mode, the chip 2 and the chip 3 receive a second instruction, enters a slave chip working mode, and the chip 4 does not receive the instruction and can be in an idle state. That is, the cascade system includes only the chip 1, the chip 2, and the chip 3, and does not include the chip 4.
According to the embodiment, the chips enter corresponding working modes according to the received instructions, so that cascade among multiple chips is more flexible, and the flexibility of a cascade system is improved.
Fig. 4 is a schematic diagram of the components of chips in the millimeter wave radar transceiver front-end chip cascade system according to the embodiment of the disclosure. As shown in fig. 4, the first chip and the second chip each include a reference clock output control module and a master clock phase-locked loop reference clock control module.
The chip entering the working mode of the main chip is used for generating a first reference clock signal according to an external reference clock signal through the reference clock output control module, and taking a received second reference clock signal as an internal reference clock signal through the reference clock phase-locked loop reference clock control module.
The chip entering the working mode of the slave chip is used for taking the received second reference clock signal as an internal reference clock signal through the reference clock control module of the master clock phase-locked loop.
For example, the internal reference clock signal may be represented by main_pll_ref_clk.
Illustratively, as shown in FIG. 4, the reference clock output control module generates and outputs a first reference clock signal Ref_CLK_Out based on an external reference clock signal Ref_CLK. The master clock phase-locked loop reference clock control module takes the received second reference clock signal Ref_CLK_in as an internal reference clock signal main_PLL_Ref_CLK and outputs the internal reference clock signal main_PLL_Ref_CLK.
The reference clock output control module and the reference clock control module of the master clock phase-locked loop in the first chip are in working states, the reference clock output control module in the second chip is in a non-working state, and the reference clock control module of the master clock phase-locked loop in the second chip is in a working state.
According to the embodiment, the first chip and the second chip comprise the reference clock output control module and the master clock phase-locked loop reference clock control module, so that the chips can accurately obtain synchronous internal reference clock signals based on synchronous second reference clock signals.
It should be understood that when there is only one chip, the chip is the first chip, and there is no cascade synchronization problem between the chips. At this time, the first chip may directly use the external reference clock signal as the internal reference clock signal through the master clock pll reference clock control module.
Fig. 5 is another flow chart of a cascading synchronization method of millimeter wave radar transceiver front-end chips according to an embodiment of the disclosure. As shown in fig. 5, the method may further include:
s501, the first chip generates a sequential logic control digital clock signal of the first chip according to an internal reference clock signal of the first chip.
S502, the second chip generates a sequential logic control digital clock signal of the second chip according to the internal reference clock signal of the second chip.
Illustratively, the first chip and the second chip may generate the sequential logic control digital clock signal via internal associated functional modules.
Illustratively, the first chip and the second chip may generate the synchronized sequential logic control digital clock signal based on the synchronized internal reference clock signal.
S503, the first chip receives the waveform modulation trigger signal.
For example, when the first chip receives the waveform modulation trigger signal, S504 may be performed.
S504, the first chip controls the digital clock signal according to the sequential logic of the first chip, samples the waveform modulation trigger signal and generates a first waveform trigger synchronous signal.
The first chip may generate the first waveform trigger synchronization signal through an associated functional module within the first chip.
For example, the first waveform trigger synchronization signal may be represented by dig_sync_out and the sequential logic control digital clock signal may be represented by inner_digctrl_clk.
For example, after the first chip generates the first waveform trigger synchronization signal, the first waveform trigger synchronization signal may be output to the second off-chip equal-length power dividing module.
Illustratively, fig. 6 is another schematic diagram of a millimeter wave radar transceiver front-end chip cascade system with four chips cascaded. As shown in fig. 6, taking the first chip as an example of the chip a, the chip a generates a first waveform trigger synchronization signal dig_sync_out according to the received waveform modulation trigger signal chirp_start_trig, and outputs the first waveform trigger synchronization signal dig_sync_out to the second off-chip equal-length power dividing module.
S505, the second off-chip equal-length power dividing module generates at least two paths of second waveform trigger synchronous signals according to the first waveform trigger synchronous signals, and outputs one path of the at least two paths of second waveform trigger synchronous signals to the first chip and the other paths of second waveform trigger synchronous signals to the second chip in a one-to-one correspondence manner.
The time length that at least two paths of second waveform trigger synchronous signals reach the corresponding chips is the same.
For example, the second waveform trigger synchronization signal may be represented by dig_sync_in.
As shown In fig. 6, the second off-chip equal-length power dividing module outputs a path of second waveform trigger synchronizing signal dig_sync_in to the chip a, the chip B, the chip C and the chip D, respectively.
Illustratively, the second waveforms received by the first chip and the second chip trigger the synchronization signal at the same time.
S506, the first chip controls the digital clock signal according to the sequential logic of the first chip, samples the received second waveform triggering synchronous signal, and generates an internal waveform modulation and processing indication signal of the first chip.
S507, the second chip controls the digital clock signal according to the time sequence logic of the second chip, samples the received second waveform trigger synchronous signal, and generates an internal waveform modulation and processing indication signal of the second chip.
The internal waveform modulation and processing indication signal is used for indicating the chip to perform waveform triggering and processing.
The first chip can complete processing flows strictly required in time sequence, such as starting and closing of modulating a Chirp waveform by a frequency modulation local oscillator source module, starting and closing of ADC data acquisition, enabling and closing of transmitting sampling data by a digital interface, enabling and closing of transmitting the sampling data by a transmitting module, and the like, by taking effective time of modulating and processing an indication signal of an internal waveform as a reference, the second chip can complete processing flows strictly required in time sequence, such as starting and closing of acquiring the ADC data, enabling and closing of transmitting the sampling data by the digital interface, enabling and closing of transmitting the sampling data, and the like, by taking the effective time of modulating and processing the indication signal of the internal waveform as a reference, and the slave chip completes processing flows strictly required in time sequence, such as starting and closing of transmitting the sampling data by the digital interface, enabling and closing of transmitting the sampling data by the digital interface, and the like, and the first chip and the second chip can start waveform modulation and subsequent working flows at the same time, and the synchronization of waveform triggering absolute time between the chips of each receiving and transmitting front end is realized.
According to the embodiment, the first chip and the second chip can generate synchronous time sequence logic control digital clock signals according to synchronous internal reference clock signals, the first chip receives waveform modulation trigger signals, samples the waveform modulation trigger signals according to the time sequence logic control digital clock signals of the first chip, and generates first waveform trigger synchronous signals; the second off-chip equal-length power dividing module generates at least two paths of second waveform triggering synchronous signals according to the first waveform triggering synchronous signals, outputs one path of the at least two paths of second waveform triggering synchronous signals to the first chip, and outputs the other paths of second waveform triggering synchronous signals to the second chip in a one-to-one correspondence mode, so that the first chip and the second chip can simultaneously receive the second waveform triggering synchronous signals, the first chip and the second chip control digital clock signals according to synchronous sequential logic, sample the synchronous second waveform triggering synchronous signals, generate synchronous internal waveform modulation and processing indication signals, and further realize strict synchronization of waveform triggering and processing of the first chip and the second chip.
Fig. 7 is another schematic diagram of a chip in a cascaded system of millimeter wave radar transceiver front-end chips according to an embodiment of the disclosure. As shown in fig. 7, the first chip and the second chip each include a master clock phase-locked loop module, a first integer frequency divider, a second integer frequency divider, a clock synchronization calibration control module, and a first controllable time delay module.
The first chip is used for generating a high-frequency reference clock signal according to the obtained internal reference clock signal through the master clock phase-locked loop module, and generating a frequency modulation local vibration source reference clock signal according to the high-frequency reference clock signal through the first integer frequency divider; the first integer frequency divider is used for generating an initial sequential logic control digital clock signal according to the generated high-frequency reference clock signal; and the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated initial sequential logic control digital clock signal through the first controllable time delay module according to the obtained internal reference clock signal and the output signal of the first controllable time delay module to obtain the sequential logic control digital clock signal.
The second chip is used for generating a high-frequency reference clock signal according to the obtained internal reference clock signal through the master clock phase-locked loop module, and generating an initial sequential logic control digital clock signal according to the generated high-frequency reference clock signal through the second integer frequency divider; and the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated initial sequential logic control digital clock signal through the first controllable time delay module according to the obtained internal reference clock signal and the output signal of the first controllable time delay module to obtain the sequential logic control digital clock signal.
For example, the high frequency reference clock signal may be represented by main_clk, the frequency modulated source reference clock signal may be represented by chirp_pll_clk, and the sequential logic control digital clock signal may be represented by inner_digctrl_clk.
Illustratively, as shown in fig. 7, the master clock phase-locked loop module generates a high-frequency reference clock signal main_clk according to an internal reference clock signal main_pll_ref_clk, the first integer divider generates a frequency modulation local oscillator source reference clock signal chirp_pll_clk according to the high-frequency reference clock signal main_clk, the second integer divider generates an initial sequential logic control digital clock signal according to the high-frequency reference clock signal main_clk, and the clock synchronization calibration control module performs time delay adjustment on the generated initial sequential logic control digital clock signal through the first controllable time delay module according to the internal reference clock signal main_pll_ref_clk and the output signal of the first controllable time delay module to obtain a sequential logic control digital clock signal Inner_digctrl_clk.
The first integer frequency divider in the second chip is in a non-working state, and the master clock phase-locked loop module, the second integer frequency divider, the clock synchronization calibration control module and the first controllable time delay module in the second chip are all in working states.
According to the embodiment, the first chip and the second chip both comprise the master clock phase-locked loop module, the first integer frequency divider, the second integer frequency divider, the clock synchronization calibration control module and the first controllable time delay module, so that each chip can accurately obtain synchronous sequential logic control digital clock signals based on synchronous internal reference clock signals, and the influence of process errors and temperature drift is avoided.
Fig. 8 is a schematic diagram of another component of a chip in the millimeter wave radar transceiver front-end chip cascade system according to an embodiment of the disclosure. As shown in fig. 8, the first chip and the second chip each further include a third integer divider and a second controllable time delay module;
the first chip and the second chip are also used for generating an initial analog-to-digital converter sampling clock signal according to the high-frequency reference clock signal generated by the master clock phase-locked loop module through the third integer frequency divider; and the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated sampling clock signal of the initial analog-to-digital converter through the second controllable time delay module according to the obtained internal reference clock signal and the output signal of the second controllable time delay module so as to obtain the sampling clock signal of the analog-to-digital converter.
The analog-to-digital converter sampling clock signal may be represented by adc_clk, for example.
As shown in fig. 8, the Main clock phase-locked loop module generates a high-frequency reference clock signal main_clk according to an internal reference clock signal main_pll_ref_clk, the third integer divider generates an initial analog-to-digital converter sampling clock signal according to the high-frequency reference clock signal main_clk, and the clock synchronization calibration control module performs time delay adjustment on the generated initial sequential logic control digital clock signal through the second controllable time delay module according to the internal reference clock signal main_pll_ref_clk and an output signal of the second controllable time delay module to obtain the analog-to-digital converter sampling clock signal adc_clk.
According to the embodiment, the first chip and the second chip also comprise a third integer frequency divider and a second controllable time delay module, so that the chips can accurately obtain synchronous sampling clock signals of the analog-to-digital converter based on synchronous internal reference clock signals, and the influence of process errors and temperature drift is avoided.
Fig. 9 is a schematic diagram of another component of a chip in the millimeter wave radar transceiver front-end chip cascade system according to an embodiment of the disclosure. As shown in fig. 9, each of the first chip and the second chip further includes a fourth integer divider and a third controllable time delay module.
The first chip and the second chip are also used for generating an initial data interface clock signal according to a high-frequency reference clock signal generated by the master clock phase-locked loop module through a fourth integer frequency divider; and the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated initial data interface clock signal through the third controllable time delay module according to the obtained internal reference clock signal and the output signal of the third controllable time delay module to obtain the data interface clock signal.
The data interface clock signal may be represented by diginter_clk, for example.
As shown in fig. 9, the Main clock phase-locked loop module generates a high-frequency reference clock signal main_clk according to an internal reference clock signal main_pll_ref_clk, the fourth integer divider generates an initial analog-to-digital converter sampling clock signal according to the high-frequency reference clock signal main_clk, and the clock synchronization calibration control module performs time delay adjustment on the generated initial sequential logic control digital clock signal through the third controllable time delay module according to the internal reference clock signal main_pll_ref_clk and the output signal of the third controllable time delay module to obtain a data interface clock signal diginter_clk.
According to the embodiment, the first chip and the second chip also comprise a fourth integer frequency divider and a third controllable time delay module, so that the chips can accurately obtain synchronous data interface clock signals based on synchronous internal reference clock signals, and the influence of process errors and temperature drift is avoided.
Fig. 10 is a schematic flow chart of another cascade synchronization method of millimeter wave radar transceiver front-end chips according to an embodiment of the disclosure. As shown in fig. 10, the method further includes:
s1001, a first chip generates a frequency modulation local vibration source reference clock signal according to an internal reference clock signal of the first chip; and generating a first frequency modulation continuous wave local oscillation signal according to the frequency modulation local oscillation source reference clock signal.
The first chip may generate the reference clock signal of the fm local oscillator source and the first fm continuous wave local oscillator signal through related functional modules within the first chip.
Illustratively, the first frequency modulated continuous wave local oscillator signal may be represented by lo_sync_out.
For example, after the first chip generates the first fm continuous wave local oscillator signal, the first fm continuous wave local oscillator signal may be output to the third off-chip equal-length power splitting module.
Illustratively, fig. 11 is a schematic diagram of still another composition of a millimeter wave radar transceiver front-end chip cascade system in which four chips are cascaded. As shown in fig. 11, taking the first chip as the chip a, the chip a generates the first fm continuous wave local oscillator signal lo_sync_out and outputs the first fm continuous wave local oscillator signal lo_sync_out to the third off-chip equal-length power dividing module.
S1002, a third off-chip equal-length power dividing module generates at least two paths of second frequency modulation continuous wave local oscillation signals according to the first frequency modulation continuous wave local oscillation signals, outputs one path of the at least two paths of second frequency modulation continuous wave local oscillation signals to the first chip, and outputs the other paths of the at least two paths of second frequency modulation continuous wave local oscillation signals to the second chip in a one-to-one correspondence mode.
And the time length for the at least two paths of second frequency modulation continuous wave local oscillation signals to reach the corresponding chips is the same.
The second frequency modulated continuous wave local oscillator signal may be represented by lo_sync_in, for example.
As shown In fig. 11, the third off-chip equal-length power dividing module outputs a path of second frequency modulation continuous wave local oscillation signal lo_sync_in to the chip a, the chip B, the chip C and the chip D, respectively.
Illustratively, the first chip and the second chip receive the second frequency modulated continuous wave local oscillation signals at the same time.
S1003, the first chip generates a radio frequency signal of the first chip by using the received second frequency modulation continuous wave local oscillation signal.
S1004, the second chip generates a radio frequency signal of the second chip by using the received second frequency modulation continuous wave local oscillation signal.
Illustratively, each chip may generate the radio frequency signal through an associated functional module within the first chip.
According to the embodiment, the first chip generates a first frequency-modulated continuous wave local oscillation signal according to the frequency-modulated continuous wave oscillation source reference clock signal, the third off-chip equal-length functional dividing module generates at least two paths of second frequency-modulated continuous wave local oscillation signals according to the first frequency-modulated continuous wave local oscillation signal, one path of the at least two paths of second frequency-modulated continuous wave local oscillation signals is output to the first chip, the other paths of the at least two paths of second frequency-modulated continuous wave local oscillation signals are output to the second chip in a one-to-one correspondence manner, the first chip and the second chip can receive the second frequency-modulated continuous wave local oscillation signals at the same time, and the first chip and the second chip can generate synchronous radio frequency signals according to the synchronous second frequency-modulated continuous wave local oscillation signals, so that radio frequency synchronization of the first chip and the second chip can be realized.
Fig. 12 is a schematic diagram of another component of a chip in the millimeter wave radar transceiver front-end chip cascade system according to an embodiment of the disclosure. As shown in fig. 12, the first chip and the second chip each further include a fm local oscillation source module, a fm local oscillation signal output control module, a local oscillation signal selection control module, a frequency multiplier, and a power divider.
The first chip is used for generating a frequency-modulated local oscillation signal according to a frequency-modulated local oscillation source reference clock signal through the frequency-modulated local oscillation source module, and generating a first frequency-modulated continuous wave local oscillation signal through the frequency-modulated local oscillation signal output control module according to the frequency-modulated local oscillation signal obtained by the frequency-modulated local oscillation source module; the frequency multiplier is used for generating a radio frequency signal according to the received second frequency modulation continuous wave local oscillation signal by taking the received second frequency modulation continuous wave local oscillation signal as an input signal of the frequency multiplier through the local oscillation signal selection control module, and performing power division on the radio frequency signal through the power divider and outputting the radio frequency signal to the receiving and transmitting channel.
The second chip is used for using the received second frequency-modulated continuous wave local oscillation signal as an input signal of the frequency multiplier through the local oscillation signal selection control module, generating a radio frequency signal according to the received second frequency-modulated continuous wave local oscillation signal through the frequency multiplier, and performing power division on the radio frequency signal through the power divider and outputting the radio frequency signal to the receiving and transmitting channel.
Illustratively, the frequency modulated local oscillator reference clock signal may be represented by chirp_pll_clk, the frequency modulated local oscillator signal may be represented by fmcw_lo, the first frequency modulated continuous wave local oscillator signal may be represented by lo_sync_out, and the second frequency modulated continuous wave local oscillator signal may be represented by lo_sync_in.
Illustratively, as shown In fig. 12, the fm local oscillation source module generates a fm local oscillation signal fmcw_lo according to a fm local oscillation source reference clock signal chirp_pll_clk, the fm local oscillation signal output control module generates a first fm continuous wave local oscillation signal lo_sync_out according to the fm local oscillation signal fmcw_lo and outputs the first fm continuous wave local oscillation signal lo_sync_out, the local oscillation signal selection control module takes a received second fm continuous wave local oscillation signal lo_sync_in as an input signal of the frequency multiplier, and the frequency multiplier generates a radio frequency signal according to the received second fm continuous wave local oscillation signal lo_sync_in, performs power division on the radio frequency signal through the power divider and outputs the radio frequency signal to the transceiver channel.
The frequency modulation local oscillation source module, the frequency modulation local oscillation signal output control module, the local oscillation signal selection control module, the frequency multiplier and the power divider in the first chip are all in a working state, the frequency modulation local oscillation source module and the frequency modulation local oscillation signal output control module in the second chip are in a non-working state, and the local oscillation signal selection control module, the frequency multiplier and the power divider in the second chip are all in a working state.
According to the embodiment, the first chip and the second chip both comprise the frequency modulation local oscillation source module, the frequency modulation local oscillation signal output control module, the local oscillation signal selection control module, the frequency multiplier and the power divider, so that the chips can accurately obtain synchronous radio frequency signals based on synchronous second frequency modulation continuous wave local oscillation signals.
It should be understood that when there is only one chip, the chip is the first chip, and there is no cascade synchronization problem between the chips. At this time, the first chip may directly use the fm local oscillation signal as the input signal of the frequency multiplier through the local oscillation signal selection control module.
It will be appreciated that in a multi-chip cascade application, the digital processing clock with synchronization requirements in the chip includes an analog-to-digital converter sampling clock adc_clk, a data interface clock diginter_clk, and a timing logic control digital clock inner_digctrl_clk. The adc_clk synchronization is used to ensure that the sampled digital signal has a strictly synchronized amplitude-phase relationship, otherwise, additional sampling errors occur between the sampling channels, which affects the signal processing result. DigInter_CLK synchronization is used for ensuring that all chips synchronously transmit sampled ADC data, and ensuring that the transmitted data are not in error matching.
The inner_digctrl_clk may be used to sample a waveform modulation trigger signal chirp_start_trig or dig_sync_in, and is a reference clock for on-chip timing control and logic control, the synchronization result of which directly affects system performance. The timing logic controls the sampling time error of the digital clock signal inner_digctrl_clk synchronization error versus the synchronization trigger signal as shown in fig. 13.
If no synchronization measures are taken for the inner_digctrl_clk, it cannot be ensured that the inner_digctrl_clk samples to the dig_sync_in signal on the same rising edge, which can lead to a synchronization triggering error of 1 inner_digctrl_clk period at maximum.
The synchronous trigger signal is a time reference standard for the chip to start waveform modulation and subsequent processing flow, if synchronous trigger errors exist in each cascade chip, each cascade chip can not start ADC data acquisition and transmission at the same time, so that phase errors exist in digital sampling signals of each channel of the millimeter wave radar, and the performance of the millimeter wave radar system is affected. If the intermediate frequency bandwidth of the millimeter wave radio frequency front-end chip is not large and the frequency of the inner_digctrl_clk signal is sufficiently high, the effects of the synchronization trigger error may be ignored. Typically, if the bandwidth of the intermediate frequency signal is 10mhz and the clock frequency of the inner_digctrl_clk is 2GHz, the phase error of the sampling signal caused by the synchronous triggering error of one inner_digctrl_clk period is 1.8 ° (10/2000×360 ° =1.8°), and the influence of the synchronous triggering error can be ignored.
On the one hand, for millimeter wave radar application, the intermediate frequency signal bandwidth of the millimeter radio frequency front end chip can be further increased, so that a millimeter wave radar system uses a larger modulation slope, the speed measurement range of the radar is increased, and the refresh rate of the radar is improved. On the other hand, from the aspects of the process, power consumption and design difficulty of the chip, it is necessary to consider reducing the frequency of the inner_digctrl_clk clock signal. Typically, if the bandwidth of the intermediate frequency signal is extended to 50mhz, and the frequency of the inner_digctrl_clk clock signal is reduced to 1GHz, the phase error of the sampling signal caused by the synchronous triggering error of one inner_digctrl_clk period is 18 ° (50/1000×360 ° =18°), and the influence of the synchronous triggering error cannot be ignored; if the frequency of the inner_digctrl_clk clock signal is further reduced to 100MHz, the phase error of the sampling signal caused by the synchronous triggering error of one inner_digctrl_clk period is 180 ° (50/100×360 ° =180°), which makes it difficult for the millimeter wave radar system to operate normally.
For the synchronization problem of inner_digctrl_clk, adc_clk and diginter_clk in multi-chip cascade application, reference can be made to the embodiments shown in fig. 5, 8 and 9.
Exemplary waveform triggering and subsequent processing sequences of the millimeter wave radio frequency front end chip are shown in fig. 14.
It can be understood that, in the multi-chip cascade application, the influence of the time error of the second waveform trigger synchronization signal dig_sync_in signal reaching each stage of cascade chip on waveform trigger synchronization has two cases:
1. under the condition that the sequential logic of each cascade chip controls the digital clock signal Inner_DigCTRL_CLK to be completely synchronous, when the time error of the second waveform trigger synchronizing signal Dig_SYNC_in signal reaching each cascade chip is not more than one sampling clock period (as shown In figure 15), each cascade chip can generate a Chirp_Start signal at the same absolute time, and the strict synchronization of the subsequent digital processing and control among the cascade chips is ensured.
2. When the time error of the dig_sync_in signal reaching each cascade chip exceeds one sampling clock period (as shown In fig. 16), even if the inner_digctrl_clk of each cascade chip is completely synchronized, each cascade chip cannot generate the chirp_start signal at the same absolute time, and subsequent digital processing and control of each cascade chip cannot be strictly synchronized, so that the multi-chip cascade fails.
If the chip design result and the radar system design result satisfy the first condition, namely:
the inner_digctrl_clk is a low frequency sampling clock, ensuring a sufficiently long sampling period for tolerating the arrival error of the dig_sync_in signal;
The length of the routing of the dig_sync_in signal directly from the master chip to all the slave chips is short enough that the transmission delay of the dig_sync_in signal from the master chip to the slave chip does not exceed one inner_digctrl_clk period.
The dig_sync_in signal can be directly connected to the chirp_start_trig pin of the slave chip, and the master chip and the slave chip both use the signal input by the chirp_start_trig pin as trigger pulse to generate the chirp_start signal In each chip, so that the number of the chip pins can be saved.
For millimeter wave radars, especially future millimeter wave imaging radars, the number of channels will increase substantially, the radar size will also increase substantially, and PCB design results will have difficulty ensuring that the transmission delay of the dig_sync_in signal from the master chip to the slave chip does not exceed one inner_digctrl_clk period unless a lower frequency inner_digctrl_clk signal is used. However, decreasing the frequency of the inner_digctrl_clk signal directly increases the processing delay of the chip, decreasing the control accuracy of the waveform time parameter.
In order to improve design constraints of the transceiver front-end chip and the millimeter wave radar, improve performance of the millimeter wave radar system, and solve the problem of waveform triggering synchronization during multi-chip cascade application, reference may be made to an embodiment shown in fig. 5.
For example, fig. 17 is a schematic diagram of a timing sequence of generating an internal waveform modulation and processing instruction signal inside a chip of a millimeter wave radar transmit-receive front-end chip cascade and synchronization system according to an embodiment of the present disclosure, and a timing sequence of generating an internal waveform modulation and processing instruction signal chirp_start inside each cascade chip is shown in fig. 17.
The foregoing description of the embodiments of the present disclosure has been presented primarily in terms of methods. To achieve the above functions, it includes corresponding hardware structures and/or software modules that perform the respective functions. Those of skill in the art will readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is implemented as hardware or computer software driven hardware depends upon the particular application and design constraints imposed on the solution. The technical aim may be to use different methods to implement the described functions for each particular application, but such implementation should not be considered beyond the scope of the present disclosure.
In an exemplary embodiment, the embodiment of the disclosure further provides a millimeter wave radar transceiver front-end chip cascade system, which may be used to implement the millimeter wave radar transceiver front-end chip cascade synchronization method as in the foregoing embodiment.
It can be understood that the structure of the millimeter wave radar transceiver front-end chip cascade system may refer to fig. 1, 3, 4, 6, 7, 8, 9, 11 and 12 in the millimeter wave radar transceiver front-end chip cascade synchronization method in the foregoing embodiments.
The system may include:
at least two chips and a first off-chip equal-length power dividing module; the first outer equal-length power dividing module is respectively connected with each chip, and at least two chips comprise a first chip in a main chip working mode and a second chip in a main chip working mode; the difference between the distances between the first external equal-length power dividing module and the connecting wires of any two chips is smaller than a second preset threshold value.
Illustratively, the second preset threshold may be 10 microns, 20 microns, etc.
In some possible embodiments, the first off-chip equal-length functional module is connected to equal-length wires of each chip respectively.
In some possible embodiments, at least two chips each include a reference clock output control module, a master clock phase-locked loop reference clock control module; the reference clock output control module is connected with the first external equal-length power dividing module, and the first external equal-length power dividing module is connected with the reference clock control module of the master clock phase-locked loop.
In some possible embodiments, the system further comprises a second off-chip equal-length power splitting module, the second off-chip equal-length power splitting module being connected to each of the chips.
In some possible embodiments, at least two chips each include a master clock phase-locked loop module, a first integer divider, a second integer divider, a clock synchronization calibration control module, a first controllable time delay module; the master clock phase-locked loop module is respectively connected with the first integer frequency divider and the second integer frequency divider, the second integer frequency divider is connected with the first controllable time delay module, and the clock synchronization calibration control module is connected with the first controllable time delay module.
In some possible embodiments, at least two chips each further comprise a third integer divider and a second controllable time delay module; the master clock phase-locked loop module is also connected with a third integer frequency divider, the third integer frequency divider is connected with a second controllable time delay module, and the clock synchronization calibration control module is also connected with the second controllable time delay module.
In some possible embodiments, at least two chips each further comprise a fourth integer divider and a third controllable time delay module; the master clock phase-locked loop module is also connected with a fourth integer frequency divider, the fourth integer frequency divider is connected with a third controllable time delay module, and the clock synchronization calibration control module is also connected with the third controllable time delay module.
In some possible embodiments, the system further comprises a third off-chip equal length power splitting module, the third off-chip equal length power splitting module being connected to each of the chips.
In some possible embodiments, at least two chips further include a frequency modulation local oscillation source module, a frequency modulation local oscillation signal output control module, a local oscillation signal selection control module, a frequency multiplier and a power divider; the frequency modulation local oscillation source module is connected with the frequency modulation local oscillation signal output control module, the frequency modulation local oscillation signal output control module is connected with the third external equal-length power dividing module, the third external equal-length power dividing module is connected with the local oscillation signal selection control module, the local oscillation signal selection control module is connected with the frequency multiplier, and the frequency multiplier is connected with the power divider.
It can be appreciated that the beneficial effects of the cascaded system of the front-end chip for transmitting and receiving millimeter wave radar can be referred to the description of the cascaded synchronization method of the front-end chip for transmitting and receiving millimeter wave radar in the foregoing embodiment, and will not be repeated.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.
The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims (18)

1. The cascade synchronization method for the millimeter wave radar receiving and transmitting front end chip is characterized by comprising the following steps of:
the method comprises the steps that a first chip receives an external reference clock signal, and the first chip is in a main chip working mode;
the first chip generates a first reference clock signal according to the external reference clock signal;
the first off-chip equal-length power dividing module equally divides the first reference clock signal into at least two paths of second reference clock signals, outputs one path of the at least two paths of second reference clock signals to the first chip, and outputs the other paths of second reference clock signals to the second chip in a one-to-one correspondence manner, wherein the second chip is in a slave chip working mode, and the time difference between the time of any two paths of second reference clock signals in the at least two paths of second reference clock signals reaching the corresponding chip is smaller than a first preset threshold value;
The first chip takes the received second reference clock signal as an internal reference clock signal of the first chip;
the second chip uses the received second reference clock signal as an internal reference clock signal of the second chip.
2. The method of claim 1, wherein prior to the first chip receiving an external reference clock signal, the method further comprises:
the first chip receives a first instruction, wherein the first instruction is used for indicating the first chip to enter the main chip working mode;
the second chip receives a second instruction, and the second instruction is used for indicating the second chip to enter the working mode of the slave chip.
3. The method of claim 2, wherein the first chip and the second chip each comprise a reference clock output control module, a master clock phase locked loop reference clock control module;
the chip entering the working mode of the main chip is used for generating the first reference clock signal according to the external reference clock signal through the reference clock output control module and taking the received second reference clock signal as an internal reference clock signal through the reference clock phase-locked loop reference clock control module;
The chip entering the working mode of the slave chip is used for taking the received second reference clock signal as an internal reference clock signal through the reference clock control module of the master clock phase-locked loop.
4. The method according to claim 1, wherein the method further comprises:
the first chip generates a sequential logic control digital clock signal of the first chip according to an internal reference clock signal of the first chip;
the second chip generates a sequential logic control digital clock signal of the second chip according to an internal reference clock signal of the second chip;
the first chip receives a waveform modulation trigger signal;
the first chip controls a digital clock signal according to the sequential logic of the first chip, samples the waveform modulation trigger signal and generates a first waveform trigger synchronous signal;
the second off-chip equal-length power dividing module generates at least two paths of second waveform trigger synchronous signals according to the first waveform trigger synchronous signals, outputs one path of the at least two paths of second waveform trigger synchronous signals to the first chip, and outputs the other paths of second waveform trigger synchronous signals to the second chip in a one-to-one correspondence manner, wherein the time length of the at least two paths of second waveform trigger synchronous signals reaching the corresponding chips is the same;
The first chip controls a digital clock signal according to the sequential logic of the first chip, samples the received second waveform triggering synchronous signal, and generates an internal waveform modulation and processing indication signal of the first chip;
the second chip controls the digital clock signal according to the time sequence logic of the second chip, samples the received second waveform triggering synchronous signal, and generates an internal waveform modulation and processing indication signal of the second chip.
5. The method of claim 4, wherein the first chip and the second chip each comprise a master clock phase-locked loop module, a first integer divider, a second integer divider, a clock synchronization calibration control module, a first controllable time delay module;
the first chip is used for generating a high-frequency reference clock signal according to the obtained internal reference clock signal through the master clock phase-locked loop module, and generating the frequency modulation local oscillator source reference clock signal according to the high-frequency reference clock signal through the first integer frequency divider; the first integer frequency divider is used for generating an initial sequential logic control digital clock signal according to the generated high-frequency reference clock signal; the clock synchronization calibration control module is further used for performing time delay adjustment on the generated initial sequential logic control digital clock signal through the first controllable time delay module according to the obtained internal reference clock signal and the output signal of the first controllable time delay module to obtain a sequential logic control digital clock signal;
The second chip is used for generating a high-frequency reference clock signal according to the obtained internal reference clock signal through the master clock phase-locked loop module, and generating an initial sequential logic control digital clock signal according to the generated high-frequency reference clock signal through the second integer frequency divider; and the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated initial sequential logic control digital clock signal through the first controllable time delay module according to the obtained internal reference clock signal and the output signal of the first controllable time delay module to obtain the sequential logic control digital clock signal.
6. The method of claim 5, wherein the first chip and the second chip each further comprise a third integer divider and a second controllable time delay module;
the first chip and the second chip are both further used for generating an initial analog-to-digital converter sampling clock signal through the third integer frequency divider according to a high-frequency reference clock signal generated by the master clock phase-locked loop module; and the clock synchronous calibration control module is also used for carrying out time delay adjustment on the generated sampling clock signal of the initial analog-to-digital converter through the second controllable time delay module according to the obtained internal reference clock signal and the output signal of the second controllable time delay module so as to obtain the sampling clock signal of the analog-to-digital converter.
7. The method of claim 5, wherein the first chip and the second chip each further comprise a fourth integer divider and a third controllable time delay module;
the first chip and the second chip are both used for generating an initial data interface clock signal according to a high-frequency reference clock signal generated by the master clock phase-locked loop module through the fourth integer frequency divider; and the clock synchronization calibration control module is also used for carrying out time delay adjustment on the generated initial data interface clock signal through the third controllable time delay module according to the obtained internal reference clock signal and the output signal of the third controllable time delay module to obtain the data interface clock signal.
8. The method according to any one of claims 4-7, further comprising:
the first chip generates a frequency modulation local vibration source reference clock signal according to the internal reference clock signal of the first chip; generating a first frequency modulation continuous wave local oscillation signal according to the frequency modulation local oscillation source reference clock signal;
the third off-chip equal-length power dividing module generates at least two paths of second frequency-modulated continuous wave local oscillation signals according to the first frequency-modulated continuous wave local oscillation signals, outputs one path of the at least two paths of second frequency-modulated continuous wave local oscillation signals to the first chip, outputs the other paths of second frequency-modulated continuous wave local oscillation signals to the second chip in a one-to-one correspondence manner, and the time length for the at least two paths of second frequency-modulated continuous wave local oscillation signals to reach the corresponding chips is the same;
The first chip generates a radio frequency signal of the first chip by receiving the second frequency modulation continuous wave local oscillation signal;
and the second chip generates a radio frequency signal of the second chip by receiving the second frequency modulation continuous wave local oscillation signal.
9. The method of claim 8, wherein the first chip and the second chip each further comprise a frequency modulation local oscillation source module, a frequency modulation local oscillation signal output control module, a local oscillation signal selection control module, a frequency multiplier, and a power divider;
the first chip is used for generating a frequency-modulated local oscillation signal according to the frequency-modulated local oscillation source reference clock signal through a frequency-modulated local oscillation source module, and generating the first frequency-modulated continuous wave local oscillation signal through a frequency-modulated local oscillation signal output control module according to the frequency-modulated local oscillation signal obtained by the frequency-modulated local oscillation source module; the local oscillator signal selection control module is also used for taking the received second frequency modulation continuous wave local oscillator signal as an input signal of the frequency multiplier, generating a radio frequency signal according to the received second frequency modulation continuous wave local oscillator signal through the frequency multiplier, and performing power division on the radio frequency signal through the power divider and outputting the radio frequency signal to a receiving and transmitting channel;
The second chip is used for using the received second frequency-modulated continuous wave local oscillation signal as an input signal of the frequency multiplier through the local oscillation signal selection control module, generating a radio frequency signal through the frequency multiplier according to the received second frequency-modulated continuous wave local oscillation signal, and performing power division on the radio frequency signal through the power divider and outputting the radio frequency signal to a receiving and transmitting channel.
10. A millimeter wave radar transceiver front-end chip cascade system, the system comprising:
at least two chips and a first off-chip equal-length power dividing module;
the first off-chip equal-length power dividing module is respectively connected with each chip, and the at least two chips comprise a first chip in a main chip working mode and a second chip in a main chip working mode; the difference between the distances between the first off-chip equal-length power dividing module and the connecting wires of any two chips is smaller than a second preset threshold value;
the system being adapted to implement the method of any one of claims 1-9.
11. The system of claim 10, wherein the first off-chip equal length power splitting module is connected to each of the chips equal length wires, respectively.
12. The system of claim 10, wherein the at least two chips each comprise a reference clock output control module, a master clock phase locked loop reference clock control module; the reference clock output control module is connected with the first external equal-length power dividing module, and the first external equal-length power dividing module is connected with the master clock phase-locked loop reference clock control module.
13. The system of claim 10 further comprising a second off-chip equal length power splitting module, the second off-chip equal length power splitting module being respectively coupled to each of the chips.
14. The system of claim 13, wherein the at least two chips each comprise a master clock phase-locked loop module, a first integer divider, a second integer divider, a clock synchronization calibration control module, a first controllable time delay module;
the master clock phase-locked loop module is respectively connected with the first integer frequency divider and the second integer frequency divider, the second integer frequency divider is connected with the first controllable time delay module, and the clock synchronous calibration control module is connected with the first controllable time delay module.
15. The system of claim 14, wherein the at least two chips each further comprise a third integer divider and a second controllable time delay module;
the master clock phase-locked loop module is further connected with the third integer frequency divider, the third integer frequency divider is connected with the second controllable time delay module, and the clock synchronization calibration control module is further connected with the second controllable time delay module.
16. The system of claim 14, wherein the at least two chips each further comprise a fourth integer divider and a third controllable time delay module;
the master clock phase-locked loop module is further connected with the fourth integer frequency divider, the fourth integer frequency divider is connected with the third controllable time delay module, and the clock synchronization calibration control module is further connected with the third controllable time delay module.
17. The system of any one of claims 10-16, further comprising a third off-board equal length power splitting module, the third off-board equal length power splitting module being respectively coupled to each of the chips.
18. The system of claim 17, wherein the at least two chips each further comprise a fm local oscillator source module, a fm local oscillator signal output control module, a local oscillator signal selection control module, a frequency multiplier, and a power divider;
the frequency modulation local oscillation source module is connected with the frequency modulation local oscillation signal output control module, the frequency modulation local oscillation signal output control module is connected with the third off-chip equal-length power dividing module, the third off-chip equal-length power dividing module is connected with the local oscillation signal selection control module, the local oscillation signal selection control module is connected with the frequency multiplier, and the frequency multiplier is connected with the power divider.
CN202311395973.5A 2023-10-25 2023-10-25 Cascading synchronization method and cascading system for millimeter wave radar receiving and transmitting front-end chip Pending CN117675159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311395973.5A CN117675159A (en) 2023-10-25 2023-10-25 Cascading synchronization method and cascading system for millimeter wave radar receiving and transmitting front-end chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311395973.5A CN117675159A (en) 2023-10-25 2023-10-25 Cascading synchronization method and cascading system for millimeter wave radar receiving and transmitting front-end chip

Publications (1)

Publication Number Publication Date
CN117675159A true CN117675159A (en) 2024-03-08

Family

ID=90074185

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311395973.5A Pending CN117675159A (en) 2023-10-25 2023-10-25 Cascading synchronization method and cascading system for millimeter wave radar receiving and transmitting front-end chip

Country Status (1)

Country Link
CN (1) CN117675159A (en)

Similar Documents

Publication Publication Date Title
EP3611540B1 (en) Apparatus and methods for synchronization of radar chips
US11543509B2 (en) Bi-static radar system
US20200292666A1 (en) Multi-chip synchronization for digital radars
JP7193692B2 (en) Timing for IC chip
EP3591434B1 (en) Communication unit, integrated circuits and method for clock and data synchronization
CN102882673B (en) Multi-channel high-speed digital-to-analogue converter (DAC) synchronization method
US9465404B2 (en) Timing synchronization circuit for wireless communication apparatus
US10788351B2 (en) Fill level measurement device comprising a plurality of radar chips
EP3591435B1 (en) Communication unit, integrated circuit and method for clock distribution and synchronization
CN109728806B (en) Apparatus comprising a phase locked loop
EP3591433B1 (en) Communication unit, integrated circuits and method for clock and data synchronization
EP2207263B1 (en) A digital time base generator and method for providing a first clock signal and a second clock signal
US10542312B1 (en) High speed data transfer
EP3591431B1 (en) Communication unit and method for clock distribution and synchronization
CN106526582B (en) Double base Radar system
CN103728893A (en) High-precision time-sequence control circuit of ground penetrating radar
JP2535816Y2 (en) Radar equipment
CN117675159A (en) Cascading synchronization method and cascading system for millimeter wave radar receiving and transmitting front-end chip
Ji et al. The synchronization design of multi-channel digital TR module for phased array radar
KR101788257B1 (en) Digital receiver for collecting of synchronized streaming data
KR101784963B1 (en) Method for collecting of synchronized streaming data in digital receiver
KR101788256B1 (en) Digital receiver and method for collecting of streaming data in digital receiver
CN111273252A (en) Deskewing method based on synchronization of multiple DDSs
WO2023160098A1 (en) Signal synchronization method and apparatus, and readable storage medium
JP7418660B2 (en) Triggers for data synchronization of gigahertz digital-to-analog converters

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination