JP7193692B2 - Timing for IC chip - Google Patents

Description

TECHNICAL FIELD This application relates generally to integrated circuit (IC) chips, and more particularly to IC chips that generate timing for controlling sampling in radio frequency (RF) receivers.

A clock signal is a particular type of signal that oscillates between high and low states. Although more complex arrangements are also used, the most common clock signal is in the form of a square wave with a 50% duty cycle and usually has a fixed constant frequency. Circuitry that uses the clock signal for synchronization can be active either on the rising edge or on the falling edge, or on both the rising and falling edges of the clock cycle in the case of double data rate. Clock signals are used to coordinate the behavior of components in digital circuits. A clock signal is generated by a clock generator. As an example, radar systems use clock signals to synchronize the operation of transmitters, receivers, and other components.

One example relates to an integrated circuit (IC) chip that may contain a root timer that generates a frame pulse based on a start trigger signal. The IC chip may also include a hardware clock control that provides a clock signal based on selected ones of frame pulses and synchronization signals provided from one of the root timer and the other IC chip. The IC chip may also include an analog-to-digital converter (ADC). Each ADC is configured to sample the output of a respective one of a plurality of radio frequency (RF) receivers based on a clock signal.

Another example relates to an IC chip that may include a microcontroller that generates a software trigger signal and a trigger selector that receives the software trigger signal, selects a synchronization signal, and provides a start trigger signal. The IC chip may also contain a root timer that generates a synchronization signal based on the start trigger signal. A sync signal may be provided to a sync output port of the IC chip coupled to a sync input port of the IC chip. The IC chip may also include a hardware clock control that provides a clock signal based on the synchronization signal received at the synchronization input port. The IC chip further includes ADCs each configured to sample a respective one output of the plurality of receivers based on the clock signal.

Yet another example relates to radar systems that may include radar controllers that process radar data to determine the position of objects. A radar system may also include a master radar integrated circuit (IC) chip. A master IC chip may be configured to sample the received RF signal at predetermined instances. The sampling timing is based on a synchronization signal generated by the master IC chip. The master IC chip may also implement software operations based on timing corresponding to the synchronization signal. A radar system may also include one or more slave IC chips. Each of the one or more slave IC chips may be configured to sample the received RF signal at predetermined instances. The sampling timing may be based on a synchronization signal generated by the master IC chip. Each slave IC chip may also be configured to perform software operations based on timing corresponding to the synchronization signal.

1 shows a diagram of an example integrated circuit (IC) chip. FIG.

FIG. 2 shows a timing diagram for an IC chip; FIG. FIG. 2 shows a timing diagram for an IC chip; FIG.

FIG. 2 shows a diagram for a radar IC chip; FIG.

1 shows a timing diagram of a radar IC chip; FIG.

1 shows a diagram of an example of a radar IC chip operating in single mode; FIG.

1 shows a diagram of an example radar IC chip operating in master mode. FIG.

1 shows a diagram of an example radar IC chip operating in slave mode. FIG.

An example of a radar system is shown.

2 shows another example of a radar system.

In the example described, an integrated circuit (IC) chip may generate clock signals to control the operation of various components within the IC chip and within other IC chips. The IC chip can be programmed/configured to operate in single mode, master mode, or slave mode. The IC chip contains functionality for controlling modules including analog-to-digital converters (ADCs) that sample radio frequency (RF) receivers that require a relatively high degree of synchronization (eg, within 10 nanoseconds). The IC chip may also control the operation of software functions (eg, calibration and built-in self-test (BIST)) that require synchronization within timing of approximately 10 microseconds.

In single mode, the IC chip can control its own timing operations. In master mode, an IC chip can be used to generate synchronization signals that are provided to one or more IC chips operating in slave mode. The synchronization signal can be used to generate a "root" trigger (e.g. frame pulse), which is used to control the timing of modules (e.g. ADC) operating on the IC chip. It can be used to generate one or more "leaf" triggers. Root triggers can also be used by processing units (eg, microcontrollers) to control the operation of software functions. In this way, the same IC radar chip design can be used in a single IC chip solution or a multiple IC chip solution. In many examples herein, timing is described in the context of equivalent acts of components implemented in one or more radar IC chips. However, the approaches described herein are applicable to other types of IC chips, such as for providing inter-chip synchronization.

FIG. 1 shows a block diagram of an example of an IC chip 2. As shown in FIG. For example, the IC chip 2 can be used in radar systems. In such situations, the IC chip 2 can be used in radar-based automotive detection systems, such as collision avoidance systems, automatic lane shift systems, and auto-cruise control systems. As described herein, IC chip 2 may be implemented in a single IC chip 2 solution, or may be in communication with one or more additional IC chips 2 that operate in a similar manner. can be

IC chip 2 may include modules for performing certain operations of IC chip 2 . Also, while modules of IC chip 2 are described as performing certain radar-related functions, in other examples, different modules may perform functions other than those described herein.

IC chip 2 may include a microcontroller unit (MCU) 6 . MCU 6 may include a processor core configured to execute machine-readable instructions stored on non-transitory machine-readable media. The non-transitory machine-readable medium may be embedded in MCU6 or may be external to MCU6. In some examples, MCU 6 may operate as a digital signal processor (DSP).

The IC chip 2 has a system clock, which is a signal of known frequency. The system clock can be used directly or indirectly after division or multiplication by digital hardware circuits and processors on the chip. In some examples, the system clock may be generated (eg, locally) within IC chip 2, such as by an oscillator or a phase-locked loop. Alternatively, in another example, the system clock may be received at an input pin of IC chip 2 from an external source.

The IC chip 2 can be configured to operate in any of multiple modes, which can include single mode, master mode, or slave mode. IC chip 2 may include a trigger selector 8 that may be controlled by a mode control signal (labeled "MODE CONTROL" in FIG. 1). For example, trigger selector 8 can be a multiplexer. Also, the mode control signal may be generated locally (eg, by MCU 6) or the mode control signal may be provided from an external source (eg, radar controller). In yet another example, the mode control signal can be controlled by an input pin of IC chip 2 .

In situations where IC chip 2 is operating in single mode, MCU 6 may provide trigger selector 8 with software triggers that may be generated by software running on MCU 6 . A software trigger may be passed to the root timer 10, which may generate a root trigger (eg, frame pulse) in response to the software trigger. In such situations, the root trigger may be a pass-through version (eg, delayed or non-delayed) of the software trigger. A root trigger may be provided to hardware clock control 12 and returned to MCU 6 . In response, hardware clock control 12 may generate a leaf timer (a timer that is a slave to the root trigger generated by root timer 10), which may be triggered by transceiver 14 and/or IC chip 2. may control the operation of other circuits in or components of external circuits. Hardware clock control 12 may be formed of discrete circuit components (eg, timers, digital logic gates, transistors, and switches) capable of generating and controlling timing signals.

Transceiver 14 may include M transmitters 16, where M is an integer greater than or equal to one. Transceiver 14 may also include N receivers 18, where N is an integer greater than or equal to one. Some examples have more receivers 18 than transmitters 16 (or vice versa). For example, transceiver 14 may include three transmitters and four receivers. Some examples have equal numbers of receivers 18 and transmitters 16 . Each transmitter 16 may be coupled to a transmit antenna capable of emitting radio frequency (RF) signals at specific frequencies in a frequency band. Each receiver 18 may also be coupled to a receive antenna capable of detecting RF signals within a frequency band. In some examples, the frequency band of M transmitters 16 and N receivers 18 may range from about 80 gigahertz (GHz) to about 81 GHz. In other examples, a different frequency may be used, such as a frequency of approximately 76 GHz.

Transceiver 14 may include components such as local oscillator (LO) 22 for facilitating generation of signals to be transmitted by transmitter 16 . Transceiver 14 may also include N analog-to-digital converters (ADCs) each coupled to a (matched) receiver 18 . Each ADC 20 may be configured to sample the signal received by its corresponding receiver 18 . In other words, the second ADC 20 (labeled "ADC2" in FIG. 2) may be configured to sample the RF signal detected by the second receiver 18 (labeled "RX2" in FIG. 1). . Each ADC 20 may be configured to sample the RF signal detected by its respective receiver 18 at a predetermined clock rate. In some examples, the predetermined clock rate may be approximately 1.8 GHz, and in other examples higher or lower sampling rates may be used.

In single mode, based on the root trigger, hardware clock control 12 may control the period of time at which transmitter 16 transmits RF signals and the frequency at which transmitter 16 transmits RF signals (via LO 22). Hardware clock control 12 may also control the times at which receiver 18 receives incoming RF signals. Hardware clock control 12 may also control the time at which each of ADCs 20 samples the RF signal detected by corresponding receiver 18 . Thus, hardware clock control 12 may control the duration and order of operation of components on IC chip 2 .

A sample RF signal may be provided to MCU 6 . MCU 6 may process the sampled RF signals in radar chirps to derive data indicative of the presence (or absence) of detected objects in the automotive detection system. In some examples, MCU 6 may make determinations regarding the location of the object. Additionally or alternatively, the MCU 6 provides data to an external system (e.g. radar controller) to coordinate data from multiple IC chips 2 to determine the position of the object relative to the automotive detection system. obtain.

Root timer 10 may also provide root triggers to MCU 6 . In response, a software module in MCU 6 (eg, a software processor timing module) may control the scheduling of software operations and/or hardware tests. For example, MCU 6 may schedule calibration tests for each of M transmitters 16 and N receivers 18 . In such situations, MCU 6 may ensure that only a particular set of transmitters 16 and/or receivers 18 are calibrated at any given time, thereby avoiding unintended interference. MCU 6 may also use the root trigger to determine when to run built-in self-tests (BIST), radar chirps, and the like.

In single mode, operations controlled by the hardware clock control 12 can be synchronized within a "tight window". As used herein, the term “tight window” means that motion occurs within a predefined time with an uncertainty around that predefined time of approximately 0.3 ns. indicates that Depending on the clock frequency used in the system, the uncertainty can be up to about 10ns. Also, software operations controlled by MCU 6 can be synchronized within a "loose window" of about 10 μs. As used herein, the term “loose window” means that motion occurs within a predefined time, during which there is relatively less uncertainty around the predefined time than a tight window. It is shown to have a large uncertainty, up to about 10 μs. The terms "tight window" and "loose window" are used multiple times throughout the specification in this sense.

In situations where an IC chip 2 operates in master mode, root timer 10 provides a synchronization signal to another IC chip 2 (not shown) via its output pin. This further IC chip 2 may be identical to IC chip 2, but may operate in slave mode in response to a mode control signal. Also, in master mode, the synchronization signal is provided to the hardware clock control 12 . As noted above, hardware clock control 12 also receives mode control signals. In response to the mode control signal being set to master and the synchronization trigger being activated, the hardware clock control 12 operates in a manner similar to that described for the single mode of operation (which is based on the root trigger). and controls the transceiver 14 based on the synchronization signal. In master mode, MCU 6 also controls transceiver operations (eg, calibration, BIST, radar chirp, etc.).

In situations where the IC chip 2 operates in slave mode, a synchronization signal is received at the input of the IC chip from another external IC chip operating in master mode. A synchronization signal is provided to the trigger selector 8 and the hardware clock control 12 . Also, the mode control signal is set to slave, distributed within the IC chip, and provided to the trigger selector 8 and the hardware clock control 12 . The mode control signal (set to slave) causes trigger selector 8 and hardware clock control 12 to select synchronous triggers to control the generation of clock signals in root timer 10 and hardware clock control 12 . For example, a pulse in the sync signal may cause the root trigger output by root timer 10 to be reset to adjust to the sync signal. Also, the hardware clock control 12 and MCU 6 continue to operate in the same manner as in single mode and master mode operation, with timing dictated by the synchronization signal. In a multi-chip example in which one IC chip 2 operates in master mode and one or more IC chips 2 operate in slave mode, the operation of the IC chips 2 operating in slave mode is local (e.g., IC chip 2) by a component local to Also, the timing of such operations is controlled by an external source (another IC chip 2) that provides a synchronization signal.

Inter-chip hardware operations (e.g., ADC 20 sampling) can be synchronized within a "tight window". Also, software operations across multiple IC chips 2 that do not require such tight synchronization can be synchronized within a "loose window." In addition, since the synchronization signal is common among the IC chips 2, a handshake procedure (for example, , procedures for establishing new channels).

As described, the same IC chip 2 can be deployed by itself (e.g. single mode) or one IC chip 2 acts as a master (in master mode) and the remaining one or more It can be deployed in a multi-chip system (eg, a multi-chip radar system) where the IC chips act as slaves (in slave mode).

FIG. 2 shows a timing diagram 50 illustrating an example of coordinated (synchronized) sampling of a hardware ADC in a multichip radar system. FIG. 3 illustrates another timing diagram 60 showing an example of coordinated software timing of radar chips in a multi-chip radar system. Timing diagram 50 and timing diagram 60 assume four IC chips 2 of the type illustrated in FIG. Works in slave mode. Also, each radar chip 2 has four ADCs 20, for a total of 16 ADCs 20 (corresponding to the signals shown as ADC1 to ADC16 in FIG. 2). Thus, reference is made to the exemplary IC chip 2 of FIG. 1 in connection with the description of FIGS.

In the example of FIG. 2, timing diagram 50 plots the output frequency of transmitter 16 (controlled by LO 22) as a function of time in microseconds (μs). As illustrated in timing diagram 50, the frequency is ramped from 80 GHz to 81 GHz over a period of approximately 80 μs. Also, each of the 16 ADCs 20 is configured to sample its corresponding receiver within a tight window during each frequency ramp.

Timing diagram 40 illustrates the behavior of RF frequency with respect to time. In a Frequency Modulated Continuous Wave Radar (FMCW Radar) system, LO22 produces a signal with a frequency that varies (ramps up or down) linearly in time from 80 GHz to 81 GHz over 90 microseconds (90 μs). One or more of the M transmitters 16 illustrated in FIG. 1 may amplify and transmit this signal using antennas. The electromagnetic signals are received using the antenna and circuitry present in one or more of the N receivers 18 illustrated in FIG. Each of the N ADCs 20 illustrated in FIG. 1 samples the output of a corresponding one of the N receivers 18 . In timing diagram 50, the time between 0 μs and 100 μs is called one chirp. A radar frame contains a series of chirps. Radar frame properties include specified numbers and sequences of chirps, and properties of the radar frame's constituent chirps. Chirp properties include when and for how long the LO frequency should start ramping up or down, when the transmitter 16 and receiver 18 should be activated and deactivated, when the ADC 20 should sample the receiver 18 output. It contains information indicating whether

As an example of the operation of a multichip radar system, sampling each of the 16 ADCs 20 at approximately the same time indicates that any receiver 18 of the multichip radar system will receive the transmitted signal reflected by the detected object (which may be referred to as a reflected signal) and may provide information indicating which receivers 18 do not receive the reflected signal. A distance between an object and a multi-chip radar system may be determined based, for example, on the frequency difference between the time of transmission of the transmitted signal and the time of sampling of the reflected signal. For example, the difference in frequency can be used to determine the time of flight of the transmitted and reflected signals, which can be used to calculate the distance to the detected object.

In the example of FIG. 3, timing diagram 60 plots output frequency as a function of time in milliseconds (ms). For ease of illustration, timing diagrams 50 and 60 plot the same lamp output signal on different scales (μs for timing diagram 50 and ms for timing diagram 60). As shown in timing diagram 60 of FIG. 3, at specific scheduled times (which can be periodic or asynchronous), transceiver calibration (denoted as "CAL" in timing diagram 60) is performed. . As will be explained, software running on each MCU 6, to perform mutual calibration, radar chirp, and/or BIST, and to avoid unwanted interference between the various IC chips 2: Schedule calibration, radar chirp triggering, and BIST (and/or other software operations) to run synchronously (eg, within about 10 μs).

In each of timing diagrams 50 and 60 a frame trigger (FT) is illustrated. FT can be an example of a clock edge in a frame pulse. FT may be provided by a synchronization signal, which may be generated by the root timer 10 of the master IC chip 2 and provided to the three slave IC chips 2 . Software operations can be synchronized within about 10 μs across each of the IC chips 2 in the radar system. Thus, by operating the IC chip 2 in master and slave modes, hardware operations (e.g. sampling of the ADC 20) can be synchronized within a tight window while requiring such tight synchronization. Software operations across multiple IC chips 2 can be synchronized within a loose window. Using multiple IC chips 2 enables beamforming (eg, using 16 or more receivers 18). Therefore, the IC chip 2 can be used for short-range or long-range radar (eg, within 10-200 meters) detection in automotive detection systems. In other examples, the IC chip 2 can also be used in industrial systems requiring radar with beamforming.

Synchronizing hardware operations (eg, receiver sampling) and software operations avoids mutual RF interference during self-calibration of transmitter 16 and receiver 18 associated with IC chip 2 .

FIG. 4 shows a component diagram of an example radar IC chip 100 . Radar IC chip 100 can be used to implement IC chip 2 of FIG. Radar IC chip 100 may include MCU 102 . MCU 102 may be a microcontroller such as a DSP. MCU 102 may include machine-executable instructions for handling timing functions. A separate component labeled software timing 104 is shown external to MCU 102 for purposes of simplicity. However, software timing 104 represents software modules (eg, machine-readable instructions) executing on MCU 102 .

IC chip 2 may include a trigger selector 106 such as a multiplexer. Trigger selector 106 can be configured to output a start trigger signal (labeled "Start Trigger" in FIG. 4), which can be a software trigger (labeled "SW Trigger" in FIG. 4) and a trigger. Based on one of the hardware triggers (denoted “HW trigger” in FIG. 4) that may be received at selector 106 . Software triggers may be generated on-chip and provided from MCU 102 . A hardware trigger (used as a sync signal) can be provided from the sync input port 105 (shown as "SYNCH INPUT" in FIG. 4), either by the 100 chip (if in master mode) or by another chip ( in slave mode). Trigger selector 106 may select either a software trigger or a hardware trigger based on a mode control signal (shown as "MODE CONTROL" in FIG. 4). A mode control signal may be provided by MCU 102 or an external source. Alternatively, in other examples, the mode control signal may be hardwired to the trigger selector 106 . In yet another example, trigger selector 106 may include internal logic for selecting trigger selector 106 in response to detecting an event or condition associated with the chip or system in which IC chip 2 is implemented.

For example, the start trigger can be a frame pulse signal. As used herein, the term "frame pulse" refers to a pulse signal having a clock edge at the beginning of each frame or having a clock edge at the beginning of a predetermined number of frames. Thus, the start trigger can be a pulse signal with a clock pulse indicating the start of a frame (eg approximately every 40 ms) or a predetermined number of frames. A start trigger may be provided to root timer 108 . In response to each pulse in the start trigger, root timer 108 may generate a root trigger (eg, frame pulse), which also marks the start of a frame. Thus, in some examples, the root trigger can be a pass-through version of the start trigger. Alternatively, the root trigger can be a delayed version of the start trigger (eg, delayed by one or more clock pulses). The root trigger may be output to the hardware clock control 111 component. Components of hardware clock control 111 may implement hardware clock control 12 of FIG.

As an example, a root trigger may be provided to the input of clock selector 112 of hardware clock control 111 . Clock selector 112 outputs a start clock signal (shown as "START CLK" in FIG. 4) corresponding to either the root trigger or a synchronization signal received at synchronization input port 105 (described herein). can be output. Clock selector 112 may be controlled by a mode control signal.

Root timer 108 may also provide a free running counter (FRC) signal (denoted “FRC” in FIG. 4) to hardware leaf timer module 114 of hardware clock control 111 . Hardware leaf timer module 114 represents a collection of hardware leaf timers that each generate one or more timing signals. Hardware leaf timer module 114 may generate several digital signals (timing signals) via hardware leaf timers that control the timing of various activities in radar IC chip 100 . These activities may include enabling and disabling various receiver, transmitter, and/or LO circuits, starting and stopping the LO output signal frequency from ramping up or down, starting digital processing of the ADC output, and the like. A hardware leaf timer may include circuitry that may generate timing and/or timing control signals that are synchronized based on the root trigger provided by root timer 108 . Similarly, root timer 108 may provide an FRC signal to software timing module 104 (of MCU 102). Also, in some modes of operation, such as master mode and slave mode, root timer 108 sends a synchronization signal (which may correspond to a hardware trigger signal) to synchronization output port 115 (see FIG. 1) of radar IC chip 100 . 4) labeled "SYNCH OUTPUT"). In some examples, the synchronization signal may be pulsed each time FRC reaches a predetermined value.

Clock selector 112 may provide a start clock signal to an input of synchronization gate 116 of hardware clock control 111 . Sync gater 116 may also receive a clock stop signal (denoted as “STOP CLK” in FIG. 4) from hardware leaf timer module 114 at a predefined time after the frame pulse or sync signal. Synchronization gate 116 may receive a clock signal from ADC clock generator 118 of hardware clock control 111 . The clock signal from ADC clock generator 118 may have clock pulses at specific instances (eg, approximately every 2-10 μs). Synchronization gate 116 may be designed as a digital circuit including logic gates and latches or flip-flops that ensure that the input clock is transferred to the output without glitches.

Synchronous gate 116 may be implemented as a digital circuit including one or more digital logic gates and latches or flip-flops. Synchronization gate 116 ensures that the clock edges of the clock signal from ADC clock generator 118 are synchronous from the frame pulse initiated at the start clock until the stop clock signal is pulsed from hardware leaf timer module 114 . It can be configured to allow output at the output of gater 116 . Enabling and disabling of the output clock is done to prevent glitches in the output clock at any time. The output of sync gate 116 is coupled to each of the four ADCs 120 and used by the sampling clock and digital state machine clock by ADC 120 and its components. Each of ADCs 120 may be coupled to a respective receiver (eg, receiver 18 of FIG. 1). In some examples, the receiver may be external to radar IC chip 100 . In other examples, the receiver may be integrated within radar IC chip 100 . As mentioned above, sync gate 116 prevents glitches at the output. Thus, the hardware leaf timers using the output of the synchronization gate 116 operate to receive clock inputs during the period that the hardware leaf timer is required to operate, and at the end of that period, each hardware leaf timer's Input clock is automatically gated.

For simplicity of explanation, many examples are described herein with a hardware leaf timer module 114 and illustrated in FIGS. 6-8. Hardware leaf timer module 114 includes several hardware leaf timers that receive FRC and root triggers directly from root timer 108 . However, in many examples, the hardware leaf timer module 114 or some of the hardware leaf timers of the hardware leaf timer module 114 receive the output clock of the synchronization gater 116 thereby allowing the root timer 108 indirectly. It allows for tight synchronization, while the operation of other components remains the same as described in the examples herein.

Each of the four ADCs 120 enables internal clock, serial-to-parallel (S2P) interface, finite state machine (FSM), and/or sampling of the output of its respective receiver at a predetermined rate (e.g., 1.8 GHz). may include other circuit components for Each ADC 120 may include a sigma-delta modulator (SDM) that samples the output of its respective receiver in response to signal pulses. For example, each ADC 120 may be designed such that a clock pulse at the output of sync gate 116 may ungate the SDM of each ADC 120, thereby causing each ADC 120 to sample the output of each respective receiver. The S2P interface may concatenate the bits sampled by each ADC 120 . A reset signal may also be provided from hardware leaf timer module 114 to reset each ADC 120 at a particular time instance. Thus, the start clock signal generated by ADC clock generator 118 is provided to ADCs 120 so that the FSM and S2P interfaces of each ADC 120 start the sampling cycle with the phase adjusted.

The hardware leaf timers generated by hardware leaf timer module 114 also control operations on associated transmitters (eg, transmitter 16 in FIG. 1) and/or LOs (eg, LO 22 shown in FIG. 1). obtain. The transmitter and/or LO can be internal or external to radar IC chip 100 . Hardware leaf timers may also control the order of operations in procedures such as DSPs and/or digital data paths. In this way, operations controlled by hardware leaf timers generated by hardware leaf timer module 114, including sampling of the receiver output, can be synchronized to a tight window.

Software timing module 104 may schedule operations such as calibration, BIST, radar chirp, and the like. Operations controlled by the software timing module 104 can be synchronized across IC chips within a loose window.

As one example software operation, a sample RF signal may be provided to MCU 102 from each of ADCs 120 . The MCU 102 may process the sampled RF signal in radar chirps to derive data indicative of the presence (or absence) of detected objects in automotive detection systems. In some examples, MCU 102 may make determinations regarding the location of the object. Additionally or alternatively, MCU 102 may send data to an external system (e.g., another radar IC chip) to coordinate data from multiple radar IC chips 100 to determine the position of an object relative to an automotive detection system. or radar controller). The radar controller (or other external system) may also provide MCU 102 with timing information that may control the order of operation of software timing module 104 to avoid interference with other radar IC chips 100 .

FIG. 5 illustrates example timing diagrams 150 , 152 , 154 , and 156 showing a set of hardware leaf timers output by hardware leaf timer module 114 . Each of the charts in FIG. 5 are scaled for the same frame of approximately 500 μs. In timing chart 150, the LO chirp signal frequency (labeled "CHARP LO FREQ" in FIG. 5) is plotted as a function of time. In one example, the frequency of the LO chirp signal can range from 80 GHz to 81 GHz. In another example, the frequency of the LO chirp signal may range from 20 GHz to 21 GHz. In still other examples, other frequencies may be used. In timing chart 152, the transmit signal (labeled "TX ENBLE" in FIG. 5) voltage is plotted as a function of time. The transmit enable signal causes the transmitter to transmit a signal at the frequency corresponding to the LO chirp signal.

Timing chart 154 plots the voltage of the receiver ADC enable signal (corresponding to the complement of the stop clock signal) as a function of time. The receiver ADC enable signal causes the receive ADC 120 to sample the corresponding receiver. Timing chart 156 also plots the voltage of the chirp Fast Fourier Transform (FFT) computing signal as a function of time. The chirp FFT computing signal causes MCU 102 to read the output of ADC 120 . This can be used, for example, in calculating the position and/or range of objects (eg, via digital signal processing) in automotive detection systems or other radar systems. As illustrated by timing diagrams 150-156, the hardware leaf timers generated by hardware leaf timer module 114 may control the operation of radar IC chip 100 within a tight window. Also, the list of example hardware leaf timers in FIG. 5 is not exhaustive. In some examples, the hardware leaf timer generated by hardware leaf timer module 114 may also or instead generate and/or transmit radar chirps, enable and disable receiver circuitry, and/or , controls the initiation of almost all radar operations.

Furthermore, hardware leaf timer module 114 may generate hardware leaf timers that control radar chirp-tuned signal generation, such as transmitter and/or receiver power control. For example, a hardware leaf timer may cause the transmitter and/or receiver to operate in a high performance, high power state during a radar chirp and operate in a low performance, low power state when the radar chirp ends.

As described above, the radar IC chip 100 can operate in single mode, master mode, or slave mode based on the mode control signal. FIG. 6 illustrates an example radar chip 100 operating in single mode. The same terminology and reference numbers are used in FIGS. 4 and 6 to denote the same structure. Also, for simplicity of explanation, some signals shown in FIG. 4 are omitted from FIG. 6 to illustrate the signal flow in single mode.

The mode control signal can be set to single mode so that trigger selector 106 outputs a software trigger from MCU 102 as the start trigger. Thus, the output of root timer 108 is controlled by MCU 102 . The clock selector 112 also selects the root trigger (frame pulse) output by the root timer 108 (in response to the mode control signal). Therefore, the output of sync gate 116 is controlled by MCU 102 . Also, in single mode, the radar IC chip 100 does not need to be synchronized with another radar IC chip. Thus, in single mode, there is no possibility of receiving an external hardware trigger and no synchronization signal needs to be provided. Thus, in single mode, MCU 102 may control sampling of ADC 120 , hardware leaf timers generated by hardware leaf timer module 114 , and software timing module 104 .

FIG. 7 illustrates an example radar chip 100 operating in master mode and coupled to another radar IC chip 100 operating in slave mode. The same terminology and reference numbers are used in FIGS. 4 and 7 to denote the same structure. Also, for simplicity of explanation, some signals shown in FIG. 4 are omitted from FIG. 7 to illustrate the signal flow in master mode.

The mode control signal can be set to master mode so that trigger selector 106 outputs a software trigger from MCU 102 as a start trigger. Thus, the output of root timer 108 is controlled by MCU 102 . A sync signal (frame pulse) is output by root timer 108 at sync output port 115 . In such situations, the synchronization signal output by root timer 108 operates on the root trigger signal. A synchronization signal is also fed back to radar IC chip 100 at synchronization input port 105 and coupled to clock selector 112 . The connection between sync input port 105 and sync output port 115 can be an external connection between pins of radar IC chip 100 or it can be implemented by an internal connection within radar IC chip 100 . In such situations, delays (eg, switches and/or timers) may be implemented in the internal connections to match the propagation delay to another radar IC chip 100 operating in slave mode.

The sync signal received at sync input port 105 is also selected by clock selector 112 (in response to the mode control signal). Therefore, the output of sync gate 116 is controlled by MCU 102 . Also, in master mode, a synchronization signal may be provided to one or more slave radar IC chips. Thus, in master mode, MCU 102 may control sampling of ADC 120 local to the radar IC chip, hardware leaf timers generated by hardware leaf timer module 114 , and software timing module 104 .

FIG. 8 illustrates an example radar chip 100 operating in slave mode, where radar IC chip 100 is coupled to another radar IC chip operating in master mode. The same terminology and reference numbers are used in FIGS. 4, 7 and 8 to denote the same structure. Also, for simplicity of explanation, some signals shown in FIG. 4 have been omitted from FIG. 8 to illustrate the signal flow in slave mode.

In slave mode, a sync signal is received at sync input port 105 . A synchronization signal may be provided from a radar IC chip operating in master mode and provided to trigger selector 106 as a hardware trigger (eg, frame pulse).

The mode control signal may be set to slave mode so that trigger selector 106 outputs a hardware trigger from MCU 102 as a start trigger. In response, root timer 108 may restart the root trigger based on the start trigger. The start trigger is based on a synchronization signal generated by an IC chip operating in master mode. In this way, the hardware trigger resynchronizes the root timer 108 of the radar IC chip 100 operating in slave mode so that the root timer 108 of the radar IC chip 100 operating in slave mode is synchronized to the IC chip operating in master mode. is adjusted to the root timer of Thus, the output of route timer 108 is controlled by the radar IC chip operating in master mode. Such resynchronization may reduce timer drift over a period of time.

Also, the sync signal received at sync input port 105 is selected by the clock selector (in response to the mode control signal). Therefore, the output of sync gate 116 is controlled by the radar IC chip operating in master mode. Thus, in slave mode, the synchronization signal provided by the radar IC chip operating in master mode is the sampling of ADC 120, the hardware leaf timer generated by hardware leaf timer module 114, and the radar IC chip operating in slave mode. A software timing module 104 local to the IC chip 200 may be controlled.

Since the root timer 108 of the radar chip 100 operating in slave mode is synchronized (via a synchronization signal) with the root timer of the radar chip operating in master mode, radar chip 100 operating in slave mode and operating in master mode. Radar chips may synchronize component (eg, transmitter and/or receiver) calibration, BIST, activity monitoring and functional radar chirps between various radar chips 100 . Also, as illustrated in FIGS. 7 and 8, the synchronization signal is applied to the radar IC chip operating in master mode (in FIG. 7) to ensure proper propagation delay match between the two radar IC chips. 100 and a synchronization input port 105 on both the radar IC chip 100 operating in slave mode (in FIG. 8).

As illustrated in FIGS. 4-8, the same radar IC chip 100 can operate in single mode, master mode, or slave mode. Therefore, in situations where multiple radar IC chips 100 are required, a radar IC chip 100 operating in master mode can control the overall timing for each of the radar IC chips 100 to which it is connected. Also, there is no need to redesign/manufacture a different radar IC chip 100 in situations where only one radar IC chip 100 is needed.

Software operations such as calibration and/or control of radar chirp may also be performed on the MCU 102 of the radar IC chip 100 even in situations where the radar IC chip 100 operates in slave mode. This architecture distributes the processing load of such software operations among the MCUs 102 of each connected radar IC chip 100 .

As illustrated and described with respect to FIGS. 4-8, hardware operations (including ADC 120 sampling) across multiple radar IC chips 100 may be synchronized within a tight window. Software operations across multiple radar IC chips 100 that do not require such tight synchronization can be synchronized within a loose window. Thus, the same radar IC chip 100 can be used to achieve two levels of synchronization (loose and tight) between multiple radar IC chips 100 in a multi-chip system. Also, since the synchronization signal is common between each radar IC chip 100 (as shown in FIGS. 7 and 8), between the master radar IC chip 100 and one or more slave radar IC chips 100: There is no need to implement a handshake procedure.

FIG. 9 illustrates an example radar system 200 that may use the radar IC chip 2 and/or the radar IC chip 100 illustrated in FIGS. The components of radar system 200 may be mounted on printed circuit board (PCB) 202 . For example, radar system 200 may be used in automotive detection systems or other radar systems. Radar system 200 may include radar control 204 to process radar data from a radar IC chip (eg, from an MCU operating thereon). Radar control 204 may be implemented as a microcontroller or one or more processor cores with access to memory storing machine-readable instructions.

Radar system 200 may also include a master radar IC chip 206 and K slave radar IC chips 208, where K is an integer greater than or equal to one. Master radar IC chip 206 may be implemented as radar chip 2 illustrated in FIG. 1 and/or radar IC chip 100 illustrated in FIGS. 5 and 7 operating in master mode. Each of the K slave radar IC chips 208 may be implemented as IC chip 2 illustrated in FIG. 1 and/or radar IC chip 100 illustrated in FIGS. 5 and 8 operating in slave mode. Thus, the master radar IC chip 206 and each of the K slave radar IC chips 208 can be different instances of the same chip design. The mode of operation of master radar IC chip 206 and K slave radar IC chips 208 may be set based on their respective local software configurations and/or based on IC chip pin configurations on PCB 202 .

The master radar IC chip 206 provides a synchronization signal (eg, a frame pulse labeled “SYNC SIGNAL” in FIG. 9) that is provided to each of the K slave radar IC chips 208 and fed back to the master radar IC chip 206. can be generated. Synchronization signals are provided between the master IC radar chip 206 and each of the K slave radar IC chips 208 to perform hardware operations (e.g., receiver sampling) in tight windows and software operations (self-calibration, BIST, radar chirp ), etc., can be synchronized in a loose window.

For example, radar control 204 may divide time windows (eg, via time division multiplexing) between master radar IC chip 206 and slave radar IC chip 208 to perform certain software functions (eg, tuning and/or BIST). can be allocated to Based on the allocated time window and synchronization signal, each of the master radar IC chip 206 and the slave radar IC chip 208 cooperate to avoid mutual interference that may occur during calibration and/or BIST. obtain.

Also, during operation, each of master radar IC chip 206 and slave radar IC chip 208 may provide radar data to radar control 204 . Radar data may include data that can be collated and used to determine the distance and direction of an object relative to the radar IC chip 2 .

Also, the master radar IC chip 206 uses only one signal, which may be provided over a single wire, such as a complementary metal-oxide-semiconductor (CMOS) signal wire (in some examples), to control the master radar IC chip 206. The operation of chip 206 and K slave radar IC chips 208 may be synchronized.

An example is described in connection with FIGS. 4-9. PCB 202 includes radar system 200 . Radar system 200 includes several radar IC chips, indicated as 206 and 208 in FIG. 9, each implemented as radar IC chip 100 shown in FIG. The radar control 204 and one of the radar IC chips 206 and 208 configure radar frame properties in the radar IC chips 206 and 208 . One of the radar IC chips, radar IC chip 206 in FIG. 9, is configured to operate in master mode and the remaining radar IC chip 208 is configured to operate in slave mode.

In master mode, the MCU 102 (illustrated in FIG. 4) of the master radar IC chip 206 generates a software trigger, which at 202 is a signal event that indicates to the radar system that a radar frame should occur. be. This event may be indicated in the form of a digital pulse, called a frame pulse as defined above. The trigger selector 106 (multiplexer) in the master radar IC chip 206 forwards this software trigger to the root timer 108 (shown in FIG. 4), which begins counting time from the time of this event ( The root timer 108 does this by counting how many system clock edges have occurred since this event). Software or firmware execution on the master radar IC in MCU 102 (illustrated in FIG. 4), or other digital state machine, triggers various radar operations when the route timer value reaches a predefined value. Radar operations may include performing radar component or radar chirp or frame calibration or BIST. Radar operations may also include generation of one or more subsequent software triggers by route timer 108 for MCU 102 . The frame pulse generated by root timer 108 is also sent to clock selector 112 (multiplexer) which is configured to forward the frame pulse to sync gate 116 .

Synchronous gates 116 may be implemented as a set of one or more digital logic gates and flip-flops. Synchronization gate 116 ensures that the clock edge of the clock signal from ADC clock generator 118 is set to ADC1-4 120 (see FIG. 4) during the time from the frame pulse until the stop clock signal is pulsed from hardware leaf timer module 114 shown) at the same time (or near the same time). This ensures that each of ADCs 1-4 120 samples their respective receiver output within a tight window so that the determination of the direction of the object orientation using the ADC output is accurate.

Root timer 108 also controls the timing of more counters in master radar IC chip 206, which are collectively represented by hardware leaf timer module 114 illustrated in FIG. Hardware leaf timer module 114 may generate several digital signals via hardware leaf timers. The digital signals enable and disable various RX/TX/LO circuits, start and stop ramping up or down the LO output signal frequency, start digital processing of the ADC output, etc., for various activities in the master radar IC chip 206. can control the timing of

The operation of one of the slave radar IC chips 208 will be described, the other slave radar IC chips 208 operate similarly. Also, the frame pulse generated by the root timer 108 of the master radar IC chip 206 is sent to the synchronization gate 116 and the root timer 108 of the slave radar IC chip 208, and the clock selector 112 and the trigger selector 106 of the slave radar IC chip 208, respectively. is transferred (as a synchronization signal) via an appropriate configuration of Upon receiving a frame pulse, the root timer 108 of the slave radar IC chip 208 resets itself and is brought into alignment with the root timer 108 of the master radar IC chip 206 (alignment can be the same value or a known difference value). can mean). The reset operation of the components in slave radar IC chip 208 is the same as master radar IC chip 206 . This ensures that ADCs 1-4 120 of the master radar IC chip 206 and ADCs 1-4 120 of the slave radar IC chip 208 sample their RX outputs at the same time (or nearly at the same time), so that objects using the ADC outputs Direction determination is accurate. The presence of more ADCs 120 in a combined master-slave system than in a system with only one radar IC chip provides improved object location determination capabilities. This also ensures that the hardware leaf timers in master radar IC chip 206 and slave radar IC chip 208 operate with tight window synchronization.

In one example, PCB 202 includes only slave radar IC chip 208 , and the function of software triggering or frame pulse generation is performed by a microcontroller functioning in radar control 204 instead of MCU 102 in master radar IC chip 206 . In such a situation, a software trigger or frame pulse is communicated to all slave radar IC chips 208 and the rest of the operation is similar to that described in the example above.

FIG. 10 illustrates another example radar system 250 . Radar system 250 may include a master IC chip 252 and a slave IC chip 254 . Master IC chip 252 may be implemented as an instance of radar IC chip 100 of FIG. 4 operating in master mode. Similarly, slave IC chip 254 may be implemented as an instance of radar IC chip 100 of FIG. 4 operating in slave mode. Thus, as described herein, each of master IC chip 252 and slave IC chip 254 may be implemented as different instances of the same IC chip design. Each of master IC chip 252 and slave IC chip 254 may be mounted on PCB 256 . Also, the mode of operation of each of master IC chip 252 and slave IC chip 254 may be set by software configuration and/or IC chip pin configuration on PCB 256, or the like.

Master IC chip 252 may include root timer 258 , which may generate a synchronization signal (shown as “SYNC SIGNAL” in FIG. 10) that is provided to trigger selector 260 of slave IC chip 254 . A synchronization signal can be a frame pulse signal that provides a clock edge at the beginning of each frame or the beginning of a set of frames. Trigger selector 260 may transfer the synchronization signal to root timer 262 of slave IC chip 254 as a start trigger signal. In response to each frame pulse in the start trigger (corresponding to the sync signal), root timer 262 may restart/reset the root trigger so that it is aligned to the sync signal.

Master IC chip 252 and slave IC chip 254 may each include microcontrollers (processors) 264 and 266 for performing radar operations with timing controlled directly or indirectly by synchronization signals. Radar operations may include triggering radar chirps, scheduling and executing BIST, calibrating RF receiver and RF transmitter circuitry, which may be local or external to each of master IC chip 252 and slave IC chip 254, and the like. Also, microcontrollers 264 and 266 can be used to perform nearly all software operations that rely on mutual coordination between master IC chip 252 and slave IC chip 254 .

Each of master IC chip 252 and slave IC chip 254 may include hardware clock controls 268 and 270 . Hardware clock control 268 may generate leaf timers for master IC chip 252 based on the synchronization signal. Similarly, hardware clock control 270 may generate leaf timers for slave IC chip 254 based on root triggers from root timer 262, which are based on synchronization signals. Also, based on the synchronization signal, the hardware clock control 268 can enable clock edges to control the sampling instances of the analog inputs of more ADCs 272 of the master IC chip 252, the data characterizing the samples being Output to master controller 264 . Similarly, based on the root trigger signal (which is based on the synchronization signal), hardware clock control 270 uses the clock edge to control sampling instances of analog inputs of one or more ADCs 274 of slave IC chip 254 . can be enabled and data characterizing the sample can be output to microcontroller 266 .

Also, the hardware leaf timers generated by hardware clock controls 268 and 270 can be used for a variety of different operations that require mutual coordination between master IC chip 252 and slave IC chip 254 . Such operations may include enabling/disabling various RF receiving and/or RF transmitting circuits (or other circuits). Such operations also include initiation of nearly all radar operations such as radar chirp frequency generation, chirp generation/transmission, digital processing of ADC outputs (by microcontrollers 264 and 266 or external circuitry), and/or RF transmission. and/or radar chirp-tuned signal generation, such as RF receiver circuit power control. For example, power control may set the RF transmit and/or RF receive circuitry to a high performance, high power state during a radar chirp and to a low performance, low power state after the radar chirp ends.

Modifications in the described embodiments are possible and other embodiments are possible within the scope of the claims.

Claims (14)

An integrated circuit (IC) chip,
a sync input terminal;
a root timer that generates a frame pulse based on the start trigger signal;
a hardware clock controller for providing a clock signal based on a selected one of said frame pulse and a synchronization signal provided to said synchronization input terminal ,
a clock selector having a first input coupled to the root timer output, a second input coupled to the synchronization input terminal, and an output;
a circuit element having an input coupled to the output of the clock selector and an output configured to output the clock signal;
the hardware clock controller comprising:
a plurality of analog-to-digital converters (ADCs) coupled to outputs of said circuit element, each of said plurality of ADCs for each one of a plurality of radio frequency (RF) receivers based on said clock signal; the plurality of ADCs configured to sample outputs;
An IC chip, including The IC chip according to claim 1,
further comprising a microcontroller controlling timing of software operations based on the frame pulse provided from the root timer;
An IC chip wherein operations controlled by said clock signal provided by said hardware clock controller are synchronized within a tight window and said software operations are synchronized within a loose window. The IC chip according to claim 2,
The IC chip, wherein the software operations include one or more of calibration and built-in self-test (BIST) for one or more of the plurality of RF transmitters and the plurality of RF receivers. The IC chip according to claim 3,
The IC chip, wherein the software operation further includes radar chirp. The IC chip according to claim 1,
The IC chip, wherein the root timer generates the synchronization signal, the synchronization signal being provided to a synchronization output terminal of the IC chip. The IC chip according to claim 5,
further comprising a trigger selector that selects the synchronization signal to provide the start trigger signal;
An IC chip, wherein the synchronization signal is fed back to the synchronization input terminal through the synchronization output terminal . The IC chip according to claim 1,
said clock selector selecting between said frame pulse and said synchronization signal to generate a start clock signal;
the hardware clock controller
an ADC clock generator that generates the clock signal for the hardware clock controller for the plurality of ADCs;
a hardware leaf timer that generates a stop clock signal based on the frame pulse;
a synchronization gate that outputs the clock signal based on the start clock signal from the clock selector and the stop clock signal from the hardware leaf timer;
An IC chip, further comprising: The IC chip according to claim 7,
An IC chip, wherein the synchronization gate includes one or more digital logic gates that output the clock signal from the ADC clock generator to the ADC based on the start clock signal and the stop clock signal. The IC chip according to claim 7,
further comprising a trigger selector that selects between the synchronization signal and a software trigger to provide the start trigger signal;
An IC chip, wherein the clock selector and the trigger selector are controlled based on a mode selection signal that sets an operation mode of the IC chip. The IC chip according to claim 9,
An IC chip, wherein the mode of operation of the IC chip is one of a single mode, a master mode, and a slave mode. The IC chip according to claim 10,
An IC chip wherein, in response to said IC chip operating in said slave mode, said trigger selector selects a synchronization signal received from another IC chip and provides said synchronization signal as said start trigger signal . The IC chip according to claim 1,
An IC chip further comprising a microcontroller for analyzing data output by each of said plurality of ADCs to facilitate object detection. The IC chip according to claim 1,
a plurality of transmitters that output RF signals;
a plurality of receivers;
further comprising
An IC chip, wherein said hardware clock controller provides said clock signal to control operation of each of said transmitter and said receiver. 14. The IC chip according to claim 13,
the hardware clock controller
enabling and disabling the plurality of transmitters and the plurality of receivers; radar chirp frequency generation and/or transmission; radar chirp-tuned signal generation; and digital processing of the outputs of the plurality of ADCs. The IC chip further including a hardware leaf timer that controls at least one timing.

Images