CN117674990A - Firmware testing method and system - Google Patents

Abstract

The invention relates to the technical field of communication, and provides a firmware testing method and a firmware testing system. Wherein the method comprises: acquiring digital waveforms of corresponding pins in the firmware according to the test items of the firmware; scaling the digital waveform to find data to be analyzed in the digital waveform; analyzing the data to be analyzed to obtain a test result of the test item. The invention obtains the waveform of the firmware pin, and carries out calibration analysis on the waveform to obtain the test result of the test item, thereby eliminating the need of manually analyzing the waveform, improving the reliability of firmware test and reducing the occupation of human resources.

Description

Firmware testing method and system

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a firmware testing method and system.

Background

The firmware is the nerve center of the optical module, and the optical module realizes the control of the internal chip and the mutual communication with the external main board through the firmware. With the increasing demand of people for downloading rate, wireless communication increasingly depends on optical fiber communication, and as part of the development of the 5G age, optical modules are used as core components in base stations and transmission equipment, and the performance requirements of the optical modules are also increasing.

In the research and development field of the optical module, firmware testing of the optical module is indispensable, at present, research and development personnel can only manually test, test projects are more, and data of the test projects need to be manually analyzed, so that a test result can be obtained, for example, in the prior art, firmware pin waveforms are usually obtained through an oscilloscope, and then the waveforms are analyzed by a person in the field to obtain a final result, so that the time consumption is long, the reliability of manual operation testing depends on personal experience, and the method is not suitable for firmware testing in mass production.

In view of this, overcoming the drawbacks of the prior art is a problem to be solved in the art.

Disclosure of Invention

The invention aims to solve the technical problems that the existing firmware test still needs to manually analyze waveforms, the process is complicated, and the efficiency of the firmware test is affected.

In a first aspect, the present invention provides a firmware testing method, including:

acquiring digital waveforms of corresponding pins in the firmware according to the test items of the firmware;

scaling the digital waveform to find data to be analyzed in the digital waveform;

analyzing the data to be analyzed to obtain a test result of the test item.

Preferably, the acquiring the digital waveform of the corresponding pin in the firmware specifically includes:

acquiring an analog waveform of the pin by using an oscilloscope;

converting the analog waveform into a digital waveform according to the coordinate parameters of the analog waveform; the digital waveform comprises a plurality of data, the data are arranged according to the signal output time sequence of the pins, and each data represents the signal size of the pins at different times.

Preferably, the converting the analog waveform into a digital waveform according to the coordinate parameters of the analog waveform specifically includes:

according to the ordinate zero position, the ordinate offset and the ordinate coefficient in the coordinate parameters, converting the ordinate value in the analog waveform into an analog ordinate value;

the analog ordinate values are converted to corresponding digital signal magnitudes, thereby generating a digital waveform.

Preferably, the scaling the digital waveform to find the data to be analyzed in the digital waveform specifically includes:

and finding out the rising edge and/or the falling edge in the digital waveform, and determining corresponding data to be analyzed according to the rising edge and/or the falling edge.

Preferably, the finding the rising edge and/or the falling edge in the digital waveform specifically includes:

judging whether the difference value between the first data and the previous piece of data in the digital waveform is larger than a first preset difference value, if the difference value is larger than the first preset difference value, selecting a preset number of second data after the first data, and judging whether the difference value between the first data and each piece of second data is smaller than a second preset difference value;

if the difference value between the first data and each second data is smaller than the second preset difference value, and the values of the first data and the second data are larger than the value of the previous data, a rising edge of the digital waveform exists between the first data and the previous data;

if the difference value between the first data and each second data is smaller than the second preset difference value, and the value of the first data and the value of the second data are smaller than the value of the previous data, a falling edge of the digital waveform exists between the first data and the previous data;

otherwise, there is neither a rising nor a falling edge between the first data and the previous piece of data.

Preferably, the analyzing the data to be analyzed to obtain a test result of the test item specifically includes:

comparing the data to be analyzed with preset waveform data, analyzing the difference between the data to be analyzed and the preset waveform data, and if the difference is smaller than a preset difference threshold, enabling the test item to be normal;

or comparing the data to be analyzed in the digital waveforms of the plurality of pins in the firmware, and analyzing and obtaining the test result of the test item according to the preset relation among the digital waveforms of the plurality of pins.

Preferably, when the firmware is an OLT device and the test item is an RxSD signal, a digital waveform of a detection signal of the OLT device, a digital waveform of a RESET signal of the OLT device, and a digital waveform of the RxSD signal of the OLT device are obtained;

acquiring a first time delay between a falling edge of the RxSD signal and a rising edge of the RESET signal, and a second time delay between the rising edge of the RxSD signal and the first rising edge of the detection signal; wherein a first rising edge of the probe signal is a first rising edge generated after a falling edge of the RESET signal;

Judging whether the first time delay is smaller than a first preset time delay threshold value or not, and judging whether the second time delay is smaller than a second preset time delay threshold value or not;

if the first time delay is smaller than a first preset time delay threshold and the second time delay is smaller than a second preset time delay threshold, the RxSD signal test item of the firmware is normal.

Preferably, the method further comprises: the same test items of multiple firmware are tested, specifically,

after the last calibration and analysis process is finished, selecting one firmware from a plurality of firmware which does not obtain a test result as a first firmware of the next time, and taking other firmware which does not obtain the test result as a second firmware of the next time, and performing the next calibration and analysis process until test results of test items of all the firmware are obtained; in the first calibration and analysis process, one firmware is selected from all the firmware to be used as a first firmware, and the other firmware is selected to be used as a second firmware;

the calibration and analysis process specifically comprises the steps of calibrating a first firmware, finding data to be analyzed of the first firmware, and analyzing and obtaining a test result of a test item of the first firmware;

if the test item of the first firmware obtained by analysis is normal, a calibration interval is generated by taking the signal output time of the data to be analyzed of the first firmware as an interval center and taking the preset time as an interval size, and the data to be analyzed of the second firmware is searched in the calibration interval;

If the data to be analyzed of the second firmware is obtained in the calibration interval, analyzing the data to be analyzed of the second firmware to obtain a test result of a test item of the second firmware;

if the data to be analyzed of the second firmware is not found in the calibration interval, the test item of the second firmware is abnormal;

if the test item of the first firmware is abnormal, the test result of the test item of the second firmware cannot be obtained, and the second firmware is reserved to the next calibration and analysis process.

In a second aspect, the invention provides a firmware testing system, which comprises a waveform acquisition module and an analysis module;

the waveform acquisition module is used for acquiring digital waveforms of corresponding pins in the firmware according to the test items of the firmware;

the analysis module is used for scaling the digital waveform to find out data to be analyzed in the digital waveform, analyzing the data to be analyzed and obtaining a test result of the test item.

Preferably, the system further comprises a power supply module and a control module;

the power supply module is used for providing working power supply for the firmware;

the control module is used for providing corresponding input signals for the firmware, so that the working state of the firmware meets the test conditions.

In a third aspect, the present invention further provides a firmware testing apparatus, configured to implement the firmware testing method described in the first aspect, where the apparatus includes:

at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor for performing the firmware test method of the first aspect.

In a fourth aspect, the present invention also provides a non-volatile computer storage medium storing computer executable instructions for execution by one or more processors to perform the firmware testing method of the first aspect.

According to the invention, the waveform of the firmware pin is obtained, and the waveform is subjected to calibration analysis, so that the test result of the test item is obtained, the waveform is not required to be manually analyzed, the reliability of firmware test is improved, and the occupation of human resources is reduced.

Drawings

In order to more clearly illustrate the technical solution of the embodiments of the present invention, the drawings that are required to be used in the embodiments of the present invention will be briefly described below. It is evident that the drawings described below are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a flow chart of a firmware testing method according to an embodiment of the present invention;

FIG. 2 is a flowchart of a firmware testing method according to an embodiment of the present invention;

FIG. 3 is a flowchart of a firmware testing method according to an embodiment of the present invention;

fig. 4 is a schematic diagram of an OLT apparatus pin waveform according to an embodiment of the present invention;

fig. 5 is a schematic diagram of an OLT apparatus pin waveform according to an embodiment of the present invention;

FIG. 6 is a flowchart of a firmware testing method according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a firmware testing system according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a firmware testing system according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a firmware test system according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a firmware test system according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of a firmware test system according to an embodiment of the present invention;

FIG. 12 is a schematic diagram of a portion of a device of a firmware test system according to an embodiment of the present invention;

FIG. 13 is a schematic diagram of a user interface in a firmware testing system according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of a user interface in a firmware testing system according to an embodiment of the present invention;

fig. 15 is a schematic diagram of a firmware testing apparatus according to an embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

In the description of the present invention, the terms "inner", "outer", "longitudinal", "transverse", "upper", "lower", "top", "bottom", etc. refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of describing the present invention and do not require that the present invention must be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.

In addition, the technical features of the embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.

Example 1:

an embodiment 1 of the present invention provides a firmware testing method, as shown in fig. 1, including:

In step 201, a digital waveform of a corresponding pin in firmware is obtained according to a test item of firmware.

In step 202, the digital waveform is scaled to find data to be analyzed in the digital waveform.

In step 203, the data to be analyzed is analyzed, and a test result of the test item is obtained.

The pins required to acquire the digital waveforms or the data to be analyzed to be found may be different for different firmware or different test items, and in some test items, the digital waveforms of a plurality of pins may also need to be acquired. The pins may be external pins of the firmware, such as output pins or input pins, or internal pins of the firmware, such as pins through which a certain signal is transmitted inside the firmware.

The analyzing the data to be analyzed, and obtaining the test result of the test item comprises the following steps: and analyzing whether the value of the data to be analyzed accords with the expectation or not, and analyzing whether the arrival time of the data to be analyzed accords with the expectation or not.

In the usual case, the data to be analyzed is typically the rising or falling edge of a digital waveform.

According to the embodiment, the waveform of the firmware pin is obtained, and scaling analysis is carried out on the waveform to obtain the test result of the test item, so that manual analysis of the waveform is not needed, the reliability of firmware test is improved, and the occupation of human resources is reduced.

In practical implementation, the most commonly used method for acquiring waveforms is to acquire waveforms by using an oscilloscope, but waveforms acquired by using an oscilloscope are usually processed by using corresponding coordinate parameters, so that analog waveforms for screen display are convenient to calculate, and because analog signals usually involve the introduction of noise at a joint, the analog waveforms are not easy to calculate, and in this case, the analog waveforms are converted into digital waveforms to calculate, so that, in combination with the above embodiment, there are the following preferred implementation manners, namely, the acquisition of digital waveforms of corresponding pins in firmware, as shown in fig. 2, specifically including:

in step 301, an oscilloscope is used to acquire an analog waveform of the pin.

In step 302, converting the analog waveform into a digital waveform according to the coordinate parameters of the analog waveform; the digital waveform comprises a plurality of data, the data are arranged according to the signal output time sequence of the pins, and each data represents the signal size of the pins at different times.

The most common means for converting the analog waveform into a digital waveform is to round up the analog waveform data and convert the analog waveform data into corresponding integer data, and there is an optional embodiment that: presetting a plurality of interval ranges and values corresponding to each interval range, and finding out the corresponding values as digital waveform data according to the interval range in which the analog waveform data are located.

The digital waveform may be presented in the form of an array of data, the order in which the data is arranged in the array representing the time at which the data was generated.

The converting the analog waveform into a digital waveform according to the coordinate parameters of the analog waveform specifically includes:

and converting the ordinate value in the analog waveform into an analog ordinate value according to the ordinate zero position, the ordinate offset and the ordinate coefficient in the coordinate parameter.

The analog ordinate values are converted to corresponding digital signal magnitudes, thereby generating a digital waveform.

Wherein the coordinate parameters include: the waveform is located at an abscissa zero position Xzero, an abscissa offset XOffset, an abscissa coefficient XInc, an ordinate zero position Yzero, an ordinate offset YOffset, and an ordinate slope YMULT.

When the waveform data obtained from the oscilloscope is denoted as a and the analog data to be obtained is denoted as B, the analog ordinate value can be calculated from b= (a-YOffset) ×ymult+yzero.

The time interval between every two adjacent waveform data can also be acquired by the abscissa zero position XZero, the abscissa offset XOffset, and the abscissa coefficient XInc, and the generation timing of each waveform data can also be acquired.

The scaling the digital waveform to find the data to be analyzed in the digital waveform, specifically comprising:

and finding out the rising edge and/or the falling edge in the digital waveform, and determining corresponding data to be analyzed according to the rising edge and/or the falling edge.

Typically, the data to be analyzed is a rising or falling edge, and in some cases, it is also possible that the data to be analyzed is high or low level data between the rising and falling edges.

Depending on the oscilloscope sampling frequency and the signal frequency of the firmware pins, the rising and falling edges of the corresponding waveforms may be presented as distinct from the high and low level data, e.g., by analyzing the data, it is found that the data representing the high level is 3, the data representing the low level is 0, and the level of the rising or falling edge is 1 or 2.

Or the rising and falling edges of the corresponding waveforms represent a switching change between high level data and low level data without being represented by specific data, such as 3 for high level data, 0 for low level data, 3 for corresponding data, and 0 for the previous data; the falling edge appears with the corresponding data being 0 and its previous data being 3.

In the digital waveform, there may be a burr that affects the positioning of the data to be analyzed, and for this case, when the rising edge and the falling edge are presented with data different from the high level and the low level, the following will specifically describe, by way of example, the finding of the rising edge and/or the falling edge in the digital waveform, for example:

searching the acquired data one by one, when the continuous 10 data are more than or equal to 3 and the following 5 data are less than 3, marking the first data which are not 3 as a first falling edge starting point, recording the offset address of the number, and then continuing searching until the waveform data are finished, and recording all falling edge starting point offset addresses.

Falling edge endpoint: i.e., the position where the intermediate level drops to the low level, undershoot may occur at the position of the transition, and thus, where the intermediate level drops to the low level, the data should be 0 or less. Searching the acquired data one by one, when the continuous 5 data are more than or equal to 2 and the following 5 data are less than or equal to 0, recording the first data which are less than or equal to 0 as a first falling edge end point, recording the offset address of the number, and then continuing searching until the waveform data are finished, and recording all the falling edge end point offset addresses.

Rising edge starting point: that is, since undershoot generally occurs at the position of the transition where the low level starts to rise, the data of the low level is 0% or less. Searching the acquired data one by one, when the continuous 5 data are smaller than or equal to 0 and the following 5 data are larger than 0, recording the first data larger than 0 as the starting point of the first rising edge, recording the offset address of the number, and then continuing searching until the waveform data are finished, and recording all the rising edge starting point offset addresses.

Rising edge endpoint: that is, where the intermediate level is shifted to the high level, the position of the transition may be overshot, and thus it is necessary to consider that the data of the high level should be 3 or more. Searching the acquired data one by one, when the continuous 5 data are smaller than 3 and the following 5 data are larger than or equal to 3, recording the first data which are equal to 3 as the end point of the first rising edge, recording the offset address of the number, and then continuing searching until the waveform data are finished, and recording all the end point offset addresses of the rising edge. Thereby finding all rising and falling edges in the digital waveform.

When the rising edge and the falling edge in the digital waveform show a switching change between high level data and low level data, in order to remove the influence of the glitch, there are preferred embodiments in which the finding of the rising edge and/or the falling edge in the digital waveform specifically includes:

Judging whether the difference value between the first data and the previous data in the digital waveform is larger than a first preset difference value, if the difference value is larger than the first preset difference value, selecting a preset number of second data after the first data, and judging whether the difference value between the first data and each second data is smaller than a second preset difference value.

If the difference between the first data and each second data is smaller than the second preset difference, and the values of the first data and the second data are larger than the value of the previous data, a rising edge of the digital waveform exists between the first data and the previous data.

And if the difference value between the first data and each piece of second data is smaller than the second preset difference value, and the value of the first data and the value of the second data are smaller than the value of the previous piece of data, a falling edge of the digital waveform exists between the first data and the previous piece of data.

Otherwise, there is neither a rising nor a falling edge between the first data and the previous piece of data.

Wherein the first data does not refer to a specific data, but refers to data in the digital waveform.

The first preset difference value, the second preset difference value and the preset number are obtained by analysis of a change rule of signals of the firmware pins by a person skilled in the art.

When the difference between the first data and the previous data is larger than a first preset difference, the first data is indicated to have data change compared with the previous data, and the first data can be the first data after rising edge, the first data after falling edge or burrs; when the difference between the first data and each second data is smaller than the second preset difference, the first data can be maintained for a certain time, namely, the first data does not belong to burrs, so that rising edges or falling edges exist between the first data and the second data, and when the rising edges or the falling edges are used as data to be analyzed for waveform time delay analysis, the time interval between the first data and the corresponding rising edges or falling edges is quite small, and the time interval is negligible in the time delay analysis, so that the first data can be directly used as the rising edges or the falling edges.

The analyzing the data to be analyzed to obtain the test result of the test item specifically comprises the following steps:

comparing the data to be analyzed with preset waveform data, analyzing the difference between the data to be analyzed and the preset waveform data, and if the difference is smaller than a preset difference threshold, the test item is normal.

Or comparing the data to be analyzed in the digital waveforms of the plurality of pins in the firmware, and analyzing and obtaining the test result of the test item according to the preset relation among the digital waveforms of the plurality of pins.

The preset difference threshold is obtained by analysis of a change rule of a signal of the firmware pin by a person skilled in the art.

As a preferred implementation, the size of the difference from the preset waveform data includes: the magnitude of the difference from the value of the preset waveform data and the magnitude of the time difference from the arrival time of the preset waveform data, so that the test item can be judged in terms of both the magnitude of the waveform value and the time delay of the waveform.

Aiming at comparing the data to be analyzed in the digital waveforms of the plurality of pins in the firmware in the above embodiment, the embodiment also provides a specific implementation for a specific implementation scenario, which specifically includes:

and when the firmware is an OLT device (Optical Line Terminal, an optical line terminal) and the test item is an RxSD signal, acquiring a digital waveform of a detection signal of the OLT device, a digital waveform of a RESET signal of the OLT device and a digital waveform of the RxSD signal of the OLT device.

Acquiring a first time delay between a falling edge of the RxSD signal and a rising edge of the RESET signal, and a second time delay between the rising edge of the RxSD signal and the first rising edge of the detection signal; wherein a first rising edge of the probe signal is a first rising edge generated after a falling edge of the RESET signal.

Judging whether the first time delay is smaller than a first preset time delay threshold value or not, and judging whether the second time delay is smaller than a second preset time delay threshold value or not.

If the first time delay is smaller than a first preset time delay threshold and the second time delay is smaller than a second preset time delay threshold, the RxSD signal test item of the firmware is normal.

Otherwise, the RxSD signal test item of the firmware is abnormal.

In the firmware that works normally, the RESET signal, the RxSD signal, and the probe signal need to satisfy the following relationships:

when the rising edge of the RESET signal arrives, the RxSD signal jumps to a low level, and when the falling edge of the RESET signal arrives, the RESET signal is recovered from a high level to a low level, and then the RxSD signal needs to respond to the rising edge of the detection signal in real time and jump from the low level to the high level.

The first preset time delay threshold and the second preset time delay threshold are obtained by analysis of performance index requirements of the OLT equipment by a person skilled in the art.

The firmware test is usually performed before leaving the factory after the firmware is manufactured, so as to ensure that the function of the firmware leaving the factory is normal, and in the actual production process, the firmware is usually produced in batch and in large quantity, in this case, a great amount of time is required for testing each firmware one by one, and in view of this problem, the following preferred embodiments are provided in combination with the above embodiments, namely, the method further includes: testing the same test items of a plurality of firmware, specifically:

after the last calibration and analysis process is finished, selecting one firmware from a plurality of firmware which does not obtain a test result as a first firmware of the next time, and taking other firmware which does not obtain the test result as a second firmware of the next time, and performing the next calibration and analysis process until test results of test items of all the firmware are obtained; in the first calibration and analysis process, one firmware is selected from all the firmware to be used as a first firmware, and the other firmware is selected to be used as a second firmware; wherein, the scaling and analyzing process is shown in fig. 3, and specifically comprises the following steps:

in step 401, the first firmware is scaled, data to be analyzed of the first firmware is found, and a test result of a test item of the first firmware is obtained through analysis.

In step 402, if the test item of the first firmware obtained by analysis is normal, a calibration interval is generated by taking the signal output time of the data to be analyzed of the first firmware as the interval center and taking the preset time as the interval size, and the data to be analyzed of the second firmware is searched in the calibration interval.

In step 403, if the data to be analyzed of the second firmware is found in the calibration interval, the data to be analyzed of the second firmware is analyzed, and a test result of the test item of the second firmware is obtained.

In step 404, if the data to be analyzed of the second firmware is not found in the calibration interval, the test item of the second firmware is abnormal.

In step 405, if the test item of the first firmware is abnormal, the test result of the test item of the second firmware cannot be obtained, and the second firmware is retained to the next calibration and analysis process.

It should be noted that, the "last" and "next" described in this embodiment are relative to two adjacent alignment processes, for example, three calibration and analysis processes have been performed by a certain time, and for convenience of description, these three alignments are referred to as in time sequence: the first scale analysis, the second scale analysis and the third scale analysis, the first scale analysis is the "last time" of the second scale analysis, the second scale analysis is the "next time" of the first scale analysis, the second scale analysis is the "last time" of the third scale analysis, and the third scale analysis is the "next time" of the second scale analysis.

The first firmware can be any one selected from a plurality of firmware which does not obtain a test result, or can be selected as the first firmware according to the test result of a plurality of test items obtained by history, and the firmware with the largest number of the test items is selected as the second firmware, and the corresponding firmware which does not obtain the test result except the first firmware is selected as the second firmware.

The preset time is obtained by analysis of a change rule of a signal of the firmware pin by a person skilled in the art.

The plurality of firmware has the same function, namely, under the condition that the plurality of firmware is normal, the signals of corresponding pins are synchronous to respond under the same working environment.

Meanwhile, in the case that the plurality of firmware has demands on the working environment, the same working environment is synchronously provided for the plurality of firmware, for example: and providing a no-light environment or a light environment for the plurality of OLT devices synchronously so as to trigger the plurality of OLT devices to synchronously generate detection signals of burst receiving light.

Since the signals between the plurality of firmware should respond synchronously, the positions of the data to be analyzed of the plurality of firmware should be similar, so that the possible interval of the data to be analyzed of the second firmware can be presumed through the data to be analyzed of the first firmware.

When the test item of the first firmware is normal and the data to be analyzed of the second firmware cannot be found in the calibration interval, the waveform of the second firmware is not synchronous with the first firmware, and the abnormal test item of the second firmware can be directly deduced.

When the test item of the first firmware is normal and the data to be analyzed of the second firmware can be found in the calibration interval, the range of the calibration data interval of the second firmware can be reduced through the first firmware, so that the time required by multi-firmware calibration and the resources occupied by calibration are shortened, and the data to be analyzed of the second firmware is directly analyzed.

When the test item of the first firmware is abnormal, the position of the data to be analyzed of the first firmware does not have reference significance, so that the next calibration and analysis process is performed by selecting a new first firmware.

According to the preferred embodiment, the range of the calibration interval can be shortened by taking one firmware as a reference, so that time and resource occupation required by calibration are saved, and when a firmware test item serving as the reference is normal, test results of abnormal test items can be directly obtained for other firmware incapable of finding data to be analyzed, calibration and analysis of the firmware are not needed again, so that the resource occupation is further saved and the test time is shortened in a large-batch firmware test environment.

In the embodiments of the present invention, the first, second, etc. are not meant to be specific sequential meanings, but are merely defined for convenience in describing two or more different objects in the same class and should not be construed to further limit the meaning.

Example 2:

the invention is based on the method described in embodiment 1, and combines specific application scenes, and the implementation process in the characteristic scene of the invention is described by means of technical expression in the relevant scene.

For example, some internal pins in the OLT device are an RxSD signal pin, a RESET signal pin, and a probe signal pin, where the probe signal is generated by receiving burst light by the OLT device, the RESET signal may generate pulses in a non-light protection time, as shown in fig. 4, or may generate pulses in a light preamble time, as shown in fig. 5, where in both cases, the RxSD signal needs to respond to a rising edge of the RESET signal in real time, and generate a corresponding falling edge, and a time delay between the two needs to be less than 50ns. After the RESET signal is restored to a low level, the RxSD signal also needs to respond to the detection signal of the burst received light in real time, and a corresponding rising edge is generated when light exists, and similarly, the time delay between the two signals needs to be less than 50ns. I.e. t1, t2 as in fig. 4 and 5, are each less than 50ns.

Taking the RxSD signal as a test item, testing a plurality of OLT devices, as shown in fig. 6, specifically includes:

in step 501, the plurality of OLT apparatuses are switched synchronously in the light environment and the no light environment, and pulse input is provided for the RESET signal pins of the plurality of OLT apparatuses synchronously in the no light environment, or pulse input is provided for the RESET signal pins of the plurality of OLT apparatuses synchronously in the preamble time when light exists. And acquiring digital waveforms of detection signals of the plurality of OLT devices, digital waveforms of RESET signals of the plurality of OLT devices and digital waveforms of RxSD signals of the plurality of OLT devices.

In step 502, one of the OLT apparatuses is selected as a first OLT apparatus, and the other apparatuses are selected as second OLT apparatuses.

In step 503, the first OLT device is found to correspond to the rising edge of the RESET signal, the rising edge of the probe signal, and the rising and falling edges of the RxSD signal. Acquiring a first time delay between a falling edge of the RxSD signal and a rising edge of the RESET signal, and a second time delay between the rising edge of the RxSD signal and the rising edge of the detection signal; the detection signal has a plurality of rising edges, and after the RESET signal is recovered to a low level, the first rising edge found participates in the subsequent step.

In step 504, it is determined whether the first delay is less than a first predetermined delay threshold, and whether the second delay is less than a second predetermined delay threshold; if the first time delay is smaller than the first preset time delay and the second time delay is smaller than the second preset time delay, the RxSD signal test item of the firmware is normal, and step 505 is entered; otherwise, the RxSD signal test item of the first OLT apparatus is abnormal, and step 507 is entered.

In step 505, the output time corresponding to the rising edge of the RxSD signal of the first OLT apparatus is taken as the first time, a first calibration interval is formed from the first 50ns of the first time to the last 50ns of the first time, and the rising edge of the RxSD signal of the second OLT apparatus is searched in the first calibration interval.

And forming a second scaling interval by taking the output time corresponding to the falling edge of the RxSD signal of the first OLT equipment as a second time and taking the first 50ns of the second time to the last 50ns of the second time, and searching the falling edge of the RxSD signal of the second OLT equipment in the second scaling interval.

In step 506, if the rising edge of the RxSD signal of the second OLT device cannot be found in the first calibration interval or the falling edge of the RxSD signal of the second OLT device cannot be found in the second calibration interval, the RxSD signal test item of the second OLT device is abnormal; otherwise, acquiring a third time delay between a falling edge of the RxSD signal of the second OLT device and a rising edge of the RESET signal, and a fourth time delay between the rising edge of the RxSD signal of the second OLT device and the rising edge of the detection signal; according to the third time delay and the fourth time delay, the test result of the RxSD signal test item of the second device is obtained, and the implementation of the method in step 504 are based on the same concept and are not described herein.

In step 507, if there is an OLT device that does not obtain a test result among the plurality of OLT devices, selecting one OLT device that does not obtain a test result as a first OLT device, and other OLT devices that do not obtain a test result as second OLT devices, and entering step 503; if all the OLT devices obtain the test result, ending the flow and entering the next test item.

In the embodiments of the present invention, the first, second, etc. are not meant to be specific sequential meanings, but are merely defined for convenience in describing two or more different objects in the same class and should not be construed to further limit the meaning.

In the present invention, the expression similar to "a and/or B" means that the implementation manner may be implemented in a manner of taking a as an object, or in a manner of taking B as an object, or in a manner of taking a combination of a and B as an object, and in which a and B may be replaced by specific subject name objects according to requirements of a specific description scenario.

Example 3:

after providing a firmware testing method described in embodiment 1 and embodiment 2, the embodiment of the present invention further provides a firmware testing system, so as to make relevant explanation on the hardware implementation angles of the corresponding methods in embodiment 1 and embodiment 2, and make relevant deep analysis on the design principles thereof. It should be noted that the methods in embodiment 1 and embodiment 2 are applicable to embodiment 3, and will not be described in detail in this embodiment.

As shown in fig. 7, the system includes a waveform acquisition module and an analysis module.

The waveform acquisition module is used for acquiring digital waveforms of corresponding pins in the firmware according to test items of the firmware.

The analysis module is used for scaling the digital waveform to find out data to be analyzed in the digital waveform, analyzing the data to be analyzed and obtaining a test result of the test item.

As a preferred implementation, the system further comprises a power supply module and a control module, as shown in fig. 8.

The power supply module is used for providing working power supply for the firmware.

The control module is used for providing corresponding input signals for the firmware, so that the working state of the firmware meets the test conditions.

Corresponding to the modules in the above system, the embodiment also provides implementation of specific devices of the above system, as shown in fig. 9, specifically including: oscilloscope, branching unit, communication box, power supply, test computer and test board; the test computer is connected to the test board through a serial port, not shown in fig. 9, the splitter is shown as a device in fig. 9 that is in communication with the firmware to be tested and the oscilloscope, and the communication box is shown as a small red box (commonly expressed by those skilled in the art) in fig. 9.

The splitter, the oscilloscope and the test computer together realize the function of the waveform acquisition module, the test computer and the test board jointly form the analysis module, the communication box is equivalent to the control module, and the power supply is equivalent to the power supply module.

The test board supports multiple optical module connectors, different test channels are selected according to different types of optical modules, firmware test items of the optical modules can be configured through the software platform, test results are recorded in real time in the test process, and a test report is automatically generated after the test is completed so as to realize automatic test of the optical module firmware. As shown in fig. 10 and 11, the system may further include an optical power meter and/or an attenuator to perform corresponding tests on firmware having an optical transmitting or receiving function. In the following text of the embodiment, the specific devices are used to replace the functional modules for explanation, and in the following text of the embodiment, the optical power meter, the attenuator and the oscilloscope are collectively referred to as a meter.

Some optional device type selection parameters are also provided herein, such as using a texas oscilloscope DPO2024, MDO3034; self-made attenuators or multiple attenuators such as EXFO, AQ and the like; self-made power meter or pm-1600 power meter; the power supply can be an ITECH voltage source.

Fig. 10 is mainly used for I2C timing test, the module to be tested is self-looped, and two probes of the oscilloscope are connected with SCL and SDA to capture timing waveforms.

Fig. 9 and 11 are mainly used for photoelectric time sequence test, the transmitting end of the module is connected with an oscilloscope optical probe, and the optical signal of the optical module is captured; the hardware control pin is used for externally giving an electric signal to the pin of the module, and the test module is turned off from electricity to light in response time sequence, such as light; the software state pin is used for reflecting the completion of the software issuing instruction and testing the time sequence of the upper computer control optical module; fig. 3 is mainly used for the timing of the status indication, such as LOS, generated by the module after the optical signal is changed.

As shown in fig. 12, according to different package structures of the optical modules, multiple golden finger connectors are provided on the test board, so that different types of optical modules can be tested on the test board, and each type of optical module is not required to be provided with one test board. According to different connector definitions, various signal detection points, such as LOS, TXDIS, VCC, are led out from the test board and used for testing the time sequence of the electric signals.

The system supports testing a plurality of test items, and the required test items can be configured by a person skilled in the art, so that the execution sequence of the test items can be adjusted arbitrarily. And part of test items can be selected to be tested, the selected test items are tested in sequence, and the test failure record result and state are recorded, so that the subsequent analysis is convenient, the test cannot be stopped because the test items fail in the test process, and the test can be continuously executed unless the instrument control fails. Thus, the method is favorable for testing the reliability of excessive test items or long time, and realizes unattended automatic test. After the test results of the corresponding test items are obtained, a test report is automatically generated according to the test report template, and the test results and pictures are automatically stored in the report for the person skilled in the art to analyze the finally generated report.

Before testing, the test computer sends a polling command to the test board to acquire the in-place condition of the module on the test board, so as to determine the test channel and the test protocol specification. The required meters are initialized and configured, and the same type of meters can support subsequent expansion. For oscilloscopes, a detailed configuration is required: the different electric probes of the oscilloscope are connected to different signal pins, a communication box or a test computer is used for carrying out targeted configuration on corresponding oscilloscope channels according to each configured signal pin, such as a display voltage range, a channel position, a horizontal display interval, a horizontal delay, a bus analysis channel, a trigger voltage, a trigger starting point and the like under a certain channel. After a series of columns, the test items selected by the user are decomposed.

At present, 10 major classes and more than 50 tests are supported, and the overall selection of the major classes can be supported and also can be selected in terms. After all the options are acquired, the test items of the same type are automatically screened and are gathered together to form a queue, and the test items of different types are arranged at the back, so that redundant configuration before the test of the same type is reduced. The execution order of the test items may also be determined by the user himself. And after the test items are screened, the interactive interface pops up a dialog box to prompt a user to carry out the supplementary configuration of the test standard and the module information, thereby facilitating the subsequent test execution and the judgment of the result.

When testing is carried out, after the test items forming the queue are obtained, the total number of the test items is recorded, each test item is carried out one by one in a queue mode, the corresponding test item sub-software is called, and a sub-software interface shown in figure 13 is presented on a test computer.

Judging whether the instrument needs to be reconfigured or not, if so, directly performing subsequent tests, and if not, needing to be reconfigured. The method is characterized by comprising the steps of firstly, transferring module information and test standards to a subroutine, and then transferring the information to the subroutine to facilitate the call of the subsequent test. In the test process, when the instrument cannot execute, the current test is immediately terminated and is transmitted to the main program, the occurrence of instrument errors is informed, and the main program is stopped. And when the instrument control is normal, recording the required data in the test process, and storing a corresponding oscilloscope memory. After the test is completed, the numerical value of the test result is judged according to the test standard, the judged result is transmitted to the main program, the main program displays the result of PASS/FAIL on the test item according to the result, the current sub-software interface is closed, the test item is completed, one item is subtracted from the total test item number, the next test item is started, and the cycle is performed until all the test items are completed, the whole test process is finished, and the interactive interface shown in figure 14 is displayed.

The oscilloscope test results are obtained in two ways: one is to directly send the data acquisition instruction, and can directly acquire the test result; the other is to perform comprehensive analysis and processing on the waveform data, and obtain the final result after finding the position to be tested. The second way of obtaining data will be described in detail below.

In firmware testing, many test results cannot be directly obtained from an oscilloscope, such as a certain section of data in a waveform diagram, so that the conventional test method is to manually calibrate, manually find the position and then continue recording, and the efficiency is quite low. To address this problem, first, analog waveform data on an oscilloscope is converted into a data array: selecting a waveform channel, acquiring an oscilloscope sampling type, acquiring various position parameters of a waveform, setting the width of data, acquiring waveform data, performing calculation processing on the data and various coordinate parameters, and outputting a result, wherein the various position parameters of the acquired waveform comprise: the waveform data obtained from the oscilloscope is marked as A, the visual data needed to be obtained is marked as B, B= (A-Yoffset) YMULTI+Yzero, and B is converted into integer data, so that an array of integers can be obtained, however, the position needed to be measured, such as a certain rising edge of the waveform, is found from the array, and further processing is needed. By analysing the data we have found that the data representing the high level is 3, the data representing the low level is 0, the level of the rising or falling edge is 1 or 2, and the data is less than 0 or greater than 3, then these two types of data may represent undershoot and undershoot respectively, and there may be some glitch data in the test waveform which may be mistaken for a rising or falling edge, so that it is necessary to filter the glitch data from these data. The high level is different from the glitch in that the high level is longer than the glitch data, so the software will last longer, and the data is 3 or more, which can be determined as the high level, and 0 or less as the low level. The specific search is implemented as follows.

The start point of the falling edge: that is, the high level starts to fall, the falling position may be overshot, and the falling burr may affect the judgment, so that the data should be greater than or equal to 3 where the high level is continuous, the falling position is less than 3, and the data amount cannot be too small. Searching the acquired data one by one, when the continuous 10 data are more than or equal to 3 and the following 5 data are less than 3, marking the first data which are not 3 as a first falling edge starting point, recording the offset address of the number, and then continuing searching until the waveform data are finished, and recording all falling edge starting point offset addresses.

Falling edge endpoint: i.e., the position where the intermediate level drops to the low level, undershoot may occur at the position of the transition, and thus, where the intermediate level drops to the low level, the data should be 0 or less. Searching the acquired data one by one, when the continuous 5 data are more than or equal to 2 and the following 5 data are less than or equal to 0, recording the first data which are less than or equal to 0 as a first falling edge end point, recording the offset address of the number, and then continuing searching until the waveform data are finished, and recording all the falling edge end point offset addresses.

Rising edge starting point: that is, since undershoot generally occurs at the position of the transition where the low level starts to rise, the data of the low level is 0 or less. Searching the acquired data one by one, when the continuous 5 data are smaller than or equal to 0 and the following 5 data are larger than 0, recording the first data larger than 0 as the starting point of the first rising edge, recording the offset address of the number, and then continuing searching until the waveform data are finished, and recording all the rising edge starting point offset addresses.

Rising edge endpoint: that is, where the intermediate level is shifted to the high level, the position of the transition may be overshot, and thus it is necessary to consider that the data of the high level should be 3 or more. Searching the acquired data one by one, when the continuous 5 data are smaller than 3 and the following 5 data are larger than or equal to 3, recording the first data which are equal to 3 as the end point of the first rising edge, recording the offset address of the number, and then continuing searching until the waveform data are finished, and recording all the end point offset addresses of the rising edge.

The difference between adjacent rising edge starting points and rising edge ending point offset positions is recorded as an interval, then the interval is respectively taken as x 10% + rising edge starting points, namely rising edge starting points of the calibration test are needed, and the end point position-interval is multiplied by 10%, namely rising edge ending points of the calibration test are needed. All rising and falling edge data are obtained in this way. Each offset position has a linear relationship with the waveform coordinates, and this coefficient we can obtain the linear coefficient by the time the oscilloscope obtained the waveform data before. And therefore, the offset position quantity of the data and the coordinate coefficient of the waveform are subjected to linear calculation, and finally the coordinates of the rising edge are obtained. And controlling the cursor to the position of the appointed coordinate, and finally obtaining the required measured value.

After analysis is finished, a test report of the firmware is generated, a folder is established for each test item on the test computer, corresponding test data are stored, and the test data comprise an oscillogram, a single test interface memory diagram, a test data table and the like. And (3) according to the provided report template, carrying out position calibration on the template, calling a word execution program in the background, importing data and pictures of corresponding test items into a report, and storing and generating a new word file.

Example 4:

fig. 15 is a schematic diagram of a firmware testing apparatus according to an embodiment of the invention. The firmware testing apparatus of the present embodiment includes one or more processors 21 and a memory 22. In fig. 15, a processor 21 is taken as an example.

The processor 21 and the memory 22 may be connected by a bus or otherwise, for example in fig. 15.

The memory 22 is used as a nonvolatile computer-readable storage medium for storing nonvolatile software programs and nonvolatile computer-executable programs, such as the firmware test method in embodiment 1. The processor 21 executes the firmware test method by running non-volatile software programs and instructions stored in the memory 22.

The memory 22 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 22 may optionally include memory located remotely from processor 21, which may be connected to processor 21 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The program instructions/modules are stored in the memory 22, and when executed by the one or more processors 21, perform the firmware test methods in embodiment 1 and embodiment 2 described above, for example, performing the steps shown in fig. 1-3 and 6 described above.

It should be noted that, because the content of information interaction and execution process between modules and units in the above-mentioned device and system is based on the same concept as the processing method embodiment of the present invention, specific content may be referred to the description in the method embodiment of the present invention, and will not be repeated here.

Those of ordinary skill in the art will appreciate that all or a portion of the steps in the various methods of the embodiments may be implemented by a program that instructs associated hardware, the program may be stored on a computer readable storage medium, the storage medium may include: read Only Memory (ROM), random access Memory (RAM, random Access Memory), magnetic or optical disk, and the like.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims (10)

1. A method for testing firmware, comprising:

acquiring digital waveforms of corresponding pins in the firmware according to the test items of the firmware;

scaling the digital waveform to find data to be analyzed in the digital waveform;

analyzing the data to be analyzed to obtain a test result of the test item.

2. The method for testing firmware according to claim 1, wherein the step of obtaining the digital waveform of the corresponding pin in the firmware specifically comprises:

acquiring an analog waveform of the pin by using an oscilloscope;

converting the analog waveform into a digital waveform according to the coordinate parameters of the analog waveform; the digital waveform comprises a plurality of data, the data are arranged according to the signal output time sequence of the pins, and each data represents the signal size of the pins at different times.

3. The firmware testing method according to claim 2, wherein said converting the analog waveform into a digital waveform according to the coordinate parameters of the analog waveform, specifically comprises:

According to the ordinate zero position, the ordinate offset and the ordinate coefficient in the coordinate parameters, converting the ordinate value in the analog waveform into an analog ordinate value;

the analog ordinate values are converted to corresponding digital signal magnitudes, thereby generating a digital waveform.

4. The firmware testing method according to claim 1, wherein said scaling said digital waveform to find data to be analyzed in said digital waveform comprises:

and finding out the rising edge and/or the falling edge in the digital waveform, and determining corresponding data to be analyzed according to the rising edge and/or the falling edge.

5. The firmware testing method of claim 4, wherein said finding a rising edge and/or a falling edge in said digital waveform comprises:

judging whether the difference value between the first data and the previous piece of data in the digital waveform is larger than a first preset difference value, if the difference value is larger than the first preset difference value, selecting a preset number of second data after the first data, and judging whether the difference value between the first data and each piece of second data is smaller than a second preset difference value;

if the difference value between the first data and each second data is smaller than the second preset difference value, and the values of the first data and the second data are larger than the value of the previous data, a rising edge of the digital waveform exists between the first data and the previous data;

If the difference value between the first data and each second data is smaller than the second preset difference value, and the values of the first data and the second data are smaller than the value of the previous data, a falling edge of the digital waveform exists between the first data and the previous data;

otherwise, there is neither a rising nor a falling edge between the first data and the previous piece of data.

6. The firmware testing method according to claim 1, wherein the analyzing the data to be analyzed obtains a test result of the test item, specifically comprising:

comparing the data to be analyzed with preset waveform data, analyzing the difference between the data to be analyzed and the preset waveform data, and if the difference is smaller than a preset difference threshold, enabling the test item to be normal;

or comparing the data to be analyzed in the digital waveforms of the plurality of pins in the firmware, and analyzing and obtaining the test result of the test item according to the preset relation among the digital waveforms of the plurality of pins.

7. The firmware testing method according to any one of claims 1 to 6, wherein when the firmware is an OLT device and the test item is an RxSD signal, a digital waveform of a detection signal of the OLT device, a digital waveform of a RESET signal of the OLT device, and a digital waveform of an RxSD signal of the OLT device are acquired;

Acquiring a first time delay between a falling edge of the RxSD signal and a rising edge of the RESET signal, and a second time delay between the rising edge of the RxSD signal and the first rising edge of the detection signal; wherein a first rising edge of the probe signal is a first rising edge generated after a falling edge of the RESET signal;

judging whether the first time delay is smaller than a first preset time delay threshold value or not, and judging whether the second time delay is smaller than a second preset time delay threshold value or not;

if the first time delay is smaller than a first preset time delay threshold and the second time delay is smaller than a second preset time delay threshold, the RxSD signal test item of the firmware is normal.

8. The firmware testing method of any one of claims 1 to 6, further comprising: the same test items of multiple firmware are tested, specifically,

after the last calibration and analysis process is finished, selecting one firmware from a plurality of firmware which does not obtain a test result as a first firmware of the next time, and taking other firmware which does not obtain the test result as a second firmware of the next time, and performing the next calibration and analysis process until test results of test items of all the firmware are obtained; in the first calibration and analysis process, one firmware is selected from all the firmware to be used as a first firmware, and the other firmware is selected to be used as a second firmware;

The calibration and analysis process specifically comprises the steps of calibrating a first firmware, finding data to be analyzed of the first firmware, and analyzing and obtaining a test result of a test item of the first firmware;

if the test item of the first firmware obtained by analysis is normal, a calibration interval is generated by taking the signal output time of the data to be analyzed of the first firmware as an interval center and taking the preset time as an interval size, and the data to be analyzed of the second firmware is searched in the calibration interval;

if the data to be analyzed of the second firmware is obtained in the calibration interval, analyzing the data to be analyzed of the second firmware to obtain a test result of a test item of the second firmware;

if the data to be analyzed of the second firmware is not found in the calibration interval, the test item of the second firmware is abnormal;

if the test item of the first firmware is abnormal, the test result of the test item of the second firmware cannot be obtained, and the second firmware is reserved to the next calibration and analysis process.

9. The firmware testing system is characterized by comprising a waveform acquisition module and an analysis module;

the waveform acquisition module is used for acquiring digital waveforms of corresponding pins in the firmware according to the test items of the firmware;

The analysis module is used for scaling the digital waveform to find out data to be analyzed in the digital waveform, analyzing the data to be analyzed and obtaining a test result of the test item.

10. The firmware testing system of claim 9, wherein the system further comprises a power module and a control module;

the power supply module is used for providing working power supply for the firmware;

the control module is used for providing corresponding input signals for the firmware, so that the working state of the firmware meets the test conditions.