CN117667547A - Storage parallel self-checking system and method after power-on - Google Patents
Storage parallel self-checking system and method after power-on Download PDFInfo
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Abstract
The invention discloses a parallel self-checking system and a method for storage after power-on, which relate to the technical field of memory self-checking and comprise a cloud platform, wherein the cloud platform is in communication connection with a self-checking judging module, a self-checking executing module, a central processing unit module and a maintenance matching module; judging whether to start storage self-checking or not by a self-checking judging module; the self-checking execution module is used for carrying out storage self-checking on the memory, the timing counter is set for counting, and the self-checking mark is set after all the memories finish the storage self-checking; acquiring a self-checking mark through a central processing unit module, judging whether the self-checking mark accords with a set time window, if so, clearing the numerical value of a timing counter and jumping to a main program, and if not, generating an overflow mark and triggering a non-maskable interrupt; and generating a fault parameter table according to the non-maskable interrupt by a maintenance matching module, setting a matching fault library, importing the fault parameter table to generate maintenance data information, and further arranging maintenance personnel to carry out maintenance processing.
Description
Technical Field
The invention relates to the technical field of memory self-checking, in particular to a memory parallel self-checking system and method after power-on.
Background
With the wide application of SOC chips in the automotive and industrial markets, functional safety becomes a key dimension of SOC chip design. Functional safety requires that SOC chips cannot have systematic faults and random hardware faults. For random hardware failures, the function of memory (memory includes read only memory ROM and static random access memory SRAM) is an important factor that affects the occurrence of random hardware failures. Since memory is typically the largest component of the overall device in terms of area and transistor count, and is a very dense circuit, it is susceptible to fine defects, and therefore, the operating voltage range of memory is lower and more susceptible to disturbances than normal logic circuits.
Therefore, the influence of temperature, voltage and the like on the memory is not negligible in the use process of the chip, but the chip in the normal use process cannot be directly returned to a factory for re-testing, so that a proper testing method needs to be found to avoid the risk. In order to solve the problem, an effective storage test method is provided for users, and the occurrence of safety problems caused by abnormal storage functions can be greatly reduced.
The existing memory self-checking after power-on is generally serial test, a PC (program counter) can wait for all memories to finish testing one by one and then finish initializing a chip, and finally jump to a main program. On the other hand, the method has the advantages that the method is flexible, different detection algorithms can be executed for the same storage, and errors which occur at any address can be accurately positioned. However, the storage self-test after power-up does not need to be particularly precisely positioned to the wrong address, if the self-test finds the error, the self-test needs to be manually intervened to replace the chip with the problem, and the chip with the problem is sent back to the factory for special test. The significance of the power-on self-test is that based on the current environment including temperature, voltage, etc., the memory function can meet the requirements, and no positioning to a specific address is necessary. The more complex the algorithm contained in the self-test, the larger the circuit itself, the larger the hardware resources required, which is not beneficial to saving the cost. The more complex the self-test circuit is, the more the probability of error per se is increased; these problems are all what we need to consider at present.
Disclosure of Invention
In order to solve the above problems, the present invention aims to provide a system and a method for storing parallel self-checking after power-up.
The aim of the invention can be achieved by the following technical scheme: the storage parallel self-checking system after power-on comprises a cloud platform, wherein the cloud platform is in communication connection with a self-checking judging module, a self-checking executing module, a central processing unit module and a maintenance matching module;
the self-checking judging module is used for operating the PC to jump to a boot-Rom to execute the boot program after the chip is powered on and reset, checking the data value of the power-down nonvolatile area in the process of executing the boot program, and further judging whether to start the storage self-checking;
the self-checking execution module is used for carrying out storage self-checking on a plurality of memories, setting a timing counter for counting, and setting a self-checking mark to be sent to the central processing unit module after all the memories finish the storage self-checking;
the central processing unit module is used for acquiring the self-checking mark, judging whether the acquisition of the self-checking mark accords with a set time window, if so, clearing the numerical value of the timing counter and jumping to a main program, and if not, generating an overflow mark by the timing counter and triggering the non-maskable interrupt;
the maintenance matching module is used for acquiring the appointed state of the IO according to the non-maskable interrupt, further generating a fault parameter table, setting a matching fault library for importing the fault parameter table to generate maintenance data information, and arranging corresponding maintenance personnel to carry out maintenance processing according to the maintenance data information.
Further, executing the boot program, and checking the data value of the power-down nonvolatile area in the process of executing the boot program, so as to judge whether to start the process of storing the self-check, wherein the process comprises the following steps:
setting a power-on period, carrying out chip power-on reset in the power-on period, judging whether the chip power-on reset is successful or not, if not, continuing to carry out the chip power-on reset in the power-on period until the chip power-on reset is successful, if so, acquiring the operation authority of the PC in the chip to operate the PC to jump to a boot-Rom position in the chip, executing a preset boot program by the boot-Rom, carrying out chip initialization corresponding to the chip by the boot program, wherein a power-down nonvolatile area is arranged in the chip, and acquiring a data value in the power-down nonvolatile area for checking in the process of executing chip initialization by the boot program;
and recording the data value in the power-down nonvolatile area as D1, presetting a self-checking expected value as D2, comparing the size relation between D1 and D2, further determining whether to start the function of storing self-checking, generating a starting signal if D1 is more than or equal to D2, starting the self-checking, and not starting the self-checking if D1 is less than D2.
Further, the self-checking execution module performs storage self-checking of a plurality of memories, sets a timing counter for counting, and sets a self-checking flag, which includes:
the chip comprises a plurality of memories, the memories are provided with corresponding storage types, the storage types comprise RAM memories and ROM memories, the memories with different storage types are associated with corresponding test circuits, and the test circuits comprise RAM test circuits and ROM test circuits;
the RAM test circuit is used for performing storage self-checking of the RAM memory, and the ROM test circuit is used for performing storage self-checking of the ROM memory and consists of test control logic, an excitation generator, a decoder and a data comparator;
after a test control logic in the test circuit receives a starting signal, the test circuit is started to carry out storage self-checking on a storage of a corresponding storage type, signals Sig0, sig1, sig2 and Sig3 are set, and when an excitation generator receives the signal Sig1, the excitation generator generates test excitation and sends the test excitation to a decoder through the signal Sig2 and to a data comparator through the signal Sig 3;
each data comparator is provided with a corresponding test IP, the test circuit sends test excitation to the corresponding test IP to generate read data, the read data is transmitted to the corresponding data comparator of the test circuit, the data comparator performs data proofreading, and then a signal 3 and a signal 5 are generated according to the data proofreading result;
setting a timing counter to count, wherein the timing counter comprises a timer 1 and a timer 2, the timer 1 is used for counting a signal 3, the timer 2 is used for counting a signal 5, full counting signals of the signal 3 and the signal 5 are respectively set, full counting signals corresponding to the signal 3 and the signal 5 are respectively a signal 4 and a signal 6, and when the storage self-checking of all memories is finished, a self-checking mark is set and sent to a central processing unit module.
Furthermore, the storage self-checking mode of the corresponding memories by the RAM test circuit and the ROM test circuit is parallel self-checking.
Further, the process of judging whether the self-checking mark accords with the set time window and executing corresponding operation according to the judging result comprises the following steps:
receiving the self-checking mark, acquiring the receiving time corresponding to the self-checking mark, setting a time window, recording the specified receiving time of the self-checking mark in the time window, judging whether the receiving time accords with the specified receiving time, and further generating different judging results, wherein the judging results comprise 'accord with' and 'do not accord with';
when the judgment result is 'accord', the corresponding count values of the timer 1 and the timer 2 are emptied, and the PC is called to jump to the set main program;
when the judgment result is "not met", the timer 1 and the timer 2 generate counting overflow, generate corresponding overflow marks, trigger an unshieldable interrupt, set IO in the chip and set the appointed state of the IO through the unshieldable interrupt.
Further, the process of generating the fault parameter table, setting a matching fault library to import the fault parameter table, and further generating the maintenance data information comprises the following steps:
acquiring the contracted state of the IO, wherein the contracted state comprises a program matching state and a manual intervention state;
when the agreed state is a program matching state, acquiring all operation parameters of the memory for storage self-checking, generating a fault parameter table according to abnormal data parts in the operation parameters, and setting a matching fault library, wherein the matching fault library comprises a plurality of fault information templates of different types, and the detailed fault parameters and fault solutions when the memory breaks down are recorded in the fault information templates of different types; importing the fault parameter table into a matching fault library, then matching a fault information template corresponding to the fault parameter table, taking detailed fault parameters and fault solutions in the fault information template as filling items, presetting a data information table, inputting the filling items into the data information table, and then generating corresponding maintenance data information;
when the contract state is the manual intervention state, an administrator schedules an off-line maintainer to replace the failed memory.
Further, the process of arranging the corresponding maintenance personnel to carry out maintenance processing according to the maintenance data information comprises the following steps:
the maintenance data information comprises maintenance time, maintenance storage numbers, maintenance priorities and maintenance personnel lists, the maintenance personnel lists record data information of a plurality of maintenance personnel, a memory with faults is located through the maintenance storage numbers, maintenance processing of the corresponding memory of the chip is carried out at the corresponding maintenance time according to the order of the maintenance priorities from high to low, a maintenance table is generated after the maintenance processing is finished, a new fault information template is generated through the maintenance table, and the new fault information template is imported into a matching fault library for matching corresponding faults of the subsequent memory.
Further, the self-checking of the memory includes self-checking of the memory, and the execution sequence is: after the storage self-checking of the non-boot related storage is completed, the storage self-checking of the boot related storage is started.
Further, a method for storing parallel self-checking after power-on, the method comprises:
step S1: after the chip is powered on and reset, the operation PC jumps to a boot-Rom to execute a boot program, and the data value of a power-down nonvolatile area is checked in the process of executing the boot program, so as to judge whether to start storage self-checking;
step S2: performing storage self-checking of a plurality of memories, setting a timing counter for counting, and setting a self-checking mark after all memories finish the storage self-checking;
step S3: acquiring a self-checking mark, judging whether the acquisition of the self-checking mark accords with a set time window, if so, clearing the numerical value of a timing counter and jumping to a main program, and if not, generating an overflow mark by the timing counter and triggering a non-maskable interrupt;
step S4: acquiring the appointed state of the IO according to the non-maskable interrupt, further generating a fault parameter table, setting a matching fault library for importing the fault parameter table to generate maintenance data information, and arranging corresponding maintenance personnel to carry out maintenance processing according to the maintenance data information.
Compared with the prior art, the invention has the beneficial effects that:
1. the power-on self-check is selectable through the programmable operation of the power-off nonvolatile area, the memory self-check in a parallel self-check mode is implemented on a plurality of memories corresponding to the test circuit in the chip, so that the self-check of the memories is more efficient and quick, the execution time of the main program in the chip is greatly advanced compared with that of the serial self-check, the structure is not limited by a process manufacturer and a process thereof, the IP of any third party can be used in a compatible mode, and the portability is high.
2. And on one hand, the matching of the fault problems of the memory is carried out through the matching fault library, the efficiency of locating the fault type is improved, on the other hand, if the matching fault library is matched with the fault information template, the corresponding maintenance data information is generated according to the fault information template, the fault solution of the corresponding fault problem of the memory is recorded in the maintenance data information, the corresponding maintenance personnel are arranged to carry out maintenance processing according to the fault solution, and the efficiency of repairing the fault problem of the memory is improved to a certain extent.
Drawings
Fig. 1 is a schematic diagram of the present invention.
Detailed Description
As shown in fig. 1, the storage parallel self-checking system after power-on comprises a cloud platform, wherein the cloud platform is in communication connection with a self-checking judging module, a self-checking executing module, a central processing unit module and a maintenance matching module;
the self-checking judging module is used for operating the PC to jump to a boot-Rom to execute the boot program after the chip is powered on and reset, checking the data value of the power-down nonvolatile area in the process of executing the boot program, and further judging whether to start the storage self-checking;
the self-checking execution module is used for carrying out storage self-checking on a plurality of memories, setting a timing counter for counting, and setting a self-checking mark to be sent to the central processing unit module after all the memories finish the storage self-checking;
the central processing unit module is used for acquiring the self-checking mark, judging whether the acquisition of the self-checking mark accords with a set time window, if so, clearing the numerical value of the timing counter and jumping to a main program, and if not, generating an overflow mark by the timing counter and triggering the non-maskable interrupt;
the maintenance matching module is used for acquiring the appointed state of the IO according to the non-maskable interrupt, further generating a fault parameter table, setting a matching fault library for importing the fault parameter table to generate maintenance data information, and arranging corresponding maintenance personnel to carry out maintenance processing according to the maintenance data information.
Specifically, after the chip is powered on and reset, the operation PC jumps to a boot-Rom to execute the boot program, and the process of checking the data value of the power-down nonvolatile area in the process of executing the boot program and further judging whether to start the process of storing the self-check comprises the following steps:
setting a power-on period, carrying out power-on reset of the chip in the power-on period, judging whether the power-on reset of the chip is successful, if not, continuing to carry out the power-on reset of the chip in the power-on period until the power-on reset of the chip is successful, if so, acquiring the operation authority of the PC in the chip, and operating the PC to jump to a boot-Rom position in the chip through the operation authority;
executing a preset boot program by the boot-Rom, wherein the boot program is used for initializing a chip corresponding to the chip, a power-down nonvolatile area is arranged in the chip, and acquiring a data value in the power-down nonvolatile area for checking in the process of executing the chip initialization by the boot program;
recording a data value in the power-down nonvolatile area as D1, presetting a self-checking expected value as D2, comparing the size relation between the D1 and the D2, and further determining whether to start a function of storing the self-checking;
if D1 is more than or equal to D2, generating a starting signal, starting the storage self-checking, and if D1 is less than D2, not starting the storage self-checking.
It should be noted that, the self-checking expected value preset in the power-down nonvolatile area can be changed through a programmable operation, and then the control of whether to power on self-checking is achieved by changing the self-checking expected value, so that the power on self-checking becomes optional.
Specifically, the self-checking execution module performs storage self-checking of a plurality of memories, sets a timing counter for counting, and sets a self-checking mark, wherein the process of setting the self-checking mark includes:
the chip comprises a plurality of memories, the memories are provided with corresponding storage types, the storage types comprise RAM memories and ROM memories, the memories of different storage types are associated with corresponding test circuits, and the test circuits comprise RAM test circuits and ROM test circuits;
the RAM test circuit is used for performing storage self-checking of the RAM memory, the ROM test circuit is used for performing storage self-checking of the ROM memory, and the structure of the test circuit is as follows: the test circuit consists of four parts, namely test control logic, an excitation generator, a decoder and a data comparator;
when a test control logic in the test circuit receives a starting signal, the test circuit is started to carry out storage self-checking on a storage of a corresponding storage type, the storage is numbered for the RAM storage, i=1, 2,3, … … and n are recorded, n is a natural number larger than 0, each number i is correspondingly provided with a corresponding signal channel and is recorded as S_i, and i is the number of the RAM storage;
the method for performing storage self-checking by the RAM test circuit comprises the steps of performing parallel self-checking, setting the number of RAM memories of the parallel self-checking as Num1, setting signals Sig0, sig1, sig2 and Sig3, generating test excitation by an excitation generator in the RAM test circuit when the excitation generator receives the signal Sig1, sending the test excitation to a decoder through the signal Sig2, and sending the test excitation to a data comparator through the signal Sig 3;
each data comparator is provided with a corresponding test IP, the data comparators and the memories keep a one-to-one correspondence in number, the corresponding test IP of the data comparator of the RAM test circuit corresponding to each RAM memory is recorded as RAM_IP [ i ], the RAM test circuit sends test excitation to the corresponding test IP through a signal channel S_i, the test IP receives the test excitation to generate read data of the RAM memory, and the read data is transmitted to the data comparator corresponding to the RAM test circuit through the signal channel S_i;
after the decoder acquires the test excitation, analyzing the test excitation to generate a correct storage data result of the current RAM memory, and acquiring the correct storage data result and the original test excitation after analysis according to the test excitation by the data comparator to further perform data verification;
the data is checked to have different checking results, the checking results comprise checking success and checking failure, the checking results are fed back to the test control logic through a signal Sig0, the test control logic outputs test success and test failure, and a signal 3 is generated, and when the test fails, the excitation generator is informed to stop working through a signal Sig 1;
when the ROM test circuit performs the self-test of the storage of the ROM memory, the workflow is the same as that of the RAM test circuit, except that: after the ROM test circuit data are collated, a collating result is generated, and then a signal 5 is generated;
the self-checking of the memory includes self-checking of the memory, and the execution sequence is: after the storage self-checking of the non-boot related storage is completed, starting the storage self-checking of the boot related storage;
setting a timing counter, wherein the timing counter comprises a timer 1 and a timer 2, the timer 1 and the timer 2 are structures similar to the counter, the timer 1 is a counter for performing storage self-checking on a non-boot related storage, the timer 2 is a counter for performing storage self-checking on a boot related storage, and design values of the timer 1 and the timer 2 are all related to the longest test time required by a single storage at a certain stage;
and respectively setting whether the timer 1 and the timer 2 are full of corresponding full signals 3 and 5, wherein the full signal corresponding to the signal 3 is a signal 4, the full signal corresponding to the signal 5 is a signal 6, and when the storage self-checking of all memories is finished, setting a self-checking mark and sending to the central processing unit module.
Specifically, the process of judging whether the self-checking mark accords with the set time window and executing corresponding operation according to the judging result comprises the following steps:
the central processing unit module receives the self-checking mark, acquires the receiving time corresponding to the self-checking mark, sets a time window, records the specified receiving time of the self-checking mark, judges whether the receiving time accords with the specified receiving time, and further generates different judging results;
the judging result comprises 'coincidence' and 'non-coincidence';
when the judgment result is 'accord', the corresponding numerical values of the timer 1 and the timer 2 are emptied, and the PC is called to jump to the set main program;
when the judgment result is "not met", the timer 1 and the timer 2 generate counting overflow, generate corresponding overflow marks, trigger an unshieldable interrupt, set IO in the chip and set the appointed state of the IO through the unshieldable interrupt.
Specifically, the process of generating the fault parameter table, setting a matching fault library to import the fault parameter table, and further generating the maintenance data information comprises the following steps:
the maintenance matching module acquires the appointed state of the IO, wherein the appointed state comprises a program matching state and a manual intervention state;
when the agreed state is a program matching state, the export memory stores all operation parameters of self-checking, and generates a fault parameter table according to abnormal data in the operation parameters, wherein the fault parameter table records all data of the memory with faults;
setting a matching fault library, wherein the matching fault library comprises a plurality of fault information templates of different types, and the fault information templates of different types record detailed fault parameters and fault solutions when a memory breaks down;
importing the fault parameter table into a matching fault library, then matching a fault information template corresponding to the fault parameter table, taking detailed fault parameters and fault solutions in the fault information template as filling items, presetting a data information table, inputting the filling items into the data information table, and then generating corresponding maintenance data information;
when the contract state is the manual intervention state, an administrator directly arranges off-line maintenance personnel to replace the failed memory.
Specifically, the process of arranging the corresponding maintenance personnel to carry out maintenance processing according to the maintenance data information comprises the following steps:
the maintenance data information comprises maintenance time, maintenance storage numbers, maintenance priority and maintenance personnel lists;
the maintenance personnel list records data information of a plurality of maintenance personnel, a faulty memory is positioned through the number of the maintenance memory, and maintenance processing of the memory corresponding to the chip is performed at the corresponding maintenance time according to the order of the maintenance priority from high to low;
and generating a maintenance repair table after the maintenance treatment is finished, generating a new fault information template through the maintenance repair table, and importing the newly generated fault information template into a matching fault library for subsequent rapid matching of corresponding faults of the memory.
The invention also provides a storage parallel self-checking method after power-on, which comprises the following steps:
step S1: after the chip is powered on and reset, the operation PC jumps to a boot-Rom to execute a boot program, and the data value of a power-down nonvolatile area is checked in the process of executing the boot program, so as to judge whether to start storage self-checking;
step S2: performing storage self-checking of a plurality of memories, setting a timing counter for counting, and setting a self-checking mark after all memories finish the storage self-checking;
step S3: acquiring a self-checking mark, judging whether the acquisition of the self-checking mark accords with a set time window, if so, clearing the numerical value of a timing counter and jumping to a main program, and if not, generating an overflow mark by the timing counter and triggering a non-maskable interrupt;
step S4: acquiring the appointed state of the IO according to the non-maskable interrupt, further generating a fault parameter table, setting a matching fault library for importing the fault parameter table to generate maintenance data information, and arranging corresponding maintenance personnel to carry out maintenance processing according to the maintenance data information.
The above embodiments are only for illustrating the technical method of the present invention and not for limiting the same, and it should be understood by those skilled in the art that the technical method of the present invention may be modified or substituted without departing from the spirit and scope of the technical method of the present invention.
Claims (9)
1. The parallel self-checking system comprises a cloud platform and is characterized in that the cloud platform is in communication connection with a self-checking judging module, a self-checking executing module, a central processing unit module and a maintenance matching module;
the self-checking judging module is used for operating the PC to jump to a boot-Rom to execute the boot program after the chip is powered on and reset, checking the data value of the power-down nonvolatile area in the process of executing the boot program, and further judging whether to start the storage self-checking;
the self-checking execution module is used for carrying out storage self-checking on a plurality of memories, setting a timing counter for counting, and setting a self-checking mark to be sent to the central processing unit module after all the memories finish the storage self-checking;
the central processing unit module is used for acquiring the self-checking mark, judging whether the acquisition of the self-checking mark accords with a set time window, if so, clearing the numerical value of the timing counter and jumping to a main program, and if not, generating an overflow mark by the timing counter and triggering the non-maskable interrupt;
the maintenance matching module is used for acquiring the appointed state of the IO according to the non-maskable interrupt, further generating a fault parameter table, setting a matching fault library for importing the fault parameter table to generate maintenance data information, and arranging corresponding maintenance personnel to carry out maintenance processing according to the maintenance data information.
2. The system of claim 1, wherein the step of executing a boot program and checking a data value of a power-down nonvolatile region during the execution of the boot program, and further determining whether to start the storage self-test comprises:
setting a power-on period, carrying out chip power-on reset in the power-on period, judging whether the chip power-on reset is successful or not, if not, continuing to carry out the chip power-on reset in the power-on period until the chip power-on reset is successful, if so, acquiring the operation authority of the PC in the chip to operate the PC to jump to a boot-Rom position in the chip, executing a preset boot program by the boot-Rom, carrying out chip initialization corresponding to the chip by the boot program, wherein a power-down nonvolatile area is arranged in the chip, and acquiring a data value in the power-down nonvolatile area for checking in the process of executing chip initialization by the boot program;
and recording the data value in the power-down nonvolatile area as D1, presetting a self-checking expected value as D2, comparing the size relation between D1 and D2, further determining whether to start the function of storing self-checking, generating a starting signal if D1 is more than or equal to D2, starting the self-checking, and not starting the self-checking if D1 is less than D2.
3. The system of claim 2, wherein the self-checking execution module performs a self-checking of the storage of the plurality of memories, sets the timer counter to count, and sets the self-checking flag, the process comprising:
the chip comprises a plurality of memories, the memories are provided with corresponding storage types, the storage types comprise RAM memories and ROM memories, the memories with different storage types are associated with corresponding test circuits, and the test circuits comprise RAM test circuits and ROM test circuits;
the RAM test circuit is used for performing storage self-checking of the RAM memory, and the ROM test circuit is used for performing storage self-checking of the ROM memory and consists of test control logic, an excitation generator, a decoder and a data comparator;
after a test control logic in the test circuit receives a starting signal, the test circuit is started to carry out storage self-checking on a storage of a corresponding storage type, signals Sig0, sig1, sig2 and Sig3 are set, and when an excitation generator receives the signal Sig1, the excitation generator generates test excitation and sends the test excitation to a decoder through the signal Sig2 and to a data comparator through the signal Sig 3;
each data comparator is provided with a corresponding test IP, the test circuit sends test excitation to the corresponding test IP to generate read data, the read data is transmitted to the corresponding data comparator of the test circuit, the data comparator performs data proofreading, and then a signal 3 and a signal 5 are generated according to the data proofreading result;
setting a timing counter to count, wherein the timing counter comprises a timer 1 and a timer 2, the timer 1 is used for counting a signal 3, the timer 2 is used for counting a signal 5, full counting signals of the signal 3 and the signal 5 are respectively set, full counting signals corresponding to the signal 3 and the signal 5 are respectively a signal 4 and a signal 6, and when the storage self-checking of all memories is finished, a self-checking mark is set and sent to a central processing unit module.
4. A storage-after-power-up parallel self-test system as claimed in claim 3, wherein said RAM test circuit and ROM test circuit perform storage self-test of the respective memories in a parallel self-test manner.
5. A storage-after-power-up parallel self-test system according to claim 3, wherein the process of judging whether the self-test flag accords with the set time window and executing the corresponding operation according to the judgment result comprises:
receiving the self-checking mark, acquiring the receiving time corresponding to the self-checking mark, setting a time window, recording the specified receiving time of the self-checking mark in the time window, judging whether the receiving time accords with the specified receiving time, and further generating different judging results, wherein the judging results comprise 'accord with' and 'do not accord with';
when the judgment result is 'accord', the corresponding count values of the timer 1 and the timer 2 are emptied, and the PC is called to jump to the set main program;
when the judgment result is "not met", the timer 1 and the timer 2 generate counting overflow, generate corresponding overflow marks, trigger an unshieldable interrupt, set IO in the chip and set the appointed state of the IO through the unshieldable interrupt.
6. The post-power-up storage parallel self-checking system according to claim 5, wherein the process of generating the fault parameter table and setting a matching fault library to import the fault parameter table, and further generating the maintenance data information comprises:
acquiring the contracted state of the IO, wherein the contracted state comprises a program matching state and a manual intervention state;
when the agreed state is a program matching state, acquiring all operation parameters of the memory for storage self-checking, generating a fault parameter table according to abnormal data parts in the operation parameters, and setting a matching fault library, wherein the matching fault library comprises a plurality of fault information templates of different types, and the detailed fault parameters and fault solutions when the memory breaks down are recorded in the fault information templates of different types; importing the fault parameter table into a matching fault library, then matching a fault information template corresponding to the fault parameter table, taking detailed fault parameters and fault solutions in the fault information template as filling items, presetting a data information table, inputting the filling items into the data information table, and then generating corresponding maintenance data information;
when the contract state is the manual intervention state, an administrator schedules an off-line maintainer to replace the failed memory.
7. The post-power-up storage parallel self-checking system according to claim 6, wherein the process of arranging the corresponding maintenance personnel to perform the maintenance process according to the maintenance data information comprises:
the maintenance data information comprises maintenance time, maintenance storage numbers, maintenance priorities and maintenance personnel lists, the maintenance personnel lists record data information of a plurality of maintenance personnel, a memory with faults is located through the maintenance storage numbers, maintenance processing of the corresponding memory of the chip is carried out at the corresponding maintenance time according to the order of the maintenance priorities from high to low, a maintenance table is generated after the maintenance processing is finished, a new fault information template is generated through the maintenance table, and the new fault information template is imported into a matching fault library for matching corresponding faults of the subsequent memory.
8. A storage self-checking system after power-up according to claim 3, wherein the storage self-checking performed on the memory includes a non-boot related storage self-checking, and a boot related storage self-checking, and the execution sequence is: after the storage self-checking of the non-boot related storage is completed, the storage self-checking of the boot related storage is started.
9. A method for storing parallel self-checking after power-up, for implementing the parallel self-checking system according to any one of claims 1 to 8, characterized by comprising the following steps:
step S1: after the chip is powered on and reset, the operation PC jumps to a boot-Rom to execute a boot program, and the data value of a power-down nonvolatile area is checked in the process of executing the boot program, so as to judge whether to start storage self-checking;
step S2: performing storage self-checking of a plurality of memories, setting a timing counter for counting, and setting a self-checking mark after all memories finish the storage self-checking;
step S3: acquiring a self-checking mark, judging whether the acquisition of the self-checking mark accords with a set time window, if so, clearing the numerical value of a timing counter and jumping to a main program, and if not, generating an overflow mark by the timing counter and triggering a non-maskable interrupt;
step S4: acquiring the appointed state of the IO according to the non-maskable interrupt, further generating a fault parameter table, setting a matching fault library for importing the fault parameter table to generate maintenance data information, and arranging corresponding maintenance personnel to carry out maintenance processing according to the maintenance data information.
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| US20190227894A1 (en) * | 2018-01-19 | 2019-07-25 | Silicon Motion, Inc. | System and method for testing a data storage device |
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