CN117650793B - Heterogeneous distributed embedded software defined radio system and waveform deployment method thereof - Google Patents
Heterogeneous distributed embedded software defined radio system and waveform deployment method thereof Download PDFInfo
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Abstract
The invention relates to a heterogeneous distributed embedded software defined radio system and a waveform deployment method thereof, wherein the system comprises a main control board and a plurality of signal processing boards, the main control board also comprises a waveform deployment module, the waveform deployment module comprises a waveform matching submodule and a waveform component loading submodule, the waveform matching submodule is used for dividing virtual GPP/DSP/FPGA logic equipment into different radio communication channels, a software defined radio waveform component is directly matched with GPP/DSP/FPGA logic equipment in the corresponding radio communication channels, and the waveform component loading submodule is used for loading the software defined radio waveform component from the matched GPP/DSP/FPGA logic equipment onto corresponding GPP processor cores of a heterogeneous embedded processor GPP processor and/or DSP processor cores of a DSP processor and/or FPGA resource areas of the heterogeneous embedded processor FPGA processor. The method has the advantages of high resource utilization rate and good application deployment efficiency.
Description
[ Field of technology ]
The invention relates to the technical field of microelectronic communication, in particular to a heterogeneous distributed embedded software defined radio system and a waveform deployment method thereof.
[ Background Art ]
In the fields of communication and military, the development of microelectronic technology and communication technology has promoted the transition from a traditional embedded system (embedded real-time system) to a heterogeneous distributed embedded system, real-time communication is required between various embedded devices, and the various embedded devices are often built on heterogeneous software and hardware platforms, so that the reasonable allocation of tasks in the heterogeneous distributed embedded system is a key for improving the performance. In general, reasonable distribution scheduling content of tasks of the heterogeneous distributed embedded system comprises a design of a computing component and a communication basic framework, so that the system performance is improved, and the system is enabled to operate efficiently.
Radio software is the implementation of a programmable, reconfigurable radio communication channel or system by applying algorithms. Software defined radio (Software Defined Radio, SDR) is a radio broadcast communication technology that is based on a software defined wireless communication protocol rather than being implemented by hard-wiring. The frequency band, air interface protocol and functions of the radio signal (waveform) can be upgraded by software downloads and updates without completely replacing the hardware.
The SRTF standard is a set of communication standards proposed for Software Defined Radio (SDR) with the aim of providing deployment, management, interconnection and intercommunication of software components in an embedded, distributed computing communication system. The SRTF standard establishes an implementation-independent framework in which a standardized set of interfaces and specifications are defined that can help develop a Software Defined Radio (SDR) communication system, improve interoperability of the communication system, and reduce development and deployment costs.
A software defined radio platform is a heterogeneous distributed embedded system consisting of a plurality of different types of processors (such as GPP, DSP and FPGA), each processor having unique computing capabilities and characteristics. In order to support complex and changeable application scenes, the system has higher requirements on flexible scheduling of processing resources and matching of software and hardware resources of the system. The existing resource allocation method has a plurality of problems, such as low resource utilization rate of the multi-core processor, low matching efficiency caused by too wide matching range during resource matching, and lack of fault-tolerant mechanism capable of enabling the system to continuously and stably run.
Existing resource management mechanisms typically take the entire multi-core processor as the smallest resource scheduling unit. Under such a resource management mechanism, tasks cannot fully exploit the performance of the entire multi-core processor. These tasks typically occupy only one or a portion of the cores of the processor, and the remaining cores are wasted and unavailable. For example, only one algorithm is run on a DSP and FPGA processor, and the rest algorithms can be divided into GPP (General Purpose Processor ) which is not suitable for special operation, thus performance bottleneck can occur; or more DSP or FPGA processors are forced to be added, so that the volume and weight of the hardware equipment are increased, the power consumption is increased, and the overall performance of the program, the power consumption of the product, the volume of the hardware equipment of the product and the like are influenced.
The current resource allocation method of the heterogeneous distributed embedded system is generally that waveform components complete matching in a resource pool of the whole system. The waveform component is matched with each logic device in sequence in the resource pool until the waveform component is successfully matched with a certain logic device or the waveform component is unsuccessfully matched with all logic devices in the resource pool, and the matching efficiency of the mode is low.
While heterogeneous distributed embedded systems lack good fault tolerance mechanisms. When abnormal phenomena (such as overhigh temperature and overhigh current of the board card) occur in the system operation, and the waveform cannot normally operate, no reliable fault-tolerant mechanism exists to enable the waveform to migrate to other board cards for re-operation, and the reliability of the program is affected.
Aiming at the technical problems of low matching efficiency and lack of a good fault tolerance mechanism in the prior art, the invention improves the heterogeneous distributed embedded software defined radio system and the waveform deployment method thereof.
[ Invention ]
The invention aims to provide a heterogeneous distributed embedded software defined radio system with high resource utilization rate, good application deployment efficiency and strong reliability.
In order to achieve the above purpose, the technical scheme adopted by the invention is a heterogeneous distributed embedded software defined radio system, which comprises a main control board and a plurality of signal processing boards, wherein the main control board comprises a GPP processor and an in-board information exchange module; the signal processing board comprises a heterogeneous embedded processor and an on-board information exchange module, wherein the heterogeneous embedded processor comprises a GPP processor and/or a DSP processor and/or an FPGA processor, the heterogeneous embedded processor comprises a plurality of GPP processing cores, the heterogeneous embedded processor DSP processor comprises a plurality of DSP processing cores, and the heterogeneous embedded processor FPGA processor comprises a plurality of FPGA resource areas; the information exchange module in the main control board is connected with the information exchange modules in the signal processing boards through an information bus; the main control board further comprises a waveform deployment module, the waveform deployment module comprises a waveform matching sub-module and a waveform component loading sub-module, the waveform matching sub-module is used for dividing virtual GPP/DSP/FPGA logic equipment into different radio communication channels, a software defined radio waveform component is directly matched with the GPP/DSP/FPGA logic equipment in the corresponding radio communication channel, and the waveform component loading sub-module is used for loading the software defined radio waveform component from the matched GPP/DSP/FPGA logic equipment onto corresponding GPP processor cores of the heterogeneous embedded processor GPP processor and/or DSP processor cores of the DSP processor and/or FPGA resource areas of the heterogeneous embedded processor FPGA processor.
Further, the main control board also comprises a health management service module; the signal processing board also comprises an IPMC module, wherein the IPMC module is a hardware module for acquiring temperature, voltage and current data of the heterogeneous embedded processor of the signal processing board and monitoring the health state; the main control board health management service module is connected with the plurality of signal processing board IPMC modules through a health management bus; the health management service module is used for monitoring health states of the heterogeneous embedded processors of the signal processing boards through the IPMC module, and timely notifying the waveform deployment module to unload the software-defined radio waveform components from the heterogeneous embedded processors of the signal processing boards in abnormal states and reload the software-defined radio waveform components onto the heterogeneous embedded processors of the signal processing boards in normal states.
Preferably, the main control board inboard information exchange module comprises an inboard service exchange sub-module and an inboard ethernet exchange sub-module, the signal processing board inboard information exchange module comprises an inboard service exchange sub-module and an inboard ethernet exchange sub-module, the main control board inboard service exchange sub-module is connected with a plurality of signal processing board inboard service exchange sub-modules through service buses, and the main control board inboard ethernet exchange sub-module is connected with a plurality of signal processing board inboard ethernet exchange sub-modules through ethernet buses.
Preferably, the main control board GPP processor performs waveform matching under the control of the waveform matching submodule, and performs the following steps:
P1, creating GPP/DSP/FPGA logic equipment, software defined radio waveforms and waveform components thereof;
P2, creating a plurality of radio communication channels, adding GPP/DSP/FPGA logic equipment into different radio communication channels, and generating a PDD.XML file;
P3, configuring a mapping relation between a software-defined radio waveform and a plurality of radio communication channels to be deployed, and generating an ADD.XML file;
P4, if the step P3 designates that the software defined radio waveform deployment is finished by using a specific radio communication channel, reading the corresponding radio communication channel information in the PDD.XML file, and finishing the matching of the software defined radio waveform component and GPP/DSP/FPGA logic equipment in the radio communication channel; otherwise, reading all radio communication channel information associated with the software defined radio waveform from the ADD.XML file, performing GPP/DSP/FPGA logic device matching on the software defined radio waveform from the first radio communication channel, and performing GPP/DSP/FPGA logic device matching on the next radio communication channel if the matching fails;
and P5, all software-defined radio waveforms in the step P4 can be matched with GPP/DSP/FPGA logic equipment, the software-defined radio waveform matching is successful, and otherwise, the software-defined radio waveform matching fails.
Preferably, the main control board GPP processor is controlled by the waveform component loading submodule to load the waveform component, and performs the following steps:
j1, creating a software defined radio waveform and a waveform component model thereof, wherein the waveform component model comprises a GPP waveform component, a DSP waveform component and an FPGA waveform component, and configuring GPP processor cores, DSP processing cores or FPGA resource area numbering attributes for the GPP waveform component, the DSP waveform component and the FPGA waveform component, and designating GPP processor cores, DSP processing cores or FPGA resource areas to be loaded and operated by the GPP waveform component, the DSP waveform component and the FPGA waveform component;
J2, generating a software defined radio waveform description file SAD.XML, wherein coreaffinity elements are used as labels of processor nuclear numbers in the SAD.XML file, and each GPP waveform component, DSP waveform component and FPGA waveform component in the software defined radio waveform has a coreaffinity value for marking GPP processor nuclear, DSP processing nuclear or FPGA resource area to be loaded and operated;
j3, when the software defined radio waveform component is loaded, analyzing a software defined radio waveform description file SAD.XML, analyzing the software defined radio waveform component elements, and reading coreaffinity values corresponding to the software defined radio waveform component;
j4, calling GPP/DSP/FPGA logic equipment execution interface, and transmitting coreaffinity values of the software defined radio waveform component as parameters;
j5, GPP/DSP/FPGA logic equipment judges whether coreaffinity values are available or not;
J6, the GPP/DSP/FPGA logic device deploys the software defined radio waveform component to GPP processor core, DSP processing core, or FPGA resource region identified by coreaffinity values.
Preferably, in step J6, the GPP logic device deploys the software defined radio waveform element to the GPP processor core: the GPP logic calls an API interface for setting CPU affinity by the operating system to bind the software defined radio waveform component program with the appointed GPP processor core; after binding through the API interface, the software defined radio waveform component executes on the designated GPP processor core when executed.
Preferably, the step J6 of deploying the software defined radio waveform component to the DSP processor core by the DSP logic device specifically includes the steps of:
DJ61, DSP logic device sends the software defined radio waveform component and DSP processing core number to DSP processor master control core;
DJ62, the DSP processor master control core stores the software defined radio waveform component file in the shared file area of the DSP processor;
DJ63, DSP processor master control core sends software defined radio waveform component file name to DSP processing core designated by DSP processing core number.
DJ64, the designated DSP processing core copies the software defined radio waveform component files from the DSP shared file area to memory space within the DSP processor core;
DJ65, the designated DSP processing core loads the software defined radio waveform component program into memory for execution.
Preferably, the deploying the software defined radio waveform component into the FPGA resource area by the FPGA logic device in step J6 specifically includes the following steps:
FJ61, dividing the resources of the FPGA processor according to the actual functional design of the software-defined radio waveform components, each software-defined radio waveform component delineating a region of resource usage on the FPGA processor according to a specific function, the region being referred to as a reconfigurable region;
FJ62, the same function of the software defined radio waveform components is integrated into a static logic area, each software defined radio waveform component has the same function, and the resource area formed by extracting and integrating the parts is called a static logic area, and the static logic area is unified to realize the same function for all the software defined radio waveform components;
FJ63, locking all logic circuit position information and routing information of a static logic area of the FPGA processor, and not allowing to be modified again;
FJ64, generating an algorithm, resource information and interaction interface information of a static logic area of the FPGA processor into an environment bit file, and configuring an initial environment of the FPGA processor;
FJ65, generating a corresponding software defined radio waveform component bit file by using the algorithm and the resource information of each reconfigurable area of the FPGA processor;
The FJ66, FPGA logic device transmits the software defined radio waveform components to the FPGA processor reconfigurable area.
FJ67, FPGA processor runs software defined radio waveform component programs for the reconfigurable area.
Preferably, the heterogeneous distributed embedded software defined radio system is used for software defined radio waveform deployment of SRTF standard.
The heterogeneous distributed embedded software defined radio system and the waveform deployment method thereof have the following beneficial effects: firstly, adopting a heterogeneous processor on-chip resource deployment technology to deploy waveform components to a processor core of GPP and DSP processors and a resource area of an FPGA processor, so as to improve the resource utilization rate and the system performance between heterogeneous resources; secondly, a channel-based waveform deployment technology is adopted, each channel is a resource pool, logic devices are divided into different channels, and when waveforms are loaded, waveform components are not matched with all logic devices in nodes, but are directly matched with the logic devices in the channels, so that the range of searching resources by the waveform components is reduced, and the resource matching efficiency is effectively improved; thirdly, health management service is adopted to monitor the health state of the resources, waveforms are unloaded from the resources in abnormal states in time and are deployed on the resources in normal states again, and therefore the reliability of the system is improved.
[ Description of the drawings ]
Fig. 1 is a channel deployment flow diagram of a heterogeneous distributed embedded software defined radio system waveform deployment method waveform.
Fig. 2 is a flow chart of a heterogeneous distributed embedded software defined radio system waveform deployment method health management service.
Fig. 3 is a schematic diagram of a specific scenario in which a heterogeneous distributed embedded software defined radio system waveform deployment method health management service and channel deployment of waveforms are used in combination.
Fig. 4 is a flow chart of a heterogeneous distributed embedded software defined radio system waveform deployment method heterogeneous processor on-chip resource deployment.
Fig. 5 is a schematic diagram of a heterogeneous distributed embedded software defined radio system waveform deployment method DSP logic device deploying waveform components to a processor core.
Fig. 6 is a flowchart of a heterogeneous distributed embedded software defined radio system waveform deployment method DSP logic device deployment waveform components to a processor core.
Fig. 7 is a schematic diagram of a heterogeneous distributed embedded software defined radio system waveform deployment method FPGA reconfigurable regions.
Fig. 8 is a flowchart of a heterogeneous distributed embedded software defined radio system waveform deployment method FPGA waveform component specific generation and loading.
[ Detailed description ] of the invention
The invention is further described below with reference to examples and with reference to the accompanying drawings.
Examples
The embodiment realizes a waveform deployment method of a heterogeneous distributed embedded software defined radio system.
The method of the embodiment aims at providing a method for distributing heterogeneous distributed embedded system computing resources such as (GPP, DSP, FPGA). The method provides an efficient and reliable resource allocation scheme for the heterogeneous distributed embedded system, and effectively improves the system resource utilization rate, the application deployment efficiency and the system reliability.
The method of the embodiment adopts a waveform channel deployment technology and a heterogeneous processor on-chip resource deployment technology to improve the computing resource allocation efficiency of the heterogeneous distributed embedded system, and simultaneously improves the system reliability by using the health management service.
Fig. 1 is a channel deployment flow diagram of a heterogeneous distributed embedded software defined radio system waveform deployment method waveform. As shown in fig. 1, the channel deployment technique of the present embodiment is a technique for reducing the range of resources that need to be matched when a waveform is deployed from the whole system resource to one or more channel resources. Each channel is a resource pool, a plurality of logic device resources are arranged in the resource pool, the logic devices have the capability of deploying waveforms, and the mapping relation between the channels and the logic devices is stored in a PDD.XML file. The number of deployable channels of a waveform may be plural, when a waveform fails to match resources on one channel (insufficient resources in a channel), the next channel may be matched, and the mapping relationship between the waveform and the channel is stored in an add. When the waveform is deployed, the waveform component is directly matched with logic equipment in the channel by reading information in ADD.XML and PDD.XML, and the waveform deployment is completed. The method effectively reduces the number of logic devices required to be matched by the waveform components, and further shortens the matching time. The specific flow of channel deployment of the waveform of this embodiment:
Step 1: create logic devices, waveform components, waveforms.
Step 2: a channel is created and a logical device is added to the channel.
Step3: a pdd.xml file is generated.
Step 4: configuring mapping relation between waveform and channel to be deployed, and searching logic device in channel to complete deployment.
Step 5: an add.xml file is generated.
Step 6: when the waveform is deployed, if the specific channel is designated to be used for completing the deployment, the corresponding channel information in the PDD.XML file is read, and the matching of the waveform component and the logic device in the channel is completed. If no specific channel is specified for use, information of all channels associated with the waveform is read from the ADD.XML file, the waveform performs resource matching on the first channel, and if matching fails (insufficient resources), the resources of the next channel are matched.
Step 7: in the case that all waveform components can be successfully matched, the waveform completes deployment. Otherwise, the waveform deployment fails.
Fig. 2 is a flow chart of a heterogeneous distributed embedded software defined radio system waveform deployment method health management service. As shown in fig. 2, the health management service of the present embodiment is a software for monitoring the status of computing resources and managing the status of logical devices. The health management service makes corresponding judgment and decision by analyzing the temperature, voltage and current data of the computing resources collected by the IPMC module. The IPMC module is a hardware module which is specially responsible for collecting temperature, voltage and current data of the processor on the board card. When the health management service monitors abnormal temperature, voltage and current data, the logic device state of the corresponding processor can be set to be abnormal. The health management service unloads the waveform from the board card with abnormal state, and redeploys the waveform to the board card with normal state to continue running.
Fig. 3 is a schematic diagram of a specific scenario in which a heterogeneous distributed embedded software defined radio system waveform deployment method health management service and channel deployment of waveforms are used in combination. As shown in fig. 3, logic devices on the signal processing board 1 and the signal processing board 2 of a specific scenario where the present implementation health management service and channel deployment of waveforms are used in combination are respectively divided into the channel 1 and the channel 2. In the initial state, the waveform successfully matches the logic device in channel 1 and is installed on channel 1. And then the IPMC module sends the collected temperature, voltage and current data on the signal processing board 1 to the health management service, and the health management service software judges that the data is abnormal and sets the logic device state of the channel 1 on the signal processing board 1as abnormal. The health management service uninstalls the waveforms from the signal processing board 1 and reinstalls the waveforms in the channels 2 on the signal processing board 2.
Fig. 4 is a flow chart of a heterogeneous distributed embedded software defined radio system waveform deployment method heterogeneous processor on-chip resource deployment. As shown in fig. 4, the heterogeneous processor on-chip resource deployment technique of the present embodiment is a technique of deploying waveform components onto the processor cores of GPP and DSP processors and the resource areas of FPGA processors. The deployment flow of the waveform component comprises the following specific steps:
step 1: waveforms and waveform component models are created. The GPP, DSP, FPGA waveform components are configured with processor core number attributes that specify that the waveform components are to be loaded and run on a certain core of the processor.
Step 2: and generating a description file SAD.XML of the waveform. The xml file uses coreaffinity elements as labels for the processor core number. Each GPP, DSP, FPGA waveform component in the waveform has a coreaffinity value that indicates what core or region of the processor the component is to be deployed in.
Step 3: when the waveform is installed, the SRTF core framework parses the description file SAD.XML of the waveform. The waveform element is parsed in the SAD.XML file and the values in the coreaffinity element tags of the waveform element are read.
Step 4: the logic device execution interface is invoked and the coreaffinity values of the waveform components are passed in as parameters.
Step 5: the logic device determines coreaffinity if a value is available.
Step 6: the logic device deploys the waveform component to the processor core identified by the coreaffinity value. The manner in which waveform components of GPP, DSP, FPGA logic devices are deployed varies, with the specific steps being as follows.
The process of deploying waveform components to processor cores by GPP logic is that the logic calls an API interface for the operating system to set CPU affinity to bind the waveform component program to the designated processor core. After binding through the API, the waveform component executes on the designated processor core when executing.
Fig. 5 is a schematic diagram of a heterogeneous distributed embedded software defined radio system waveform deployment method DSP logic device deploying waveform components to a processor core. Fig. 6 is a flowchart of a heterogeneous distributed embedded software defined radio system waveform deployment method DSP logic device deployment waveform components to a processor core. As shown in fig. 5 and 6, a specific flowchart of the DSP logic device deployment waveform components to the processor core is as follows.
Step 1: the logic device sends the waveform component and the processor core number to the master core of the DSP processor.
Step 2: the main control core of the DSP processor stores the waveform component files in the shared file area. The shared file region is a memory space where all processor cores of the DSP can store files.
Step 3: the master core of the DSP processor sends the waveform component filename to the designated processor core.
Step 4: the designated processor core copies the waveform element file from the shared file region to memory space within the processor core.
Step 5: the designated core loads the waveform component program into the memory and then executes the waveform component program.
The partition to which the FPGA component partition loads the waveform component is determined at the time the waveform component is generated. The FPGA waveform component, when generated, divides a reconfigurable region, which is the region that the waveform component produces when resources are delineated on the FPGA processor according to its function. When generating the bit file of the waveform component, the development tool writes the base address of the reconfigurable area into the bit file; when the waveform component is loaded, the FPGA processor loads the waveform component into the corresponding reconfigurable area by reading the base address of the reconfigurable area in the file. Fig. 7 is a schematic diagram of a heterogeneous distributed embedded software defined radio system waveform deployment method FPGA reconfigurable regions. Fig. 8 is a flowchart of a heterogeneous distributed embedded software defined radio system waveform deployment method FPGA waveform component specific generation and loading. As shown in fig. 7 and 8, the FPGA reconfigurable area is divided into two areas, and the specific generating and loading flow of the FPGA waveform component is as follows.
Step 1: and dividing the resources of the FPGA processor according to the actual functional design of the waveform component. Each waveform component delineates the resource usage of an area on the FPGA processor according to a specific function. This region is called the reconfigurable region.
Step 2: the same function is integrated into a static logic area. The resource area which is formed by extracting and integrating the parts with the same functions of each waveform component is called a static logic area. The static logic area is unified to realize the functions of the same part for all waveform components.
Step 3: all location information and routing information of the static logical area are locked. All logic circuit position information and routing information of the static logic area are locked, and are not allowed to be modified again.
Step 4: the algorithm, the resource information, the interaction interface and other information of the static logic area are generated into an environment bit file and are used for configuring the initial environment of the FPGA processor.
Step 5: the algorithm and the resource information of each reconfigurable area generate a corresponding waveform component bit file.
Step 6: the FPGA logic device transmits the waveform components to a reconfigurable area of the FPGA processor.
Step 7: the FPGA processor runs the reconfigurable area program.
The core technical conception of the method of the embodiment is as follows:
1. and the waveform components are deployed on the processor cores of GPP and DSP processors and the resource areas of FPGA processors by adopting the on-chip resource deployment technology of the heterogeneous processors, so that the resource utilization rate and the system performance among the heterogeneous resources are improved.
2. By adopting the channel-based waveform deployment technology, each channel is a resource pool, logic devices are divided into different channels, and when the waveform is loaded, waveform components are not matched with all logic devices in the nodes, but are directly matched with the logic devices in the channels, so that the range of searching resources by the waveform components is reduced, and the resource matching efficiency is effectively improved.
3. The health management service is adopted to monitor the health state of the resources, and the waveform is unloaded from the resources in the abnormal state in time and is deployed on the resources in the normal state again, so that the reliability of the system is improved.
It will be appreciated by those of ordinary skill in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing related hardware, where the program may be stored in a computer readable storage medium, where the storage medium may be a magnetic disk, an optical disc, a Read-Only Memory (ROM), a random access Memory (Random Acess Memory, RAM), or the like.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and additions to the present invention may be made by those skilled in the art without departing from the principles of the present invention and such modifications and additions are to be considered as well as within the scope of the present invention.
Claims (8)
1. The utility model provides a heterogeneous distributed embedded software defined radio system, includes main control board and a plurality of signal processing board, its characterized in that: the main control board comprises a GPP processor and an in-board information exchange module; the signal processing board comprises a heterogeneous embedded processor and an on-board information exchange module, wherein the heterogeneous embedded processor comprises a GPP processor and/or a DSP processor and/or an FPGA processor, the heterogeneous embedded processor comprises a plurality of GPP processing cores, the heterogeneous embedded processor DSP processor comprises a plurality of DSP processing cores, and the heterogeneous embedded processor FPGA processor comprises a plurality of FPGA resource areas; the information exchange module in the main control board is connected with the information exchange modules in the signal processing boards through an information bus; the main control board further comprises a waveform deployment module, wherein the waveform deployment module comprises a waveform matching sub-module and a waveform component loading sub-module, the waveform matching sub-module is used for dividing virtual GPP/DSP/FPGA logic equipment into different radio communication channels, a software defined radio waveform component is directly matched with the GPP/DSP/FPGA logic equipment in the corresponding radio communication channel, and the waveform component loading sub-module is used for loading the software defined radio waveform component from the matched GPP/DSP/FPGA logic equipment onto corresponding GPP processing cores of the heterogeneous embedded processor GPP processor and/or DSP processing cores of the DSP processor and/or FPGA resource areas of the heterogeneous embedded processor FPGA processor;
The main control board also comprises a health management service module; the signal processing board also comprises an IPMC module, wherein the IPMC module is a hardware module for acquiring temperature, voltage and current data of the heterogeneous embedded processor of the signal processing board and monitoring the health state; the main control board health management service module is connected with the plurality of signal processing board IPMC modules through a health management bus; the health management service module is used for monitoring health states of the heterogeneous embedded processors of the signal processing boards through the IPMC module, and timely notifying the waveform deployment module to unload the software-defined radio waveform components from the heterogeneous embedded processors of the signal processing boards in abnormal states and reload the software-defined radio waveform components onto the heterogeneous embedded processors of the signal processing boards in normal states.
2. A heterogeneous distributed embedded software defined radio system according to claim 1, wherein: the main control board inboard information exchange module comprises an inboard service exchange sub-module and an inboard Ethernet exchange sub-module, the signal processing board inboard information exchange module comprises an inboard service exchange sub-module and an inboard Ethernet exchange sub-module, the main control board inboard service exchange sub-module is connected with a plurality of signal processing board inboard service exchange sub-modules through service buses, and the main control board inboard Ethernet exchange sub-module is connected with a plurality of signal processing board inboard Ethernet exchange sub-modules through Ethernet buses.
3. A heterogeneous distributed embedded software defined radio system according to claim 1, wherein said main control board GPP processor is controlled by said waveform matching submodule to perform waveform matching by:
P1, creating GPP/DSP/FPGA logic equipment, software defined radio waveforms and waveform components thereof;
P2, creating a plurality of radio communication channels, adding GPP/DSP/FPGA logic equipment into different radio communication channels, and generating a PDD.XML file;
P3, configuring a mapping relation between a software-defined radio waveform and a plurality of radio communication channels to be deployed, and generating an ADD.XML file;
P4, if the step P3 designates that the software defined radio waveform deployment is finished by using a specific radio communication channel, reading the corresponding radio communication channel information in the PDD.XML file, and finishing the matching of the software defined radio waveform component and GPP/DSP/FPGA logic equipment in the radio communication channel; otherwise, reading all radio communication channel information associated with the software defined radio waveform from the ADD.XML file, performing GPP/DSP/FPGA logic device matching on the software defined radio waveform from the first radio communication channel, and performing GPP/DSP/FPGA logic device matching on the next radio communication channel if the matching fails;
and P5, all software-defined radio waveforms in the step P4 can be matched with GPP/DSP/FPGA logic equipment, the software-defined radio waveform matching is successful, and otherwise, the software-defined radio waveform matching fails.
4. A heterogeneous distributed embedded software defined radio system according to claim 3, wherein said main control board GPP processor is controlled by said waveform component loading sub-module to perform waveform component loading by:
J1, creating a software defined radio waveform and a waveform component model thereof, wherein the waveform component model comprises a GPP waveform component, a DSP waveform component and an FPGA waveform component, and configuring GPP processing cores, DSP processing cores or FPGA resource area numbering attributes for the GPP waveform component, the DSP waveform component and the FPGA waveform component, and designating GPP processing cores, DSP processing cores or FPGA resource areas to be loaded and operated by the GPP waveform component, the DSP waveform component and the FPGA waveform component;
J2, generating a software-defined radio waveform description file SAD.XML, wherein coreaffinity elements are used as labels for processing nuclear numbers in the SAD.XML file, and each GPP waveform component, DSP waveform component and FPGA waveform component in the software-defined radio waveform has a coreaffinity value for marking a GPP processing nuclear, DSP processing nuclear or FPGA resource area to be loaded and operated;
j3, when the software defined radio waveform component is loaded, analyzing a software defined radio waveform description file SAD.XML, analyzing the software defined radio waveform component elements, and reading coreaffinity values corresponding to the software defined radio waveform component;
j4, calling GPP/DSP/FPGA logic equipment execution interface, and transmitting coreaffinity values of the software defined radio waveform component as parameters;
j5, GPP/DSP/FPGA logic equipment judges whether coreaffinity values are available or not;
J6, the GPP/DSP/FPGA logic device deploys the software defined radio waveform component to the GPP processing core, the DSP processing core, or the FPGA resource region identified by the coreaffinity values.
5. The heterogeneous distributed embedded software defined radio system of claim 4, wherein in step J6 the GPP logic device deploys software defined radio waveform components to the GPP processing cores: the GPP logic device calls an API interface for setting CPU affinity by the operating system to bind the software defined radio waveform component program with the appointed GPP processing core; after binding through the API interface, the software defined radio waveform component executes on the designated GPP processing core when executing.
6. The heterogeneous distributed embedded software defined radio system of claim 4, wherein the DSP logic device in step J6, when deploying software defined radio waveform components to the DSP processing core, comprises the steps of:
DJ61, DSP logic device sends the software defined radio waveform component and DSP processing core number to DSP processor master control core;
DJ62, the DSP processor master control core stores the software defined radio waveform component file in the shared file area of the DSP processor;
DJ63, the DSP processor master control core sends the file name of the software defined radio waveform component to the DSP processing core designated by the DSP processing core number;
DJ64, the designated DSP processing core copies the software defined radio waveform component files from the DSP shared file area to memory space within the DSP processing core;
DJ65, the designated DSP processing core loads the software defined radio waveform component program into memory for execution.
7. The heterogeneous distributed embedded software defined radio system of claim 4, wherein said FPGA logic device deploys software defined radio waveform components into FPGA resource areas in step J6 comprising the steps of:
FJ61, dividing the resources of the FPGA processor according to the actual functional design of the software-defined radio waveform components, each software-defined radio waveform component delineating a region of resource usage on the FPGA processor according to a specific function, the region being referred to as a reconfigurable region;
FJ62, the same function of the software defined radio waveform components is integrated into a static logic area, each software defined radio waveform component has the same function, and the resource area formed by extracting and integrating the parts is called a static logic area, and the static logic area is unified to realize the same function for all the software defined radio waveform components;
FJ63, locking all logic circuit position information and routing information of a static logic area of the FPGA processor, and not allowing to be modified again;
FJ64, generating an algorithm, resource information and interaction interface information of a static logic area of the FPGA processor into an environment bit file, and configuring an initial environment of the FPGA processor;
FJ65, generating a corresponding software defined radio waveform component bit file by using the algorithm and the resource information of each reconfigurable area of the FPGA processor;
FJ66, FPGA logic device transmits the software defined radio waveform components to the FPGA processor reconfigurable region;
FJ67, FPGA processor runs software defined radio waveform component programs for the reconfigurable area.
8. A heterogeneous distributed embedded software defined radio system according to any of claims 1 to 7, wherein: software defined radio waveform deployment for the SRTF standard.
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