CN116166610A - SCA waveform dynamic local reconfiguration method and device based on heterogeneous multi-core SOC processor - Google Patents
SCA waveform dynamic local reconfiguration method and device based on heterogeneous multi-core SOC processor Download PDFInfo
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Abstract
The invention discloses a method and a device for dynamically and locally reconfiguring SCA waveforms based on heterogeneous multi-core SOC processors, wherein the method comprises the following steps: generating netlist files according to HDL codes of writing a fixed interface functional module and a dynamic local reconfiguration functional module respectively; partitioning and distributing FPGA resources to the fixed interface functional module and the dynamic local reconfiguration functional module, and creating corresponding time sequence constraint files; and comprehensively wiring all the partitions of the fixed interface functional module and the dynamic local reconfiguration functional module to generate a global bit file and a local bit file. Downloading a global bit file through an interface between the ARM processor and the FPGA after the system is powered on; when the SCA waveform is switched, the corresponding local bit file is selected to be downloaded, so that the switching of different SCA waveforms is realized. The invention improves the development and debugging efficiency of FPGA software, reduces the time for dynamically loading the FPGA program by the software radio equipment, accelerates the speed of switching the SCA waveform by loading the equipment, reduces the internal resource consumption of the FPGA and reduces the power consumption.
Description
Technical Field
The invention relates to the technical field of multi-core processors, in particular to a method and a device for SCA waveform dynamic local reconfiguration based on a heterogeneous multi-core SOC processor.
Background
United states joint tactical radio system (Joint Tactical Tadio System, JTRS) joint project office (Joint Program Executive Office, JPEO) promulgates a software communications architecture (Software Communications Architecture, SCA) aimed at configuring hardware platforms, software technologies, and communications technologies as needed into different functional communications systems. SCA defines an open architecture using an object-oriented design approach, and proposes a standardized approach to instantiating, configuring and managing waveform applications running on a radio hardware platform. The SCA decouples the waveform software from the specific platform software and hardware, and operates different software waveforms on a general hardware platform to realize different communication devices, so that the reuse of the waveform software is promoted, the development cost is reduced to the maximum extent, and the flexibility, the universality, the reconfigurability and the interoperability of the communication system can be effectively improved. Therefore, for waveforms running on the FPGA device, the FPGA program function can be dynamically and rapidly switched and deployed, which is an important technical index for realizing the software radio equipment, and fully embodies the capability of running multiple sets of waveforms of the software radio on one hardware platform.
The FPGA has the characteristics of programmable configuration and parallel computation, and is generally used in software radio equipment to complete hardware interface configuration of a physical layer, rapid processing algorithms, modulation and demodulation of different modulation modes, digital frequency conversion and encoding and decoding processes. However, since the current software radio switches FPGA programs all by replacing the whole FPGA program, it takes a long time to switch FPGA programs. In addition, in the development process of the FPGA program, the function of the local module is changed, the whole FPGA project is required to be compiled again and synthesized, the development and debugging time is increased, and the transplanting of the software function is not facilitated.
Disclosure of Invention
The invention aims to solve the problems of the prior art and provide a method and a device for dynamically and locally reconfiguring SCA waveforms based on a heterogeneous multi-core SOC processor, which improve the development and debugging efficiency of FPGA software, reduce the time for dynamically loading FPGA programs by software radio equipment, accelerate the speed of switching SCA waveforms by equipment loading, reduce the consumption of internal resources of the FPGA and reduce the power consumption.
In order to achieve the above purpose of the present invention, the following technical scheme is adopted:
a method for dynamically and locally reconfiguring SCA waveforms based on heterogeneous multi-core SOC processors comprises the following steps:
s1: respectively writing HDL codes of a fixed interface function module at the FPGA side and HDL codes of a dynamic local reconfiguration function module, and comprehensively generating a netlist file of the fixed interface function module at the FPGA side and a netlist file of the dynamic local reconfiguration function module according to the corresponding HDL codes;
s2: partitioning and distributing FPGA resources to a fixed interface functional module and a dynamic local reconfiguration functional module on the FPGA respectively, and creating time sequence constraint files of the fixed interface functional module and the dynamic local reconfiguration functional module according to the corresponding partitioning and distributing FPGA resources respectively;
s3: carrying out layout wiring configuration on each partition of the fixed interface functional module and the dynamic local reconfiguration functional module by utilizing the corresponding netlist file and the time sequence constraint file; generating a global bit file of the fixed interface function module and a local bit file of the dynamic local reconfiguration function module based on the corresponding layout wiring;
s4: after the heterogeneous multi-core SOC processor is powered on and started, downloading a global bit file through an interface between an ARM processor and an FPGA on the heterogeneous multi-core SOC processor; when the SCA waveform is switched, the local bit file of the corresponding dynamic local reconfiguration function module is selected to be downloaded, so that the rapid switching of different SCA waveform functions is realized.
Preferably, the fixed interface function module comprises an MHAL/MOCB FPGA interface and a peripheral hardware interface, and on the FPGA side, the MHAL/MOCB FPGA interface and the peripheral hardware interface are both defined as the fixed interface function module.
Further, the SCA waveform related functional module is defined as a dynamic local reconfiguration functional module.
Further, the function module related to the SCA waveform comprises modulation, demodulation, digital frequency conversion and encoding and decoding processing; the corresponding dynamic local reconfiguration function module comprises modulation, demodulation, digital frequency conversion and encoding and decoding processing related to the SCA waveform.
Preferably, vivado software is used as a development tool, and the specific development process is as follows: opening Vivado software, creating a new project according to the model of the heterogeneous multi-core SOC processor, and enabling Partial Reconfiguration; the development of the steps S1 to S3 is realized by using Vivado software.
Further, the heterogeneous multi-core SOC processor selects Xilinx Zynq7000 series chips.
A device based on SCA waveform dynamic local reconfiguration of heterogeneous multi-core SOC processor comprises
The synthesis module is used for synthesizing and generating a netlist file of the fixed interface function module at the FPGA side and a netlist file of the dynamic local reconfiguration function module according to HDL codes of the fixed interface function module at the FPGA side and HDL codes of the dynamic local reconfiguration function module;
the time sequence constraint module is used for partitioning and distributing FPGA resources according to the fixed interface functional module and the dynamic local reconfiguration functional module on the FPGA, and creating time sequence constraint files of the fixed interface functional module and the dynamic local reconfiguration functional module;
the bit file generating module is used for carrying out layout and wiring configuration on each partition of the fixed interface functional module and the dynamic local reconfiguration functional module according to the corresponding netlist file and the time sequence constraint file; generating a global bit file of the fixed interface function module and a local bit file of the dynamic local reconfiguration function module based on the corresponding layout wiring;
the downloading updating module is used for downloading the global bit file through an interface between an ARM processor and the FPGA on the heterogeneous multi-core SOC processor after the heterogeneous multi-core SOC processor is electrified and started;
and the updating switching module is used for selecting and downloading the local bit file corresponding to the dynamic local reconfiguration function module when the SCA waveform is switched so as to realize the rapid switching of different SCA waveform functions.
Preferably, the method further comprises a definition module, wherein the definition module is used for defining the MHAL/MOCB FPGA interface and the peripheral hardware interface as fixed interface function modules, and the function module related to the SCA waveform is defined as a dynamic local reconfiguration function module.
A computer system comprising a memory, a processor and a computer program stored on the memory and executable on the processor, said processor implementing the steps of the method of dynamic local reconfiguration of SCA waveforms based on heterogeneous multi-core SOC processors as described herein when said computer program is executed by said processor.
A computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of dynamic local reconfiguration of SCA waveforms based on heterogeneous multi-core SOC processors as described.
The beneficial effects of the invention are as follows:
the FPGA program conforming to the SCA standard is developed by creatively adopting the FPGA dynamic local reconfiguration method, the development and debugging efficiency of FPGA software is improved, the time for switching the FPGA program of the software radio equipment is reduced, the loading and switching waveform speed of the equipment is accelerated, the consumption of internal resources of the FPGA is reduced, and the power consumption is reduced.
When the FPGA program is designed and developed, the MHAL/MOCB FPGA interface and the peripheral hardware control interface are defined as fixed interface function modules, and the function modules (modulation, demodulation, digital frequency conversion and encoding and decoding processing) related to the SCA waveform are defined as dynamic local reconfiguration function modules.
Drawings
FIG. 1 is a flow chart of a method for dynamic local reconfiguration of SCA waveforms based on a heterogeneous multi-core SOC processor according to the present invention.
FIG. 2 is a schematic diagram of the definition of the fixed interface function module, the dynamic local reconfiguration function module of the present invention.
Detailed Description
The invention is described in detail below with reference to the drawings and the detailed description.
Example 1
In this embodiment, vivado software is used as a development tool, and the specific development process is as follows: and opening Vivado software, creating a new project according to the model of the heterogeneous multi-core SOC processor, and enabling Partial Reconfiguration. The heterogeneous multi-core SOC processor described in this embodiment selects the Xilinx Zynq7100 serial chip.
As shown in fig. 1, the method for dynamically and locally reconfiguring the SCA waveform of the heterogeneous multi-core SOC processor is developed by using Vivado software, and the steps of the method are as follows:
s1: respectively writing HDL codes of a fixed interface function module at the FPGA side and HDL codes of a dynamic local reconfiguration function module, and comprehensively generating a netlist file of the fixed interface function module at the FPGA side and a netlist file of the dynamic local reconfiguration function module by adopting Vivado software according to the corresponding HDL codes;
s2: partitioning and distributing FPGA resources to a fixed interface functional module and a dynamic local reconfiguration functional module on the FPGA by using Vivado software, and respectively creating time sequence constraint files of the fixed interface functional module and the dynamic local reconfiguration functional module according to the corresponding partitioning and distributing FPGA resources;
s3: adopting Vivado software to perform layout and wiring configuration on each partition of the fixed interface functional module and the dynamic local reconfiguration functional module by using a corresponding netlist file and a time sequence constraint file; generating a global bit file of the fixed interface function module and a local bit file of the dynamic local reconfiguration function module based on the corresponding layout wiring;
s4: after the heterogeneous multi-core SOC processor is powered on and started, downloading a global bit file through an interface between an ARM processor and an FPGA on the heterogeneous multi-core SOC processor; when the SCA waveform is switched, the local bit file of the corresponding dynamic local reconfiguration function module is selected to be downloaded, so that the rapid switching of different SCA waveform functions is realized.
In a specific embodiment, as shown in fig. 2, the fixed interface functional module includes an MHAL/MOCB FPGA interface and a peripheral hardware interface, where the MHAL/MOCB FPGA interface and the peripheral hardware interface are both defined as the fixed interface functional module on the FPGA side.
In a specific embodiment, the SCA waveform related functional module is defined as a dynamic local reconfiguration functional module.
In a specific embodiment, the function module related to the SCA waveform includes modulation, demodulation, digital frequency conversion and encoding and decoding processes; the corresponding dynamic local reconfiguration function module comprises modulation, demodulation, digital frequency conversion and encoding and decoding processing related to the SCA waveform.
As shown in FIG. 2, the peripheral hardware interface of the FPGA on a hardware platform is fixed, the MHAL/MOCB FPGA interface based on the SCA uses a unified interface, and the change is a program function module related to the SCA waveform of the FPGA side. The logic functions of the corresponding partitions are dynamically modified by downloading the local bit files on the FPGA side, and meanwhile, the logic functions of the rest partitions of the FGPA continuously run without interruption.
The embodiment can improve the efficiency of developing the FPGA software conforming to the SCA standard, reduce the time for loading the FPGA bit file when the software radio equipment is dynamically switched, improve the speed of loading the switching waveform of the equipment, reduce the use of the internal resources of the FPGA and reduce the power consumption.
Example 2
An apparatus for dynamic local reconfiguration of SCA waveforms based on heterogeneous multi-core SOC processors, comprising:
the synthesis module is used for synthesizing and generating a netlist file of the fixed interface function module at the FPGA side and a netlist file of the dynamic local reconfiguration function module according to HDL codes of the fixed interface function module at the FPGA side and HDL codes of the dynamic local reconfiguration function module;
the time sequence constraint module is used for partitioning and distributing FPGA resources according to the fixed interface functional module and the dynamic local reconfiguration functional module on the FPGA, and creating time sequence constraint files of the fixed interface functional module and the dynamic local reconfiguration functional module;
the bit file generating module is used for carrying out layout and wiring configuration on each partition of the fixed interface functional module and the dynamic local reconfiguration functional module according to the corresponding netlist file and the time sequence constraint file; generating a global bit file of the fixed interface function module and a local bit file of the dynamic local reconfiguration function module based on the corresponding layout wiring;
the downloading updating module is used for downloading the global bit file through an interface between an ARM processor and the FPGA on the heterogeneous multi-core SOC processor after the heterogeneous multi-core SOC processor is electrified and started;
and the updating switching module is used for selectively downloading the local bit file of the corresponding dynamic local reconfiguration function module when the SCA waveform is switched, so as to realize the switching of different waveform functions.
Preferably, the method further comprises a definition module, wherein the definition module is used for defining the MHAL/MOCB FPGA interface and the peripheral hardware interface as fixed interface function modules, and the function module related to the SCA waveform is defined as a dynamic local reconfiguration function module.
In a specific embodiment, the function module related to the SCA waveform includes modulation, demodulation, digital frequency conversion and encoding and decoding processes; the corresponding dynamic local reconfiguration function module comprises modulation, demodulation, digital frequency conversion and encoding and decoding processing related to the SCA waveform.
As shown in FIG. 2, the peripheral hardware interface of the FPGA on a hardware platform is fixed, the MHAL/MOCB FPGA interface based on the SCA uses a unified interface, and the change is a program function module related to the SCA waveform of the FPGA side. The logic functions of the corresponding partitions are dynamically modified by downloading the local bit files on the FPGA side, and meanwhile, the logic functions of the rest partitions of the FGPA continuously run without interruption.
The embodiment can improve the efficiency of developing the FPGA software conforming to the SCA standard, reduce the time for loading the FPGA bit file when the software radio equipment is dynamically switched, improve the speed of loading the switching waveform of the equipment, reduce the use of the internal resources of the FPGA and reduce the power consumption.
Example 3
A computer system comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the method for implementing the dynamic local reconfiguration of the SCA waveforms of the heterogeneous multi-core based SOC processor when the processor executes the computer program comprises the steps of:
s1: respectively writing HDL codes of a fixed interface function module at the FPGA side and HDL codes of a dynamic local reconfiguration function module, and comprehensively generating a netlist file of the fixed interface function module at the FPGA side and a netlist file of the dynamic local reconfiguration function module by adopting Vivado software according to the corresponding HDL codes;
s2: partitioning and distributing FPGA resources to a fixed interface functional module and a dynamic local reconfiguration functional module on the FPGA by using Vivado software, and respectively creating time sequence constraint files of the fixed interface functional module and the dynamic local reconfiguration functional module according to the corresponding partitioning and distributing FPGA resources;
s3: adopting Vivado software to perform layout and wiring configuration on each partition of the fixed interface functional module and the dynamic local reconfiguration functional module by using a corresponding netlist file and a time sequence constraint file; generating a global bit file of the fixed interface function module and a local bit file of the dynamic local reconfiguration function module based on the corresponding layout wiring;
s4: after the heterogeneous multi-core SOC processor is powered on and started, downloading a global bit file through an interface between an ARM processor and an FPGA on the heterogeneous multi-core SOC processor; when the SCA waveform is switched, the local bit file of the corresponding dynamic local reconfiguration function module is selected to be downloaded, so that the rapid switching of different SCA waveform functions is realized.
Where the memory and the processor are connected by a bus, the bus may comprise any number of interconnected buses and bridges, the buses connecting the various circuits of the one or more processors and the memory together. The bus may also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or may be a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor is transmitted over the wireless medium via the antenna, which further receives the data and transmits the data to the processor.
Example 4
A computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the method steps of dynamically and locally reconfiguring SCA waveforms based on a heterogeneous multi-core SOC processor as described below:
s1: respectively writing HDL codes of a fixed interface function module at the FPGA side and HDL codes of a dynamic local reconfiguration function module, and comprehensively generating a netlist file of the fixed interface function module at the FPGA side and a netlist file of the dynamic local reconfiguration function module by adopting Vivado software according to the corresponding HDL codes;
s2: partitioning and distributing FPGA resources to a fixed interface functional module and a dynamic local reconfiguration functional module on the FPGA by using Vivado software, and respectively creating time sequence constraint files of the fixed interface functional module and the dynamic local reconfiguration functional module according to the corresponding partitioning and distributing FPGA resources;
s3: adopting Vivado software to perform layout and wiring configuration on each partition of the fixed interface functional module and the dynamic local reconfiguration functional module by using a corresponding netlist file and a time sequence constraint file; generating a global bit file of the fixed interface function module and a local bit file of the dynamic local reconfiguration function module based on the corresponding layout wiring;
s4: after the heterogeneous multi-core SOC processor is powered on and started, downloading a global bit file through an interface between an ARM processor and an FPGA on the heterogeneous multi-core SOC processor; when the SCA waveform is switched, the local bit file of the corresponding dynamic local reconfiguration function module is selected to be downloaded, so that the rapid switching of different SCA waveform functions is realized.
That is, it will be understood by those skilled in the art that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, where the program includes several instructions for causing a device (which may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps in the methods of the embodiments described herein. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
It is to be understood that the above examples of the present invention are provided by way of illustration only and not by way of limitation of the embodiments of the present invention. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the invention are desired to be protected by the following claims.
Claims (10)
1. A method for dynamically and locally reconfiguring SCA waveforms based on heterogeneous multi-core SOC processors is characterized by comprising the following steps: the method comprises the following steps:
s1: respectively writing HDL codes of a fixed interface function module at the FPGA side and HDL codes of a dynamic local reconfiguration function module, and comprehensively generating a netlist file of the fixed interface function module at the FPGA side and a netlist file of the dynamic local reconfiguration function module according to the corresponding HDL codes;
s2: partitioning and distributing FPGA resources to a fixed interface functional module and a dynamic local reconfiguration functional module on the FPGA respectively, and creating time sequence constraint files of the fixed interface functional module and the dynamic local reconfiguration functional module according to the corresponding partitioning and distributing FPGA resources respectively;
s3: carrying out layout wiring configuration on each partition of the fixed interface functional module and the dynamic local reconfiguration functional module by utilizing the corresponding netlist file and the time sequence constraint file; generating a global bit file of the fixed interface function module and a local bit file of the dynamic local reconfiguration function module based on the corresponding layout wiring;
s4: after the heterogeneous multi-core SOC processor is powered on and started, downloading a global bit file through an interface between an ARM processor and an FPGA on the heterogeneous multi-core SOC processor; when the SCA waveform is switched, the local bit file of the corresponding dynamic local reconfiguration function module is selected to be downloaded, so that the rapid switching of different SCA waveform functions is realized.
2. The method for dynamic local reconfiguration of SCA waveforms based on heterogeneous multi-core SOC processor of claim 1, wherein: the fixed interface functional module comprises an MHAL/MOCB FPGA interface and a peripheral hardware interface, and the MHAL/MOCB FPGA interface and the peripheral hardware interface are defined as the fixed interface functional module at the FPGA side.
3. The method for dynamic local reconfiguration of SCA waveforms based on heterogeneous multi-core SOC processor of claim 1, wherein: the SCA waveform related functional module is defined as a dynamic local reconfiguration functional module.
4. A method for dynamic local reconfiguration of SCA waveforms based on heterogeneous multi-core SOC processors as claimed in claim 3, wherein:
the function module related to the SCA waveform comprises modulation, demodulation, digital frequency conversion and encoding and decoding processing; the corresponding dynamic local reconfiguration function module comprises modulation, demodulation, digital frequency conversion and encoding and decoding processing related to the SCA waveform.
5. The method for dynamic local reconfiguration of SCA waveforms based on heterogeneous multi-core SOC processor of claim 1, wherein: vivado software is adopted as a development tool, and the specific development process is as follows: opening Vivado software, creating a new project according to the model of the heterogeneous multi-core SOC processor, and enabling Partial Reconfiguration; the development of the steps S1 to S3 is realized by using Vivado software.
6. The method for dynamic local reconfiguration of SCA waveforms based on heterogeneous multi-core SOC processor of claim 5, wherein: the heterogeneous multi-core SOC processor selects Xilinx Zynq7000 series chips.
7. The utility model provides a device based on heterogeneous multicore SOC treater SCA waveform dynamic local reconfiguration which characterized in that: comprising
The synthesis module is used for synthesizing and generating a netlist file of the fixed interface function module at the FPGA side and a netlist file of the dynamic local reconfiguration function module according to HDL codes of the fixed interface function module at the FPGA side and HDL codes of the dynamic local reconfiguration function module;
the time sequence constraint module is used for partitioning and distributing FPGA resources according to the fixed interface functional module and the dynamic local reconfiguration functional module on the FPGA, and creating time sequence constraint files of the fixed interface functional module and the dynamic local reconfiguration functional module;
the bit file generating module is used for carrying out layout and wiring configuration on each partition of the fixed interface functional module and the dynamic local reconfiguration functional module according to the corresponding netlist file and the time sequence constraint file; generating a global bit file of the fixed interface function module and a local bit file of the dynamic local reconfiguration function module based on the corresponding layout wiring;
the downloading updating module is used for downloading the global bit file through an interface between an ARM processor and the FPGA on the heterogeneous multi-core SOC processor after the heterogeneous multi-core SOC processor is electrified and started;
and the updating switching module is used for selectively downloading the local bit file of the corresponding dynamic local reconfiguration function module when the SCA waveform is switched, so as to realize the switching of different waveform functions.
8. The heterogeneous multi-core SOC processor SCA waveform dynamic local reconfiguration based apparatus of claim 7 wherein: the system also comprises a definition module which is used for defining the MHAL/MOCB FPGA interface and the peripheral hardware interface as fixed interface function modules and defining the function module related to the SCA waveform as a dynamic local reconfiguration function module.
9. A computer system comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized by: the processor, when executing the computer program, performs the steps of the method according to any one of claims 1 to 6.
10. A computer-readable storage medium having stored thereon a computer program, characterized by: the computer program, when executed by a processor, performs the steps of the method according to any one of claims 1 to 6.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116521614A (en) * | 2023-07-05 | 2023-08-01 | 西安智多晶微电子有限公司 | FPGA dynamic local reconfiguration method |
| CN117591454A (en) * | 2024-01-19 | 2024-02-23 | 成都谐盈科技有限公司 | System and method for realizing mocb on EMif bus FPGA |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116521614A (en) * | 2023-07-05 | 2023-08-01 | 西安智多晶微电子有限公司 | FPGA dynamic local reconfiguration method |
| CN116521614B (en) * | 2023-07-05 | 2023-09-15 | 西安智多晶微电子有限公司 | FPGA dynamic local reconfiguration method |
| CN117591454A (en) * | 2024-01-19 | 2024-02-23 | 成都谐盈科技有限公司 | System and method for realizing mocb on EMif bus FPGA |
| CN117591454B (en) * | 2024-01-19 | 2024-04-23 | 成都谐盈科技有限公司 | Mocb implementation system and method based on emif bus FPGA |
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