CN117650701B - Step-down circuit - Google Patents
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Abstract
The application discloses a step-down circuit. The step-down circuit includes: the power conversion sub-circuit is used for performing buck conversion on the input direct current level and outputting the buck conversion; the first end and the second end of the additional current feedback module are electrically connected with the power conversion sub-circuit, and the additional current feedback module is used for measuring inductor information of the power conversion sub-circuit; and the first input end and the second input end of the offset elimination sub-circuit are respectively and electrically connected with the additional current feedback module, the output end of the offset elimination sub-circuit is electrically connected with the power conversion sub-circuit, the first input end and the second input end of the offset elimination sub-circuit have voltage information with the same direct current quantity, and the voltage information with the same direct current quantity is the direct current offset voltage of the power conversion sub-circuit. The embodiment of the application can improve the accuracy of the output voltage, save the area of a chip and reduce the complexity of circuit design.
Description
Technical Field
The application belongs to the technical field of power supplies, and particularly relates to a voltage-reducing circuit.
Background
Typically, a Constant On Time (COT) converter requires a large capacitor Equivalent Series Resistance (ESR) to provide sufficient inductor current information. The chip type multilayer ceramic capacitor (Multi-LAYER CERAMIC Capacitors, MLCC) adopted by the existing BUCK circuit (BUCK) has small ESR, the small ESR value can lead to larger output ripple voltage, and the increase of the output ripple voltage can lead to unstable COT converter. To solve the problem of instability of the COT converter, an additional current feedback loop technique is introduced. However, the additional current feedback loop technique may cause an offset voltage to be generated at the dc level of the output voltage of the BUCK circuit, thereby affecting the accuracy of the BUCK circuit.
In the related art, two low-pass filters are added on the basis of an additional current feedback loop technology to eliminate offset voltage.
However, the low-pass filter needs to adopt a large capacitance and a large resistance, so that the whole area occupied by the chip is large, and meanwhile, the voltage needs to be subjected to multiple filtering and superposition to achieve the purpose of offset elimination, so that the complexity of circuit design is increased.
Disclosure of Invention
The embodiment of the application provides a step-down circuit, which can improve the accuracy of output voltage, save the area of a chip and reduce the complexity of circuit design.
In a first aspect, an embodiment of the present application provides a step-down circuit, including: the power conversion sub-circuit is used for performing buck conversion on the input direct current level and outputting the buck conversion; the first end and the second end of the additional current feedback module are electrically connected with the power conversion sub-circuit, and the additional current feedback module is used for measuring inductor information of the power conversion sub-circuit; and the first input end and the second input end of the offset elimination sub-circuit are respectively and electrically connected with the additional current feedback module, the output end of the offset elimination sub-circuit is electrically connected with the power conversion sub-circuit, the first input end and the second input end of the offset elimination sub-circuit have voltage information with the same direct current quantity, and the voltage information with the same direct current quantity is the direct current offset voltage of the power conversion sub-circuit.
According to an embodiment of the first aspect of the present application, the offset cancellation subcircuit includes: the input end of the offset voltage sampling module is electrically connected with the power conversion sub-circuit, and the offset voltage sampling module is used for collecting the voltage of the additional current feedback module, wherein the voltage of the additional current feedback module comprises direct current offset voltage; the first input end of the adder is electrically connected with the offset voltage sampling module, the second input end of the adder is used for receiving the reference voltage, and the adder is used for summing the reference voltage and the voltage of the additional current feedback module to obtain a first voltage; and the second input end of the comparison module is used for receiving a second voltage, and the comparison module responds to the first voltage being larger than the second voltage and outputs a high level.
According to any of the foregoing embodiments of the first aspect of the present application, the power conversion sub-circuit includes: the first end of the first P-type transistor is electrically connected with the power supply end, and the first P-type transistor is turned on when responding to the control end of the first P-type transistor to receive a low level; the first end of the logic driving module is electrically connected with the control end of the first P-type transistor; the control end of the first N-type transistor is electrically connected with the second end of the logic driving module, the first end of the first N-type transistor is electrically connected with the second end of the first P-type transistor, and the second end of the first N-type transistor is electrically connected with the grounding end; and the constant conduction time module is used for responding to the output high level of the comparison module to generate constant conduction time.
According to any of the foregoing embodiments of the first aspect of the present application, the power conversion sub-circuit further includes: the first end of the inductor is electrically connected with the second end of the first P-type transistor and the first end of the additional current feedback module; the first end of the inductor equivalent series resistor is electrically connected with the second end of the inductor, and the second end of the inductor equivalent series resistor is electrically connected with the second end of the additional current feedback module; the first end of the first capacitor is electrically connected with the power supply end; the first end of the first capacitor equivalent series resistor is electrically connected with the second end of the inductor equivalent series resistor, and the second end of the first capacitor equivalent series resistor is electrically connected with the second end of the first capacitor; and the first end of the load is electrically connected with the second end of the equivalent series resistance of the inductor, and the second end of the load is electrically connected with the grounding end.
According to any of the foregoing embodiments of the first aspect of the present application, the offset voltage sampling module includes: the first end of the second P-type transistor is electrically connected with the power supply end and the second end of the first P-type transistor, and the control end of the second P-type transistor is electrically connected with the grounding end; the positive input end of the operational amplifier is electrically connected with the first end of the first P-type transistor, the negative input end of the operational amplifier is electrically connected with the second end of the second P-type transistor, and the operational amplifier is used for making the input voltage of the positive input end and the input voltage of the negative input end equal; the control end of the second N-type transistor is electrically connected with the output end of the operational amplifier, the first end of the second N-type transistor is electrically connected with the second end of the second P-type transistor, the second end of the second N-type transistor is electrically connected with the second input end of the adder, and the second end of the second N-type transistor is used for outputting the voltage of the additional current feedback module; the first end of the resistor is electrically connected with the second end of the second N-type transistor, and the second end of the resistor is electrically connected with the grounding end and the second end of the first N-type transistor.
According to any of the foregoing embodiments of the first aspect of the present application, a ratio of a width-to-length ratio of a channel region of the first P-type transistor to a width-to-length ratio of a channel region of the second P-type transistor is equal to a predetermined multiple, and a ratio of a resistance of the resistor to a resistance of an equivalent series resistance of the inductor is equal to the predetermined multiple.
According to any of the foregoing embodiments of the first aspect of the present application, the additional current feedback module includes: the negative plate of the second capacitor is electrically connected with the second end of the equivalent series resistance of the inductor, and the positive plate of the second capacitor is electrically connected with the second input end of the comparison module; and the second end of the second capacitor equivalent series resistor is electrically connected with the positive plate of the second capacitor.
According to any of the foregoing embodiments of the first aspect of the present application, the comparing module includes: the control end of the first transistor is used for receiving bias voltage, and the first end of the first transistor is electrically connected with the power supply end; the control end of the second transistor is used for receiving the bias voltage, and the first end of the second transistor is electrically connected with the power supply end and the first end of the first transistor; a third transistor, a control terminal of which is used for receiving the voltage of the additional current feedback module, and a first terminal of which is electrically connected with a second terminal of the first transistor; a fourth transistor, a control terminal of which is used for receiving the output voltage of the power conversion subcircuit, and a first terminal of which is electrically connected with a second terminal of the first transistor; a fifth transistor, a control terminal of which is used for receiving a reference voltage, and a first terminal of which is electrically connected with a second terminal of the second transistor; a sixth transistor, a control terminal of the sixth transistor being electrically connected to the additional current feedback module, a first terminal of the sixth transistor being electrically connected to the second terminal of the second transistor, the second terminal of the sixth transistor being electrically connected to the second terminal of the fourth transistor; the first end of the first current mirror module is electrically connected with the second end of the third transistor, the second end of the first current mirror module is electrically connected with the second end of the fourth transistor, and the third end of the first current mirror module is electrically connected with the grounding end; the first end of the second current mirror module is electrically connected with the second end of the fifth transistor and the second end of the third transistor, the second end of the second current mirror module is electrically connected with the second end of the sixth transistor, and the third end of the second current mirror module is electrically connected with the grounding end; and the first end of the inverter is electrically connected with the second end of the second current mirror module and the second end of the sixth transistor, and the inverter outputs a high level in response to receiving a low level and outputs a low level in response to receiving a high level.
According to any of the foregoing embodiments of the first aspect of the present application, the first current mirror module includes: a seventh transistor, a first end of which is electrically connected with the control end of the seventh transistor and a second end of the third transistor, and a second end of which is electrically connected with the grounding end; and the first end of the eighth transistor is electrically connected with the second end of the fourth transistor, the control end of the eighth transistor is electrically connected with the control end of the seventh transistor, and the second end of the eighth transistor is electrically connected with the grounding end.
According to any of the foregoing embodiments of the first aspect of the present application, the second current mirror module includes: a ninth transistor, a first end of which is electrically connected to the control end of the ninth transistor and a second end of the fifth transistor, and a second end of which is electrically connected to the ground end; and a tenth transistor, a control terminal of the tenth transistor is electrically connected to a control terminal of the ninth transistor, a first terminal of the tenth transistor is electrically connected to a first terminal of the inverter, and a second terminal of the tenth transistor is electrically connected to a ground terminal.
In the existing step-down circuit, the output end voltage of the power conversion subcircuit has direct current offset due to the existence of an additional current feedback module. According to the embodiment of the application, the first input end and the second input end of the offset cancellation sub-circuit are electrically connected with the additional current feedback module, the output voltage direct current offset of the power conversion sub-circuit is introduced into the first input end and the second input end of the offset cancellation sub-circuit, the direct current offset of the two input ends are mutually offset, and the output precision of the step-down circuit is improved. And secondly, the step-down circuit eliminates offset voltage and does not use a low-pass filter to filter the offset of direct current, so that the chip area is reduced and the complexity of circuit design is reduced.
Drawings
In order to more clearly illustrate the technical solution of the embodiments of the present application, the drawings that are needed to be used in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.
Fig. 1 is a circuit schematic diagram of a step-down circuit in the related art;
Fig. 2 is a schematic circuit diagram of a step-down circuit according to an embodiment of the present application;
Fig. 3 is a schematic diagram of another voltage step-down circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a step-down circuit according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a step-down circuit according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a step-down circuit according to an embodiment of the present application;
Fig. 7 is a schematic circuit diagram of a step-down circuit according to an embodiment of the present application.
Detailed Description
Features and exemplary embodiments of various aspects of the present application will be described in detail below, and in order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail below with reference to the accompanying drawings and the detailed embodiments. It should be understood that the particular embodiments described herein are meant to be illustrative of the application only and not limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In embodiments of the present application, the term "electrically connected" may refer to two components being directly electrically connected, or may refer to two components being electrically connected via one or more other components.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Accordingly, it is intended that the present application covers the modifications and variations of this application provided they come within the scope of the appended claims (the claims) and their equivalents. The embodiments provided by the embodiments of the present application may be combined with each other without contradiction.
Before describing the technical solution provided by the embodiments of the present application, in order to facilitate understanding of the embodiments of the present application, the present application firstly specifically describes the problems existing in the related art:
The DC-DC converter maintains a stable output voltage by controlling a ratio of on and off times of switching transistors, is a high-frequency power conversion device, and is a switching power supply for realizing a stable output voltage step-down, and is widely used because of its high conversion efficiency and wide output range.
A BUCK-type DC-DC converter, namely a BUCK-type circuit, comprises a COT converter, wherein the COT converter is operated in a continuous conduction mode (Continuous Conduction Mode, CCM) under heavy load to keep high efficiency, and is operated in an intermittent conduction mode (Discontinuous Conduction Mode, DCM) under light load to reduce conduction loss through frequency reduction. And the COT converter requires a large ESR to provide sufficient inductor current information to avoid instability when operating in CCM. But large ESR values can result in excessively high output ripple voltages.
The chip type multi-layer ceramic capacitor (MLCC) used in the prior art has a small ESR and size, and provides high power efficiency and reduced PCB area if it is used in the COT converter to reduce the output ripple voltage, but causes instability in the operation of the COT converter in CCM due to the small ESR.
In order to solve the problem that the COT converter is unstable when the capacitor is in a small ESR state, an additional current feedback loop technology is proposed, inductor information is sensed through additional current feedback and is injected into a feedback loop, so that the inductor current information is decoupled from the ESR state, and the problem that the COT converter of the small ESR capacitor is unstable is solved. However, the introduction of the additional current feedback loop technology causes the additional current feedback loop technology to generate an offset voltage on the output voltage dc level of the BUCK circuit when the load changes, thereby affecting the output accuracy of the BUCK circuit.
In the related art, in order to improve the output accuracy of the BUCK circuit, the output voltage of the BUCK circuit is subjected to a low-pass filtering operation, thereby improving the output accuracy. Fig. 1 is a circuit schematic of a buck-type circuit in the related art, and as shown in fig. 1, the buck-type circuit may include a power conversion sub-circuit 101, an additional current feedback module 102, and an offset cancellation sub-circuit 103. The offset canceling sub-circuit 103 may include a comparator EA ', a first low pass filter LPF1, a second low pass filter LPF2, a first operator A1', a second operator A2', and a third operator A3'.
The output V OUT of the power conversion sub-circuit 101 may be electrically connected to the first low-pass filter LPF1 for separating the dc voltage component V OUT-DC of V OUT from the ac voltage component V OUT-AC of V OUT, the additional current feedback module 102 is electrically connected to the power conversion sub-circuit 101 for decoupling the inductor current information in the power conversion sub-circuit 101 from the ESR, and the offset cancellation sub-circuit 103 is electrically connected to the power conversion sub-circuit 101 and the additional current feedback module 102 for canceling the dc offset voltage due to the additional current feedback module 102.
As can be seen from fig. 1, in the related art, the output voltage V OUT at the output end of the power conversion sub-circuit 101 is separated into a direct current voltage component V OUT-DC and an alternating current voltage component V OUT-AC by a first low-pass filter LPF1, the output voltage V S 'in the additional current feedback module 102 is low-pass filtered by a second low-pass filter LPF2 to obtain a direct current voltage component V c of V S', and V OUT-DC、Vc and a reference voltage V REF 'are generated by a second arithmetic unit A2' to be used as a standard voltage for comparison; and the output voltages V S 'and V OUT-AC of the additional current feedback module 102 are calculated by the third arithmetic unit A3' to obtain a comparison voltage V A, and V A and V B 'are compared by the comparator EA', so as to eliminate the dc offset voltage generated by the additional current feedback module 102.
As can be seen from fig. 1, in the related art, the dc offset voltage in the additional current feedback module 102 is mainly eliminated by the first low pass filter LPF1 and the second low pass filter LPF 2. Because the low-pass filter needs to adopt a large capacitor and a resistor to achieve the filtering effect, the method greatly increases the chip area, and under the development trend of high integration, the large capacitor and the resistor are not easy to integrate into the chip, and are not suitable for large-scale application. Meanwhile, the voltage needs to be subjected to multiple filtering and superposition to achieve the purpose of offset elimination, and the complexity of circuit design is increased.
In view of the above-mentioned studies of the inventors, an embodiment of the present application provides a step-down circuit capable of solving at least one of the above-mentioned technical problems existing in the related art.
Fig. 2 is a schematic circuit diagram of a buck circuit according to an embodiment of the present application, and as shown in fig. 2, the buck circuit 200 may include a power conversion sub-circuit 210, an additional current feedback module 220, and an offset cancellation sub-circuit 230. Wherein, the power conversion sub-circuit 210 may be used for down-converting the input dc level and outputting, the power conversion sub-circuit 210 may include a BUCK circuit, and the BUCK circuit may include an inductor; the first and second ends of the additional current feedback module 220 are electrically connected to the power conversion sub-circuit 210 and can be used to measure inductor information of the power conversion sub-circuit 210. The additional current feedback module 220 may include a capacitor and its equivalent series resistance.
The first input terminal and the second input terminal of the offset cancellation sub-circuit 230 are electrically connected to the additional current feedback module 220, the output terminal of the offset cancellation sub-circuit 230 is electrically connected to the power conversion sub-circuit 210, the first input terminal and the second input terminal of the offset cancellation sub-circuit 230 have voltage information with the same dc, and the voltage information with the same dc is the dc offset voltage of the power conversion sub-circuit 210. The dc offset voltage is caused by the additional current feedback module 220, and the offset cancellation sub-circuit 230 is used to cancel the dc offset voltage of the power conversion sub-circuit 210.
In this way, on the one hand, since the dc offset of the output voltage of the power conversion sub-circuit 210 is introduced into the first input terminal and the second input terminal of the offset cancellation sub-circuit 230, the dc offsets of the two input terminals cancel each other, thereby improving the output accuracy of the step-down circuit 200. On the other hand, the step-down circuit eliminates offset voltage and does not use a low-pass filter to filter the offset of direct current, so that the chip area is reduced and the complexity of circuit design is reduced.
Fig. 3 is another schematic circuit diagram of a buck circuit according to an embodiment of the present application, and as shown in fig. 3, the offset cancellation sub-circuit 230 may include: an offset voltage sampling module 231, an adder A1 and a comparison module EA.
The input end of the offset voltage sampling module 231 is electrically connected with the power conversion sub-circuit 210 through the additional current feedback module 220, the offset voltage sampling module 231 may be used to collect the voltage V OS of the additional current feedback module 220, the voltage V OS of the additional current feedback module 220 includes a dc offset voltage, and the offset voltage sampling module 231 may include offset voltage sampling (Offset voltage sampling).
A first input of the adder A1 is electrically connected to the offset voltage sampling module 231, a second input of the adder A1 is configured to receive the reference voltage V REF, and the adder A1 is configured to sum the reference voltage V REF with the voltage V OS of the additional current feedback module 220 to obtain a first voltage V B.
The first input end of the comparison module EA is electrically connected to the output end of the adder A1, the second input end of the comparison module EA is electrically connected to the additional current feedback module 220, and the second input end of the comparison module EA is configured to receive the second voltage V S, and since the second voltage V S is the sum of the acquired voltage of the additional current feedback module 220 and the output voltage of the power conversion sub-circuit 210, the second voltage V S also includes the dc offset voltage of the additional current feedback. The comparison module EA outputs a high level in response to the first voltage V B being greater than the second voltage V S.
In this way, the dc offset voltage in the second voltage V S and the dc offset voltage in the first voltage V B can cancel each other when the comparison module EA performs the comparison, so as to eliminate the influence of the dc offset voltage on the power conversion sub-circuit 210, and improve the output accuracy of the buck circuit 200.
Fig. 4 is a schematic circuit diagram of a buck circuit according to an embodiment of the present application, and as shown in fig. 4, a power conversion sub-circuit 210 may include: the first P-type transistor HS, the logic driving module L & D, the first N-type transistor LS and the constant on-time module COT.
The first end of the first P-type transistor HS is electrically connected to the power supply terminal V IN, and the first P-type transistor HS is turned on in response to the control terminal of the first P-type transistor HS receiving a low level. The first terminal of the logic driving module L & D is electrically connected to the control terminal of the first P-type transistor HS. The control end of the first N-type transistor LS is electrically connected with the second end of the logic driving module L & D, the first end of the first N-type transistor LS is electrically connected with the second end of the first P-type transistor HS, and the second end of the first N-type transistor LS is electrically connected with the grounding end. The logic driving module L & D may be configured to control on and off of the first P-type transistor HS and the first N-type transistor LS, which are alternately turned on.
The first end of the constant conduction time module COT is electrically connected with the third end of the logic driving module L & D, the second end of the constant conduction time module COT is electrically connected with the output end of the comparison module, the constant conduction time module COT responds to the output high level of the comparison module and can generate constant conduction time, the constant conduction time module COT is used for controlling the logic driving module L & D to output high and low levels, and when the constant conduction time module COT is in the constant conduction time TON, the logic driving module L & D is controlled to output low levels; and when the constant on-time of the constant on-time module COT is finished, the COT stops working, and the logic driving module L & D is controlled to output a high level. The control of the constant on-time module COT will be explained in detail below, and will not be described in detail herein.
With continued reference to fig. 4, in accordance with some embodiments of the application, the power conversion subcircuit 210 may optionally further include: inductor L, inductor equivalent series resistance R DCR, first capacitance C, first capacitance equivalent series resistance R ESR, and load I LOAD.
The first end of the inductor L is electrically connected with the second end of the first P-type transistor HS and the first end of the additional current feedback module; a first end of the inductor equivalent series resistor R DCR is electrically connected to a second end of the inductor L, and a second end of the inductor equivalent series resistor R DCR is electrically connected to a second end of the additional current feedback module 220; the first end of the first capacitor C is electrically connected with the power supply end V IN; a first end of the first capacitance equivalent series resistor R ESR is electrically connected with a second end of the inductor equivalent series resistor R DCR, and a second end of the first capacitance equivalent series resistor R ESR is electrically connected with a second end of the first capacitance C; the first end of the load I LOAD is electrically connected to the second end of the inductor equivalent series resistor R DCR, and the second end of the load I LOAD is electrically connected to ground.
The step-down circuit 200 operates as follows: when the logic driving module L & D outputs a low level, the first P-type transistor HS is turned on, the first N-type transistor LS is kept turned off, the current I L of the inductor L increases, and the output voltage V OUT increases. When the logic driving module L & D outputs a high level, the first N-type transistor LS is turned on, the first P-type transistor HS is turned off, and at this time, the inductor current I L starts to decrease, and the output voltage V OUT decreases.
Fig. 5 is a schematic circuit diagram of a buck circuit according to an embodiment of the present application, and as shown in fig. 5, the additional current feedback module 220 may include: the second capacitor C SEN and the second capacitor equivalent series resistance R SEN.
The negative plate of the second capacitor C SEN is electrically connected with the second end of the equivalent series resistance of the inductor, and the positive plate of the second capacitor C SEN is electrically connected with the second input end of the comparison module; the first end of the second capacitance equivalent series resistor R SEN is electrically connected to the first end of the inductor, and the second end of the second capacitance equivalent series resistor R SEN is electrically connected to the positive plate of the second capacitance C SEN.
The step-down circuit 200 operates as follows: the power supply terminal V IN is powered on, the first P-type transistor HS is turned on, the first N-type transistor LS is kept turned off, the inductor current I L is increased, the output voltage V OUT is increased, the additional current feedback module 220 starts to sample the inductor current I L, and the second voltage V S is generated after passing through the second capacitor C SEN and is transmitted to the negative input terminal of the comparison module EA. Meanwhile, the offset voltage sampling module 231 samples the current of the first P-type transistor HS, generates a voltage V OS after passing through the resistor R1, and superimposes V OS and a reference voltage V REF by using an adder, at this time, V S<VB, the comparator outputs a level V COMP =1, the constant on-time module COT starts to work to generate a constant on-time TON to the first P-type transistor HS until the on-time is over, the constant on-time module COT stops working, the first P-type transistor HS is turned off, and the first N-type transistor LS is turned on. At this time, the inductor current I L starts to fall, the output voltage V OUT starts to fall, when it falls to V S<VB, V COMP =1, and the next cycle is restarted.
After passing through the second capacitor C SEN, a second voltage V S is generated and transmitted to the negative input terminal of the comparison module EA, where:
In the formula (1), Representing the dc voltage component of the additional current feedback module 220,Representing the ac voltage component of the additional current feedback module 220,/>Representing the DC voltage component of power conversion subcircuit 210,/>Representing the ac voltage component of the power conversion subcircuit 210.
In the case of the reference voltage V REF,
The formula (2) represents that the reference voltage is selected as the valley voltage of the step-down circuit, the right side of the formula (2) represents the valley voltage formula of the step-down circuit, and the valley voltage formula is the existing formula of the step-down circuit, so that detailed explanation is not provided herein.
The voltage V OS of the additional current feedback module is overlapped with the reference voltage V REF by using an adder, and a first voltage V B can be obtained:
(3)
the solution according to formulas (1) to (3) is:
Due to And/>Are all AC components, and do not affect the DC offset of the output voltage,/>For a set valley voltage, the dc offset of the output voltage is not affected either, so it can be concluded from equation (4): the output accuracy of the output voltage V OUT of the power conversion sub-circuit is defined by/>And/>And (5) determining. Thus can be constructed/>And/>To cancel the flow/>, in V SEN The influence of (i) i.e./>The DC component of (a) is to be combined with/>The dc voltage offset of the buck circuit is reduced by the same magnitude.
Since the additional current feedback module 220 is connected in parallel with the inductor L, the dc voltage of the additional current feedback module can be obtained according to the average current on the inductor L and the inductor equivalent series resistance R DCR:
Wherein the method comprises the steps of Is the average current of the inductor,/>Is the resistance of the equivalent series resistance of the inductor.
Since V SEN is generated by the additional current feedback module 220, it is available from the transfer function:
Where sL is the impedance of the inductor L, Representing the inductor L and the resistance/>Total resistance value of/>Representing the total resistance of the additional current feedback module 220. If the voltage V SEN of the additional current feedback module 220 is in phase with the inductor Lcurrent, it is necessary to make/>And (3) solving to obtain:
transfer function at this time 。
When the constraint of equation (7) is satisfied, the dc magnitude V SEN_DC at the voltage V SEN of the additional current feedback module 220 will have a linear relationship with the output current I OUT of the first P-type transistor HS, so that a value equal to V SEN_DC can be obtained by sampling the output current I OUT of the first P-type transistor HS. Therefore, the generation of the design V OS of the present application is derived by sampling the output current of the first P-type transistor HS.
Fig. 6 is a schematic circuit diagram of a buck circuit according to an embodiment of the present application, and as shown in fig. 6, the offset voltage sampling module 231 may include: the second P-type transistor Q1, the operational amplifier OP, the second N-type transistor Q2 and the resistor R1.
The first end of the second P-type transistor Q1 is electrically connected with the power supply end and the second end of the first P-type transistor, and the control end of the second P-type transistor Q1 is electrically connected with the grounding end; the positive input end of the operational amplifier OP is electrically connected with the first end of the first P-type transistor, the negative input end of the operational amplifier OP is electrically connected with the second end of the second P-type transistor Q1, and the operational amplifier OP is used for making the input voltage of the positive input end and the input voltage of the negative input end equal.
The control end of the second N-type transistor Q2 is electrically connected with the output end of the operational amplifier OP, the first end of the second N-type transistor Q2 is electrically connected with the second end of the second P-type transistor Q1, the second end of the second N-type transistor Q2 is electrically connected with the second input end of the adder, and the second end of the second N-type transistor Q2 is used for outputting the voltage V OS of the additional current feedback module; the first end of the resistor R1 is electrically connected with the second end of the second N-type transistor Q2, and the second end of the resistor R1 is electrically connected with the grounding end and the second end of the first N-type transistor. The ratio of the resistance of the resistor R1 to the resistance of the inductor equivalent series resistor R DCR is equal to a preset multiple K.
As can be seen from fig. 6, the driving signal connected to the gate terminal of the first N-type transistor LS is n_drv. The offset voltage sampling module 231 samples the output current of the first P-type transistor HS. Since the first P-type transistor HS is turned on when the low level is reached, when the offset voltage sampling module 231 starts sampling, the driving signal p_drv connected to the gate terminal of the first P-type transistor HS is turned on when the driving signal p_drv is reached to the low level, so that the gate terminal of the first P-type transistor HS is considered to be grounded. The gate of the second P-type transistor Q1 is grounded. Since the source terminals of the first P-type transistor HS and the second P-type transistor are both connected to the power supply terminal VDD, and the drain terminal is clamped by the operational amplifier OP, that is, the drain terminal voltages of HS and Q1 are also equal, the gate terminal voltages are also equal, at this time HS and Q1 are simultaneously in the saturation region, and the output current I OUT is mirrored through Q1 to be I sen. The current through Q1 and HS is related to the aspect ratio of the channel region.
In the embodiment of the application, the width-to-length ratio of the channel regions of the first P-type transistor HS and the second P-type transistor Q1 is set to be a preset multiple K, and the ratio of the resistance value of the resistor R1 to the resistance value of the equivalent series resistor R DCR of the inductor is also equal to the preset multiple K. The method can obtain the following steps:
Wherein I sen is the detected current, the detected current flows through the resistor R1, and the ratio of the resistance value of the resistor R1 to the resistance value of the inductor equivalent series resistor R DCR is equal to the preset multiple K, so that the detected current is converted into the voltage V OS of the additional current feedback module 220:
At this time, under the constraint condition that the formula (7) is satisfied, the voltage V OS of the additional current feedback module 220 is obtained as follows:
Thus, combining equation (4) with equation (10) can yield a dc expression of the final output voltage:
from equation (11), the DC component of the final output voltage can be seen Absence/>Influence of/(I)Is counteracted, the ac voltage of the additional current feedback module 220/>And alternating voltage of output voltage/>Reference voltage/>The output precision of the step-down circuit is not affected, so that the precision of the output voltage can be improved through the embodiment of the application.
Fig. 7 is a schematic circuit diagram of a step-down circuit according to an embodiment of the present application, and as shown in fig. 7, the comparison module EA may include: the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the first current mirror module 701, and the second current mirror module 702.
The control ends of the first transistor M1 and the second transistor are used for receiving the bias voltage V BIAS, and the first end of the first transistor M1 is electrically connected with the power supply end VDD; the first end of the second transistor M2 is electrically connected with the power supply end VDD and the first end of the first transistor M1; the control end of the third transistor M3 is configured to receive the voltage V OS of the additional current feedback module, and the first end of the third transistor M3 is electrically connected to the second end of the first transistor M1; the control terminal of the fourth transistor M4 is configured to receive the output voltage V OUT of the power conversion sub-circuit, and the first terminal of the fourth transistor M4 is electrically connected to the second terminal of the first transistor M1; the control terminal of the fifth transistor M5 is configured to receive the reference voltage V REF, and the first terminal of the fifth transistor M5 is electrically connected to the second terminal of the second transistor M2; the control terminal of the sixth transistor M6 is electrically connected to the additional current feedback module, the first terminal of the sixth transistor M6 is electrically connected to the second terminal of the second transistor M2, and the second terminal of the sixth transistor M6 is electrically connected to the second terminal of the fourth transistor M4.
A first end of the first current mirror module 701 is electrically connected to the second end of the third transistor M3, a second end of the first current mirror module 701 is electrically connected to the second end of the fourth transistor M4, and a third end of the first current mirror module 701 is electrically connected to the ground terminal; the first end of the second current mirror module 702 is electrically connected to the second end of the fifth transistor M5 and the second end of the third transistor M3, the second end of the second current mirror module 702 is electrically connected to the second end of the sixth transistor M6, and the third end of the second current mirror module 702 is electrically connected to the ground. And an inverter F1, wherein a first terminal of the inverter F1 is electrically connected to a second terminal of the second current mirror module 702 and a second terminal of the sixth transistor M6, and the inverter F1 outputs a high level in response to receiving a low level and outputs a low level in response to receiving a high level.
With continued reference to fig. 7, the first current mirror module 701 may include: a seventh transistor M7 and an eighth transistor M8.
The first end of the seventh transistor M7 is electrically connected with the control end of the seventh transistor M7 and the second end of the third transistor, and the second end of the seventh transistor M7 is electrically connected with the grounding end; the first end of the eighth transistor M8 is electrically connected to the second end of the fourth transistor, the control end of the eighth transistor M8 is electrically connected to the control end of the seventh transistor M7, and the second end of the eighth transistor M8 is electrically connected to the ground.
The second current mirror module 702 may include: a ninth transistor M9 and a tenth transistor M10.
A first end of the ninth transistor M9 is electrically connected to the control end of the ninth transistor M9 and a second end of the fifth transistor, and a second end of the ninth transistor M9 is electrically connected to the ground; the control terminal of the tenth transistor M10 is electrically connected to the control terminal of the ninth transistor M9, the first terminal of the tenth transistor M10 is electrically connected to the first terminal of the inverter F1, and the second terminal of the tenth transistor M10 is electrically connected to the ground terminal.
By deriving from the above formulas, V S and V B, the voltages of V SEN、VOUT and V REF need to be superimposed, and the conventional voltage superimposing method is to superimpose currents on resistors to obtain different voltages, but the power consumption of the method is larger and the occupied chip area is large, so that the application selects to copy the voltages through the current mirror of the circuit, and then directly compares the magnitudes of the two currents to obtain the control signal of the constant on-time module COT, and the circuit principle of the comparison module EA is as follows:
The first transistor M1 and the second transistor M2 may be PMOS transistors, and the gate terminals of the M1 and the M2 are connected to a fixed bias voltage V BIAS, which is used to provide current for the overall circuit, and the corresponding current can be obtained by controlling the sizes of the M1 and the M2. The third transistor M3, the fourth transistor M4, the fifth transistor M5 and the sixth transistor M6 form a differential pair for converting the voltage V OUT、VOS、VREF、VSEN into corresponding currents and comparing the magnitudes, wherein the signal of V S in the formula (1) is converted into the output current I S of the additional current feedback module, the signal of the first voltage V B is converted into the current signal I B by the formula (3), and the result can be obtained by combining with FIG. 7
Wherein I M4 represents the current flowing through the fourth transistor M4, I M8 represents the current flowing through the eighth transistor M8, and I M6 represents the current flowing through the sixth transistor M6; i M3 denotes a current flowing through the third transistor M3, I M7 denotes a current flowing through the seventh transistor M7, and I M5 denotes a current flowing through the fifth transistor M5.
Due to the existence of the inverter F1, the following can be achieved
Wherein V COMP represents a judgment signal, so that the output V COMP judgment signal is transmitted to the constant on-time module COT to control on and off of the first P-type transistor HS. When implemented inWhen a high level signal is output, the constant on-time module starts to work to generate constant on-time TON, and the control logic driving module sends a low level signal to the first P-type transistor HS to enable the first P-type transistor HS to be turned on. After the on-time TON is turned off, the constant on-time module COT stops working, the first P-type transistor HS is turned off, and the first N-type transistor LS is turned on. At this point, the inductor L current begins to drop, when/>When V COMP =1, the step-down voltage-stabilizing output of the step-down circuit in the next cycle is restarted.
On the one hand, on the basis of using a smaller ESR resistor, V OS with sampling direct-current voltage information is added to offset output voltage offset, so that the stability of a step-down circuit is improved, the output offset voltage is reduced, and the output voltage precision is improved; on the other hand, the disadvantage that a low-pass filter is formed by a large capacitor to filter to eliminate direct current in the related art is reduced, and the chip area is saved.
It should be understood that the specific structures of the circuits provided in the drawings of the embodiments of the present application are only examples and are not intended to limit the present application. In addition, the above embodiments provided by the present application may be combined with each other without contradiction.
It should be understood that, in the present specification, each embodiment is described in an incremental manner, and the same or similar parts between the embodiments are all referred to each other, and each embodiment is mainly described in a different point from other embodiments. These embodiments are not exhaustive of all details, nor are they intended to limit the application to the precise embodiments disclosed, in accordance with the application. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best utilize the application and various modifications as are suited to the particular use contemplated. The application is limited only by the claims and the full scope and equivalents thereof.
Those skilled in the art will appreciate that the above-described embodiments are exemplary and not limiting. The different technical features presented in the different embodiments may be combined to advantage. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in view of the drawings, the description, and the claims. In the claims, the term "comprising" does not exclude other structures; the amounts refer to "a" and do not exclude a plurality; the terms "first," "second," and the like, are used for designating a name and not for indicating any particular order. Any reference signs in the claims shall not be construed as limiting the scope. The presence of certain features in different dependent claims does not imply that these features cannot be combined to advantage.
Claims (8)
1. A buck circuit, comprising:
The power conversion sub-circuit is used for performing buck conversion on the input direct current level and outputting the buck converted direct current level;
The first end and the second end of the additional current feedback module are electrically connected with the power conversion sub-circuit, and the additional current feedback module is used for measuring inductor information of the power conversion sub-circuit;
The first input end and the second input end of the offset elimination sub-circuit are electrically connected with the additional current feedback module, the output end of the offset elimination sub-circuit is electrically connected with the power conversion sub-circuit, the first input end and the second input end of the offset elimination sub-circuit have voltage information with the same direct current, and the voltage information with the same direct current is the direct current offset voltage of the power conversion sub-circuit;
The offset cancellation subcircuit includes:
the input end of the offset voltage sampling module is electrically connected with the additional current feedback module, the offset voltage sampling module is used for collecting the voltage of the additional current feedback module, and the voltage of the additional current feedback module comprises the direct current offset voltage;
The first input end of the adder is electrically connected with the offset voltage sampling module, the second input end of the adder is used for receiving a reference voltage, and the adder is used for summing the reference voltage and the voltage of the additional current feedback module to obtain a first voltage;
The first input end of the comparison module is electrically connected with the output end of the adder, the second input end of the comparison module is electrically connected with the additional current feedback module, the second input end of the comparison module is used for receiving a second voltage, and the comparison module responds to the first voltage being larger than the second voltage and outputs a high level;
the power conversion subcircuit includes:
A first P-type transistor, a first end of the first P-type transistor is electrically connected with a power supply end, and the first P-type transistor is turned on when a control end of the first P-type transistor receives a low level;
the first end of the logic driving module is electrically connected with the control end of the first P-type transistor;
The control end of the first N-type transistor is electrically connected with the second end of the logic driving module, the first end of the first N-type transistor is electrically connected with the second end of the first P-type transistor, and the second end of the first N-type transistor is electrically connected with the grounding end;
the offset voltage sampling module includes:
The first end of the second P-type transistor is electrically connected with the power supply end and the second end of the first P-type transistor, and the control end of the second P-type transistor is electrically connected with the grounding end;
The positive input end of the operational amplifier is electrically connected with the first end of the first P-type transistor, the negative input end of the operational amplifier is electrically connected with the second end of the second P-type transistor, and the operational amplifier is used for enabling the input voltage of the positive input end and the input voltage of the negative input end to be equal;
The control end of the second N-type transistor is electrically connected with the output end of the operational amplifier, the first end of the second N-type transistor is electrically connected with the second end of the second P-type transistor, the second end of the second N-type transistor is electrically connected with the second input end of the adder, and the second end of the second N-type transistor is used for outputting the voltage of the additional current feedback module;
and the first end of the resistor is electrically connected with the second end of the second N-type transistor, and the second end of the resistor is electrically connected with the grounding end and the second end of the first N-type transistor.
2. The buck circuit according to claim 1, wherein the power conversion sub-circuit further comprises:
And the constant conduction time module is used for responding to the output high level of the comparison module to generate constant conduction time.
3. The buck circuit according to claim 2, wherein the power conversion sub-circuit further includes:
an inductor, a first end of which is electrically connected with a second end of the first P-type transistor and a first end of the additional current feedback module;
An inductor equivalent series resistance, a first end of the inductor equivalent series resistance being electrically connected with a second end of the inductor, a second end of the inductor equivalent series resistance being electrically connected with a second end of the additional current feedback module;
the first end of the first capacitor is electrically connected with the power supply end;
A first capacitor equivalent series resistor, wherein a first end of the first capacitor equivalent series resistor is electrically connected with a second end of the inductor equivalent series resistor, and a second end of the first capacitor equivalent series resistor is electrically connected with a second end of the first capacitor;
And the first end of the load is electrically connected with the second end of the equivalent series resistance of the inductor, and the second end of the load is electrically connected with the grounding end.
4. The buck circuit according to claim 1, wherein a ratio of a width to length ratio of a channel region of the first P-type transistor to a width to length ratio of a channel region of the second P-type transistor is equal to a predetermined multiple, and a ratio of a resistance of the resistor to a resistance of the inductor equivalent series resistor is equal to the predetermined multiple.
5. A buck circuit according to claim 3, wherein the additional current feedback module includes:
The negative plate of the second capacitor is electrically connected with the second end of the equivalent series resistance of the inductor, and the positive plate of the second capacitor is electrically connected with the second input end of the comparison module;
And the first end of the second capacitor equivalent series resistor is electrically connected with the first end of the inductor, and the second end of the second capacitor equivalent series resistor is electrically connected with the positive plate of the second capacitor.
6. The buck circuit according to claim 1, wherein the comparison module includes:
the control end of the first transistor is used for receiving bias voltage, and the first end of the first transistor is electrically connected with the power supply end;
a second transistor, a control end of which is used for receiving the bias voltage, and a first end of which is electrically connected with the power supply end and a first end of the first transistor;
a third transistor, a control terminal of which is used for receiving the voltage of the additional current feedback module, and a first terminal of which is electrically connected with a second terminal of the first transistor;
a fourth transistor, a control terminal of which is used for receiving the output voltage of the power conversion subcircuit, and a first terminal of which is electrically connected with a second terminal of the first transistor;
A fifth transistor, a control terminal of which is used for receiving the reference voltage, a first terminal of which is electrically connected with a second terminal of the second transistor, and a second terminal of which is electrically connected with a second terminal of the third transistor;
A sixth transistor, a control terminal of the sixth transistor being electrically connected to the additional current feedback module, a first terminal of the sixth transistor being electrically connected to the second terminal of the second transistor, a second terminal of the sixth transistor being electrically connected to the second terminal of the fourth transistor;
The first end of the first current mirror module is electrically connected with the second end of the third transistor, the second end of the first current mirror module is electrically connected with the second end of the fourth transistor, and the third end of the first current mirror module is electrically connected with the grounding end;
the first end of the second current mirror module is electrically connected with the second end of the fifth transistor and the second end of the third transistor, the second end of the second current mirror module is electrically connected with the second end of the sixth transistor, and the third end of the second current mirror module is electrically connected with the grounding end;
And the first end of the inverter is electrically connected with the second end of the second current mirror module and the second end of the sixth transistor, and the inverter outputs a high level in response to receiving a low level and outputs a low level in response to receiving a high level.
7. The buck circuit according to claim 6, wherein the first current mirror module includes:
A seventh transistor, a first end of which is electrically connected with the control end of the seventh transistor and a second end of the third transistor, and a second end of which is electrically connected with a ground end;
And the first end of the eighth transistor is electrically connected with the second end of the fourth transistor, the control end of the eighth transistor is electrically connected with the control end of the seventh transistor, and the second end of the eighth transistor is electrically connected with the grounding end.
8. The buck circuit according to claim 6, wherein the second current mirror module includes:
a ninth transistor, a first end of the ninth transistor is electrically connected with a control end of the ninth transistor and a second end of the fifth transistor, and a second end of the ninth transistor is electrically connected with a ground end;
and a tenth transistor, wherein the control terminal of the tenth transistor is electrically connected with the control terminal of the ninth transistor, the first terminal of the tenth transistor is electrically connected with the first terminal of the inverter, and the second terminal of the tenth transistor is electrically connected with the ground terminal.
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