CN106100305A - DC maladjustment removing method in COT ripple compensation circuit - Google Patents

Abstract

DC maladjustment removing method in COT ripple compensation circuit, belongs to technical field of power management.Produce process including sampling pulse S/H and misalignment rate eliminates process, during sampling pulse S/H generation, output signal LoopCom_OUT of acquisition system loop comparator is input to the set end S of set-reset flip-floop, output signal TonComp_OUT of acquisition system constant on-time module be input to the clear terminal R of set-reset flip-floop, set-reset flip-floop reversed-phase output NQ output signal lag process after with in-phase output end Q output signal be jointly input to door carry out with operation after obtain sampling keep pulse S/H；Misalignment rate utilizes sampling to keep pulse S/H control the extraction of DC information and utilize the DC information extracted to eliminate the misalignment rate of output voltage in ripple laminating module during eliminating.The present invention realizes the output imbalance of changer and eliminates by adding DC maladjustment removing method in extracting circuit in DC quantity, it is not necessary to add extra offset cancellation circuit.

Description

DC maladjustment removing method in COT ripple compensation circuit

Technical field

The invention belongs to technical field of power management, be specifically related to a kind of for eliminating constant on-time (Constant On Time, COT) control framework buck convertor output DC maladjustment removing method.

Background technology

Compared to voltage mode control and Peak Current-Mode Controlled Circuit, COT control model need not traditional mistake Difference amplifier, this makes COT control model can provide faster transient response on the basis of keeping precision；COT controls mould Frequency stabilization in the full input voltage range that formula is provided, all makes great sense for electromagnetism interference characteristic etc.；COT simultaneously The lifting of control model efficiency under underloading meets the development trend of present stage electronic product.COT controls framework at power supply pipe Favor is enjoyed in the middle of reason chip.

COT, while bringing advantage for power management products, self there is also some defects, and COT controls changer and adopts Starting each new cycle with valley triggering mode, this will introduce extra DC maladjustment amount on the output voltage.As shown in Figure 1 Control to produce the key waveforms of imbalance in output voltage for tradition COT, can obtain under valley triggering pattern, each new week Phase, when feedback voltage V FB is less than reference voltage VREF, based on this pattern, can obtain meansigma methods and the base of feedback voltage Offset voltage V is there is between quasi-voltage VREF_OS, offset voltage amount V can be drawn according to the basic theories of buck convertor_OS As follows:

$V_{OS}=\frac{1}{2}\frac{V_{in}-V_o}{L}{T}_{on}{R}_{SEN}$

Offset voltage V_OSWith ON time Ton, input voltage V_in, output voltage V_OAnd inductive current sampling resistor R_SEN Relevant, to offset voltage V under low duty ratio is applied_OSImpact particularly evident.The COT technology being typically based on ripple control is being made an uproar There is the compromise selection of design between sound nargin and the upper DC maladjustment amount introduced of output, high anti-noise ability requires to compensate stricture of vagina Ripple has enough amplitudes, and this will bring bigger output DC maladjustment, and in high-precision application, the defect of DC maladjustment shows Obtain the most prominent.

Summary of the invention

Present invention aim to address that existing COT controls the problems referred to above that framework exists, it is proposed that COT ripple compensation electricity DC maladjustment removing method in road, it is the ripple compensation base in half period sampling that the DC maladjustment that the present invention proposes eliminates circuit Formed on plinth, it is not necessary to add extra offset cancellation circuit.

The technical scheme is that the DC maladjustment removing method in COT ripple compensation circuit, including:

Sampling pulse S/H produces process and misalignment rate eliminates process；

It is characterized in that, described sampling pulse S/H produces process and comprises the following steps:

Step one: gather output signal LoopCom_OUT and the system of system loop comparator in COT ripple compensation circuit Output signal TonComp_OUT of constant on-time module；

Step 2: the set end that output signal LoopCom_OUT of system loop comparator is input in set-reset flip-floop S, carries out letter by the clear terminal R that output signal TonComp_OUT of systems constant ON time module is input in set-reset flip-floop Number process；

Step 3: the signal of set-reset flip-floop in-phase output end Q output is not processed, to set-reset flip-floop reversed-phase output NQ The signal of output makees delay process；

Step 4: the signal and the step 3 that are exported by set-reset flip-floop in-phase output end Q are defeated to set-reset flip-floop reversed-phase output NQ Signal after the signal lag gone out processes is input to carry out obtaining sampling holding pulse S/H with operation with door；

Described misalignment rate eliminates process and comprises the following steps:

Step 5: extract DC information in ripple DC quantity extracts circuit；

Described ripple DC quantity extract circuit include the first transmission gate TG1, the second transmission gate TG2, the second phase inverter INV2, First resistance R₁, the second resistance R₂, the first electric capacity C₁With the second electric capacity C₂；The outfan of the first transmission gate TG1 passes through the first resistance R₁With the first electric capacity C₁Cascaded structure after ground connection, the outfan of the second transmission gate TG2 pass through the second resistance R₂With the second electric capacity C₂ Cascaded structure after ground connection；

Sampling keeps pulse S/H as the first transmission gate TG1 and the second transmission gate TG2 of ripple DC quantity extraction circuit Control signal, controls high live end and the low live end of the second transmission gate TG2 of the first transmission gate TG1, simultaneously anti-through second Phase device INV2 controls low live end and the high live end of the second transmission gate TG2 of the first transmission gate TG1；

First differential amplification outfan V of the input termination inductive current pre-amplification circuit of the first transmission gate TG1₁, second Second differential amplification outfan V of the input termination inductive current pre-amplification circuit of transmission gate TG2₂；First transmission gate TG1's is defeated Go out to hold V₃Outfan V with the second transmission gate TG2₄The output signal kept as sampling；By calculating V₃-V₄=K V_DC= K·I_S/HR_{ds_on}The ripple DC component obtaining extracting is:

$I_{S/H}{R}_{dson}=(I_o-\frac{{\mathrm{\ΔI}}_L}{2})R_{dson}$

Step 6: by calculating V₁-V₂=-K V_ISENSE=K I_LR_{ds_on}The ripple information obtaining pre-amplification is: I_LR_{ds_on}；

The ripple information of pre-amplification is superimposed upon feedback voltage V after deducting ripple DC component_FBOn, each semaphore meet with Lower relation:

$V_{FB}+(I_L-I_o)R_{dson}=V_{REF}-\frac{{\mathrm{\ΔI}}_L}{2}{R}_{dson}$

It is equivalent in reference voltage V_REFOn introduce value and beDC maladjustment amount, this imbalance value and COT control The DC maladjustment measurer of framework self has identical size and contrary symbol, last feedback voltage V_FBAccurately it is clamped at base Quasi-voltage V_REFOn, i.e. the DC maladjustment amount of output voltage is completely eliminated.

Gain effect of the present invention: the output DC maladjustment of the present invention eliminates circuit based on half period sampling ripple compensation electricity Road, the output imbalance eliminating circuit realiration changer by adding DC maladjustment in extracting circuit in DC quantity eliminates；Need not Add extra offset cancellation circuit.

Accompanying drawing explanation

Fig. 1 is tradition COT control model buck convertor output DC maladjustment waveform diagram.

Fig. 2 is the DC maladjustment removing method flow chart in the COT ripple compensation circuit that the present invention proposes.

Fig. 3 is the frame diagram of the DC maladjustment removing method in the COT ripple compensation circuit that the present invention proposes.

Fig. 4 is that the DC quantity in the DC maladjustment removing method in the COT ripple compensation circuit proposed in the present invention is extracted Circuit realiration figure.

Fig. 5 is that the sampling in the DC maladjustment removing method in the COT ripple compensation circuit that the present invention proposes keeps pulse Realize figure.

Fig. 6 is that the DC maladjustment in the DC maladjustment removing method in the COT ripple compensation circuit that the present invention proposes eliminates Key waveforms schematic diagram.

Fig. 7 is that the voltage-dropping type being integrated with the DC maladjustment removing method in the COT ripple compensation circuit that the present invention proposes becomes Parallel operation DC maladjustment eradicating efficacy figure.

Detailed description of the invention

The invention will be further elaborated with specific embodiment below in conjunction with the accompanying drawings.

As Fig. 2 is the DC maladjustment removing method flow chart in the COT ripple compensation circuit that proposes of the present invention, including sampling Pulse S/H produces process and misalignment rate eliminates process.

DC maladjustment removing method in the COT ripple compensation circuit that the present invention proposes realizes figure as shown in Fig. 3 block diagram, and half Inductive current ripple information after periodic sampling, after prime amplifier carries out K times of fully differential amplification, is delivered to DC quantity and is carried Carrying out DC quantity extraction in sense circuit, the core of the present invention is that DC quantity is extracted the generation of pulse and coordinates ripple superposition electricity Extracted amount is deducted by road.

Ripple DC quantity is extracted circuit i.e. sampling hold circuit and is included as shown in Figure 4, the first transmission gate TG1, the second transmission Door TG2, the first resistance R1, the second resistance R2, the first phase inverter INV2, the first electric capacity C1 and the second electric capacity C2；First transmission gate First differential amplification outfan V of the input termination inductive current pre-amplification circuit of TG1₁, the input termination of the second transmission gate TG2 Second differential amplification outfan V of inductive current pre-amplification circuit₂；The outfan of the first transmission gate TG1 passes through the first resistance R₁With First electric capacity C₁Cascaded structure after ground connection, the outfan of the second transmission gate TG2 pass through the second resistance R₂With the second electric capacity C₂String Ground connection after connection structure；Sampling keeps pulse S/H to extract the first transmission gate TG1 and second transmission gate of circuit as ripple DC quantity The control signal of TG2, controls high live end and the low live end of the second transmission gate TG2 of the first transmission gate TG1, simultaneously through stricture of vagina Ripple DC quantity is extracted the first phase inverter INV1 in circuit and is controlled low live end and the second transmission gate TG2 of the first transmission gate TG1 High live end；Ripple DC quantity extracts the outfan V of the first transmission gate TG1 of the i.e. sampling hold circuit of circuit₃Pass with second The outfan V of defeated door TG2₄The output signal kept as sampling.

Sampling keeps the burst length the shortest, can be approximately considered the DC quantity that value is input signal after sampling keeps, Sampling keeps signal to update once when each end cycle, and the sampling for a upper cycle making computing with this ripple information is protected The amount of holding, in the work of stable state, has identical value.

Sampling keeps the generation of pulse to be the key point of the present invention, a kind of implementation method of concrete circuit as it is shown in figure 5, Described sampling keep pulse-generating circuit include set-reset flip-floop SR1, delay unit Delay, the first phase inverter INV1 and with door AND1；The clear terminal R of the output LoopComp_OUT, set-reset flip-floop SR1 of the set end S T-Ring road comparator of set-reset flip-floop SR1 Meet the output TonComp_OUT of constant on-time module；The in-phase output end Q of set-reset flip-floop SR1 connects the road with door AND1 Input, the reversed-phase output NQ of set-reset flip-floop SR1 connects another road input with door AND1 after delay unit Delay End, i.e. sample holding pulse S/H with the computing output signal of door AND1, another side by after the first phase inverter INV1 as power The master switch signal Switch of pipe is input to drive module to realize upper power tube and the control of lower power tube.

Fig. 6 illustrates generation and the ultimate principle of DC maladjustment elimination of related keyword signal in the present invention, below Describing in detail according to Fig. 6, sampling keeps pulse before each new cycle starts, and passes through

V₁-V₂=-K V_ISENSE=K I_LR_{ds_on}

V₃-V₄=K V_DC=K I_S/HR_{ds_on}

The ripple DC component that can obtain extracting is:

$I_{S/H}{R}_{dson}=(I_o-\frac{{\mathrm{\ΔI}}_L}{2})R_{dson}$

The system ripple principle of stacking figure be given in conjunction with Fig. 3, the ripple information of pre-amplification will be at ripple overlapping portion It is superimposed upon feedback voltage V after deducting the DC quantity information after sampling keeps_FBOn, and to its realize compensate, then have each newly The trigger point in cycle, each semaphore meets following relation:

$V_{FB}+(I_L-I_o)R_{dson}=V_{REF}-\frac{{\mathrm{\ΔI}}_L}{2}{R}_{dson}$

Δ I in above formula_LFor the peak-to-peak value of inductive current, I_OFor the meansigma methods of inductive current, then it is equivalent at benchmark Voltage V_REFOn introduce value and beDC maladjustment amount, this imbalance value and COT control the DC maladjustment of framework self Measurer has identical size, and contrary symbol, and the most last feedback voltage will be accurately clamped at reference voltage V_REFOn, i.e. the DC maladjustment amount of output voltage is completely eliminated.

Fig. 7 is the correlation output waveform of the COT control changer of the half period sampling compensation way being integrated with the present invention, from Can be seen that in figure that the meansigma methods of feedback voltage is completely the same with reference voltage, DC maladjustment amount is completely eliminated.

Those of ordinary skill in the art it will be appreciated that embodiment described here be to aid in reader understanding this Bright principle, it should be understood that protection scope of the present invention is not limited to such special statement and embodiment.This area It is each that those of ordinary skill can make various other without departing from essence of the present invention according to these technology disclosed by the invention enlightenment Planting concrete deformation and combination, these deform and combine the most within the scope of the present invention.

Claims (1)

1. DC maladjustment removing method in 1.COT ripple compensation circuit, including:

   Sampling pulse S/H produces process and misalignment rate eliminates process；

   It is characterized in that, described sampling pulse S/H produces process and comprises the following steps:

   Step one: the output signal (LoopCom_OUT) and the system that gather system loop comparator in COT ripple compensation circuit are permanent Determine the output signal (TonComp_OUT) of ON time module；

   Step 2: the set end that the output signal (LoopCom_OUT) of system loop comparator is input in set-reset flip-floop (S) clear terminal (R), the output signal (TonComp_OUT) of systems constant ON time module being input in set-reset flip-floop Carry out signal processing；

   Step 3: the signal exporting set-reset flip-floop in-phase output end (Q) does not processes, to set-reset flip-floop reversed-phase output (NQ) The signal of output makees delay process；

   Step 4: the signal and the step 3 that are exported by set-reset flip-floop in-phase output end (Q) are defeated to set-reset flip-floop reversed-phase output (NQ) Signal after the signal lag gone out processes is input to carry out obtaining sampling holding pulse (S/H) with operation with door；

   Described misalignment rate eliminates process and comprises the following steps:

   Step 5: extract DC information in ripple DC quantity extracts circuit；

   Described ripple DC quantity is extracted circuit and is included the first transmission gate (TG1), the second transmission gate (TG2), the second phase inverter (INV2), the first resistance (R₁), the second resistance (R₂), the first electric capacity (C₁) and the second electric capacity (C₂)；First transmission gate (TG1) Outfan passes through the first resistance (R₁) and the first electric capacity (C₁) cascaded structure after ground connection, the outfan of the second transmission gate (TG2) lead to Cross the second resistance (R₂) and the second electric capacity (C₂) cascaded structure after ground connection；

   Sampling keeps pulse (S/H) to extract the first transmission gate (TG1) and second transmission gate (TG2) of circuit as ripple DC quantity Control signal, control high live end and the low live end of the second transmission gate (TG2) of the first transmission gate (TG1), pass through simultaneously Second phase inverter (INV2) controls low live end and the high live end of the second transmission gate (TG2) of the first transmission gate (TG1)；

   First differential amplification outfan (V of the input termination inductive current pre-amplification circuit of the first transmission gate (TG1)₁), second passes Second differential amplification outfan (V of the input termination inductive current pre-amplification circuit of defeated door (TG2)₂)；First transmission gate (TG1) Outfan (V₃) and the outfan (V of the second transmission gate (TG2)₄) as the output signal kept of sampling；By calculating V₃-V₄ =K V_DC=KI_S/HR_{ds_on}The ripple DC component obtaining extracting is:

   $I_{S/H}{R}_{dson}=(I_o-\frac{{\mathrm{\ΔI}}_L}{2})R_{dson}$

   Step 6: by calculating V₁-V₂=-K V_ISENSE=KI_LR_{ds_on}The ripple information obtaining pre-amplification is: I_LR_{ds_on}；

   The ripple information of pre-amplification is superimposed upon feedback voltage (V after deducting ripple DC component_FBOn), each semaphore meet below Relation:

   $V_{FB}+(I_L-I_o)R_{dson}=V_{REF}-\frac{{\mathrm{\ΔI}}_L}{2}{R}_{dson}$

   It is equivalent at reference voltage (V_REFIntroducing value on) isDC maladjustment amount, this imbalance value and COT control cage The DC maladjustment measurer of structure self has identical size and contrary symbol, last feedback voltage (V_FB) accurately it is clamped at base Quasi-voltage (V_REFOn), i.e. the DC maladjustment amount of output voltage is completely eliminated.