CN117650163B - Semiconductor device with a semiconductor device having a plurality of semiconductor chips - Google Patents
Semiconductor device with a semiconductor device having a plurality of semiconductor chips Download PDFInfo
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- CN117650163B CN117650163B CN202311440110.5A CN202311440110A CN117650163B CN 117650163 B CN117650163 B CN 117650163B CN 202311440110 A CN202311440110 A CN 202311440110A CN 117650163 B CN117650163 B CN 117650163B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 112
- 239000002184 metal Substances 0.000 claims description 98
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 47
- 230000007704 transition Effects 0.000 claims description 12
- 238000011084 recovery Methods 0.000 description 21
- 230000006835 compression Effects 0.000 description 15
- 238000007906 compression Methods 0.000 description 15
- 238000000034 method Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 12
- 238000000151 deposition Methods 0.000 description 9
- 238000001259 photo etching Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- WSNMPAVSZJSIMT-UHFFFAOYSA-N COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 Chemical compound COc1c(C)c2COC(=O)c2c(O)c1CC(O)C1(C)CCC(=O)O1 WSNMPAVSZJSIMT-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 229920002120 photoresistant polymer Polymers 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a semiconductor device, which comprises: a drift layer of the first conductivity type; a second conductivity type voltage-resistant ring provided at a portion of the drift layer corresponding to the terminal region of the semiconductor device, the upper surface of the voltage-resistant ring constituting a portion of the upper surface of the drift layer; the field stop layer is arranged on the lower surface of the drift layer; and the collector layer is arranged on the lower surface of the field stop layer, an emitter layer is arranged in the collector layer, and the emitter layer is positioned at a part of the collector layer corresponding to the terminal region. Therefore, by arranging the emitter layer at the position of the collector layer corresponding to the terminal region, the semiconductor device can be reversely conducted, the area utilization rate of the semiconductor device can be improved, the whole area of the semiconductor device can be prevented from being increased, and the power consumption of the semiconductor device can be reduced while the reverse conduction of the semiconductor device is realized, and the reliability of the semiconductor device is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device.
Background
Reverse conducting insulated gate bipolar transistor refers to an insulated gate bipolar transistor and a freewheeling diode (or an insulated gate bipolar transistor and a fast recovery diode) integrated on a single chip. When preparing reverse-conduction insulated gate bipolar transistor in industry, insulated gate bipolar transistor and fast recovery diode are integrated in cell area of device, and two devices share terminal, so as to realize purpose of integrating fast recovery diode on insulated gate bipolar transistor.
In the prior art, as the insulated gate bipolar transistor and the fast recovery diode share the cell area of the device, the method has the defect that a part of the cell area of the insulated gate bipolar transistor is sacrificed, and in order to achieve the theoretical performance of the insulated gate bipolar transistor device during the design of the device, the area of the cell area of the device must be increased, so that the heat generated by the insulated gate bipolar transistor during the operation is further increased, and the reliability of the device is reduced.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, an object of the present invention is to provide a semiconductor device which can improve the reliability of the semiconductor device.
The semiconductor device according to an embodiment of the present invention includes: a drift layer of the first conductivity type; a second conductivity type voltage-resistant ring provided at a portion of the drift layer corresponding to a terminal region of the semiconductor device, an upper surface of the voltage-resistant ring constituting a portion of an upper surface of the drift layer; a field stop layer provided on a lower surface of the drift layer; and the collector layer is arranged on the lower surface of the field stop layer, an emitter layer is arranged in the collector layer, and the emitter layer is positioned at the part of the collector layer corresponding to the terminal region.
Therefore, by arranging the emitter layer at the position of the collector layer corresponding to the terminal region, the semiconductor device can be reversely conducted, the area utilization rate of the semiconductor device can be improved, the whole area of the semiconductor device can be prevented from being increased, and the power consumption of the semiconductor device can be reduced while the reverse conduction of the semiconductor device is realized, and the reliability of the semiconductor device is improved.
In some examples of the present invention, an emitter metal is provided on an upper surface of the drift layer corresponding to an active region portion of the semiconductor device, and a metal connection channel is connected between the voltage resistance ring and the emitter metal.
In some examples of the present invention, a polysilicon field plate is disposed above the surface of the pressure-resistant ring, a dielectric layer is disposed above the surface of the polysilicon field plate, the dielectric layer is provided with a through hole, one end of the metal connection channel penetrates through the through hole and is electrically connected with the polysilicon field plate contact, and the other end of the metal connection channel is electrically connected with the emitter metal contact.
In some examples of the present invention, the plurality of the pressure-resistant rings are arranged at intervals, the plurality of the polysilicon field plates are arranged in a one-to-one correspondence manner, and one end of the metal connecting channel is in contact electrical connection with the polysilicon field plate on one of the plurality of the pressure-resistant rings.
In some examples of the present invention, the plurality of the pressure-resistant rings are arranged at intervals, the plurality of the polysilicon field plates are arranged in a one-to-one correspondence, and one end of the metal connecting channel is respectively in contact electrical connection with the polysilicon field plates on at least two of the plurality of the pressure-resistant rings.
In some examples of the present invention, the emitter layer is at least one, and at least one of the emitter layers and at least one of the compression rings are in one-to-one correspondence.
In some examples of the present invention, the semiconductor device has a transition region connected between the active region and the termination region, and a metal layer is disposed on an upper surface of the transition region near the active region, the metal layer is in metal connection with the emitter, and the other end of the metal connection channel is in contact electrical connection with the metal layer.
In some examples of the present invention, the metal connection channel includes a first portion penetrating the through hole and electrically connected to the polysilicon field plate contact, a second portion electrically connected to the emitter metal contact, and a third portion extending in a vertical direction, the second portion being connected between the first portion and the third portion.
In some examples of the present invention, the widths of the cross-sections in the up-down direction of the first portion and the third portion are equal, and the width of the cross-section in the up-down direction of the second portion is smaller than the width of the cross-section in the up-down direction of the first portion and the third portion.
In some examples of the invention, the doping concentration of the emitter layer is greater than the doping concentration of the drift layer.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
Fig. 1 is a schematic view of a semiconductor device according to an embodiment of the present invention;
fig. 2 is a partial schematic view of a semiconductor device according to an embodiment of the present invention;
fig. 3 is a schematic view of a semiconductor device according to another embodiment of the present invention;
Fig. 4 is a partial schematic view of a semiconductor device according to an embodiment of the present invention;
Fig. 5 is a partial schematic view of a semiconductor device according to other embodiments of the present invention;
fig. 6 is a partial schematic view of a semiconductor device according to an embodiment of the present invention;
Fig. 7 is a partial schematic view of a semiconductor device according to an embodiment of the present invention;
fig. 8 is a partial schematic view of a semiconductor device according to an embodiment of the present invention;
fig. 9 is a flowchart of the fabrication of a semiconductor device according to an embodiment of the present invention.
Reference numerals:
100. A semiconductor device;
1. an active region;
2. A transition zone; 201. a metal layer;
3. A termination region; 4. a drift layer; 5. a pressure ring; 6. a field stop layer; 7. a collector layer; 8. an emitter layer; 9. an emitter metal;
10. a metal connection channel; 1001. a first portion; 1002. a second portion; 1003. a third section;
11. A polysilicon field plate; 12. a dielectric layer; 1201. perforating;
13. a base region; 14. a carrier storage layer; 15. a collector metal layer; 16. a gate; 17. an emitter region; 18. a groove.
Detailed Description
Embodiments of the present invention will be described in detail below, by way of example with reference to the accompanying drawings.
A semiconductor device 100 according to an embodiment of the present invention is described below with reference to fig. 1 to 8. The semiconductor device 100 is, for example, a reverse-turn-on insulated gate bipolar transistor. In the following description, N and P denote conductivity types of semiconductors, and in the present invention, the first conductivity type is described as N type and the second conductivity type is described as P type.
As shown in fig. 1-2, a semiconductor device 100 according to the present invention may mainly include: a drift layer 4 of the first conductivity type, a voltage-resistant ring 5 of the second conductivity type, a field stop layer 6, and a collector layer 7, wherein the voltage-resistant ring 5 is provided at a portion of the drift layer 4 corresponding to the termination region 3 of the semiconductor device 100, and an upper surface of the voltage-resistant ring 5 constitutes a portion of an upper surface of the drift layer 4.
Specifically, the drift layer 4 of the first conductivity type, the withstand voltage ring 5 of the second conductivity type, the field stop layer 6, and the collector layer 7 are provided in the semiconductor device 100, and the field stop layer 6 is provided on the lower surface of the drift layer 4, and the collector layer 7 is provided on the lower surface of the field stop layer 6, so that a basic structure of the semiconductor structure can be formed, ensuring normal operation of the semiconductor device 100.
Further, in consideration of the fact that the electric field strength of the termination region 3 of the semiconductor device 100 is high, the voltage applied per unit length is high, and voltage breakdown is likely to occur there, the voltage resistance ring 5 is provided on the surface of the drift layer 4 at a portion corresponding to the termination region 3 of the semiconductor device 100, so that the voltage resistance ring 5 can optimize the electric field distribution of the termination region 3 and improve the voltage resistance capability of the termination region 3.
Further, an emitter layer 8 is provided in the collector layer 7, and the emitter layer 8 is located at a portion of the collector layer 7 corresponding to the termination region 3. Specifically, the conductivity type of the collector layer 7 is the second conductivity type, the conductivity type of the emitter layer 8 in the collector layer 7 is the first conductivity type, and the emitter layer 8 is disposed at a portion of the collector layer 7 corresponding to the termination region 3, so that the first conductivity type emitter layer 8 in the collector layer 7, the drift layer 4 of the first conductivity type, and the second conductivity type voltage-resistant ring 5 in the termination region 3 form a reverse conduction structure in the semiconductor device 100, and reverse conduction of the semiconductor device 100 can be ensured.
In the prior art, an insulated gate bipolar transistor and a fast recovery diode in a reverse conducting insulated gate bipolar transistor are integrally arranged in an active area of a semiconductor device, and need to occupy a part of the area of the active area of the semiconductor device. In addition, in order to achieve the theoretical performance of the insulated gate bipolar transistor, the area of the active region of the insulated gate bipolar transistor needs to be increased, so that heat generated during the operation of the insulated gate bipolar transistor can be increased, and the reliability of the insulated gate bipolar transistor is reduced.
Further, in the embodiment of the present invention, the emitter layer 8 structure forming the fast recovery diode is disposed at the portion of the semiconductor device 100 corresponding to the termination region 3, so that the fast recovery diode structure can be disposed at the termination region 3, not only the reverse conduction of the semiconductor device 100 can be achieved, but also the structure disposed in the active region 1 in the semiconductor device 100 can be reduced, so that the area of the active region 1 can be used as much as possible for disposing the insulated gate bipolar transistor structure, and the area utilization rate of the active region 1 can be improved.
In addition, under the condition that the theoretical performance of the insulated gate bipolar transistor meets the requirement, the area of the active region 1 of the semiconductor device 100 can be reduced, so that the heat generated by the insulated gate bipolar transistor during operation is reduced, the power consumption of the semiconductor device 100 is reduced, the whole area of the semiconductor device 100 is reduced, and the reliability of the semiconductor device 100 is improved.
By providing the emitter layer 8 at a position of the collector layer 7 corresponding to the termination region 3, the semiconductor device 100 can be turned on reversely, the area utilization ratio of the semiconductor device 100 can be improved, and the entire area of the semiconductor device 100 can be prevented from being increased, thereby contributing to the reduction of power consumption of the semiconductor device 100 and the improvement of reliability of the semiconductor device 100 while realizing the reverse conduction of the semiconductor device 100.
As shown in fig. 1 to 2, an emitter metal 9 is provided on the upper surface of the drift layer 4 corresponding to the active region 1 of the semiconductor device 100, and a metal connection channel 10 is connected between the voltage resistance ring 5 and the emitter metal 9. Specifically, the emitter metal 9 is disposed on the upper surface of the drift layer 4 corresponding to the active region 1 of the semiconductor device 100, so as to form a basic structure of the insulated gate bipolar transistor, and ensure that the insulated gate bipolar transistor operates normally in the semiconductor device 100. A metal connecting channel 10 is connected between the voltage-resistant ring 5 and the emitter metal 9, so that the fast recovery diode arranged in the terminal area 3 and the insulated gate bipolar transistor arranged in the active area 1 can be connected in reverse parallel, and the reverse conduction insulated gate bipolar transistor can work normally.
As shown in fig. 1,2, 6, 7 and 8, a polysilicon field plate 11 is disposed above the surface of the pressure-resistant ring 5, a dielectric layer 12 is disposed above the surface of the polysilicon field plate 11, a through hole 1201 is formed in the dielectric layer 12, one end of a metal connection channel 10 penetrates through the through hole 1201 and is in contact electrical connection with the polysilicon field plate 11, and the other end of the metal connection channel 10 is in contact electrical connection with an emitter metal 9. Specifically, a polysilicon field plate 11 is disposed above the surface of the pressure-resistant ring 5, and the polysilicon field plate 11 has high conductivity and low resistivity and can be used to connect the pressure-resistant ring 5 to other structures for electrical conduction. The dielectric layer 12 is provided above the surface of the polysilicon field plate 11, and the dielectric layer 12 has insulation properties, so that other structures in the semiconductor device 100 can be prevented from being electrically contacted with the polysilicon field plate 11, and thus the reliability of circuit communication in the semiconductor device 100 can be prevented. The dielectric layer 12 is provided with a through hole 1201, so that the polysilicon field plate 11 corresponding to the through hole 1201 is exposed, so that other structures in the semiconductor device 100 are electrically connected with the polysilicon field plate 11.
Further, the metal connection channel 10 has conductivity, one end of the metal connection channel 10 is provided with a through hole 1201, and can be in contact with the polysilicon field plate 11, so that the polysilicon field plate 11 is electrically connected with the metal connection channel 10, and the current can be guaranteed to be conducted between the metal connection channel 10 and the polysilicon field plate 11, and the other end of the metal connection channel 10 is in contact with the emitter metal 9, so that the emitter metal 9 is electrically connected with the metal connection channel 10, and the current can be guaranteed to be conducted between the metal connection channel 10 and the emitter metal 9, so that the fast recovery diode and the insulated gate bipolar transistor can be reversely connected in parallel, and the structural reliability of the semiconductor device 100 is guaranteed.
According to some embodiments of the present invention, as shown in fig. 1-4, the number of the compression rings 5 is plural, the number of the plurality of compression rings 5 is plural, the number of the polysilicon field plates 11 is plural, the plurality of polysilicon field plates 11 are disposed in one-to-one correspondence with the plurality of compression rings 5, and one end of the metal connection channel 10 is in contact electrical connection with the polysilicon field plate 11 on one of the plurality of compression rings 5. Specifically, a plurality of the voltage-resistant rings 5 may be provided on the terminal area 3, and the plurality of voltage-resistant rings 5 may be provided at intervals, so that the result of optimizing the electric field distribution of the voltage-resistant rings 5 to the terminal area 3 may be enhanced, and the voltage-resistant capability of the terminal area 3 may be further improved. The polysilicon field plates 11 are plural, and the plural polysilicon field plates 11 are disposed in one-to-one correspondence with the plural compression rings 5, so that the plural compression rings 5 can be electrically connected with other structures in the semiconductor device 100, which is beneficial to improving the connection convenience of the semiconductor device 100.
Further, in the embodiment of the present invention, a fast recovery diode structure is disposed in the semiconductor device 100, and one end of the metal connection channel 10 is electrically connected to the polysilicon field plate 11 on one of the plurality of voltage-resistant rings 5 in contact, so as to ensure that the fast recovery diode structure is connected in anti-parallel with the insulated gate bipolar transistor structure.
According to other embodiments of the present invention, as shown in fig. 1,2, 3 and 5, the number of the compression rings 5 is plural, the number of the plurality of compression rings 5 is plural, the number of the polysilicon field plates 11 is plural, the plurality of polysilicon field plates 11 are disposed in one-to-one correspondence with the plurality of compression rings 5, and one end of the metal connection channel 10 is respectively in contact electrical connection with the polysilicon field plates 11 on at least two of the plurality of compression rings 5. Specifically, a plurality of the voltage-resistant rings 5 may be provided on the terminal area 3, and the plurality of voltage-resistant rings 5 may be provided at intervals, so that the result of optimizing the electric field distribution of the voltage-resistant rings 5 to the terminal area 3 may be enhanced, and the voltage-resistant capability of the terminal area 3 may be further improved. The polysilicon field plates 11 are plural, and the plural polysilicon field plates 11 are disposed in one-to-one correspondence with the plural compression rings 5, so that the plural compression rings 5 can be electrically connected with other structures in the semiconductor device 100, which is beneficial to improving the connection convenience of the semiconductor device 100.
Further, in the embodiment of the present invention, at least two fast recovery diode structures are disposed in the semiconductor device 100, and one end of the metal connection channel 10 is electrically connected to the polysilicon field plates 11 on at least two of the plurality of voltage-resistant rings 5 in contact, so that the fast recovery diode structures of at least two of the semiconductor device 100 are connected in anti-parallel with the insulated gate bipolar transistor structures.
As shown in connection with fig. 1, the number of emitter layers 8 is at least one, and at least one emitter layer 8 corresponds to at least one compression ring 5 one by one. Specifically, the number of emitter layers 8 needs to be set according to the number of fast recovery diode structures in the semiconductor device 100. According to some embodiments of the present invention, the number of emitter layers 8 is one, and the emitter layers 8 are disposed corresponding to one voltage-resistant ring 5 to which the metal connection channel 10 is connected, so that the metal connection channel 10 is electrically connected to the fast recovery diode structure on the termination region 3. According to other embodiments of the present invention, the number of emitter layers 8 is plural, and the plural emitter layers 8 are disposed in one-to-one correspondence with the plural voltage-resistant rings 5 to which the metal connection channels 10 are respectively connected, so that the metal connection channels 10 are respectively electrically connected with the plural fast recovery diode structures disposed in parallel on the termination region 3.
As shown in fig. 1, the semiconductor device 100 has a transition region 2, the transition region 2 is connected between the active region 1 and the terminal region 3, a metal layer 201 is disposed on the upper surface of the transition region 2 near the active region 1, the metal layer 201 is connected to the emitter metal 9, and the other end of the metal connection channel 10 is in contact electrical connection with the metal layer 201. Specifically, a transition region 2 is further provided in the semiconductor device 100, and the transition region 2 is provided between the active region 1 and the terminal region 3 for transitioning the active region 1 and the terminal region 3. The upper surface of the transition region 2 is provided with the metal layer 201 near the active region 1, the metal layer 201 has a conductive effect, the metal layer 201 is connected with the emitter metal 9, the metal layer 201 and the emitter metal 9 can be electrically connected, the distance between the metal layer 201 and the voltage-resistant ring 5 is shorter than the distance between the emitter metal 9 and the voltage-resistant ring 5, the other end of the metal connecting channel 10 is in contact electrical connection with the metal layer 201, the reverse parallel connection of a fast recovery diode structure and an insulated gate bipolar transistor structure in the semiconductor device 100 can be ensured, the structural reliability of the insulated gate bipolar transistor can be ensured, and the reliability of the semiconductor device 100 can be improved.
As shown in fig. 1, the metal connection channel 10 includes a first portion 1001, a second portion 1002, and a third portion 1003, the first portion 1001 is perforated with a perforation 1201 and is in contact electrical connection with the polysilicon field plate 11, the third portion 1003 is in contact electrical connection with the emitter metal 9, the first portion 1001 and the third portion 1003 are provided extending in the up-down direction, and the second portion 1002 is connected between the first portion 1001 and the third portion 1003. Specifically, the metal connection channel 10 may be divided into a first portion 1001, a second portion 1002 and a third portion, where the first portion 1001 is penetrated by the through hole 1201 and extends into the through hole 1201, so that the metal connection channel can be electrically connected with the polysilicon field plate 11 below the dielectric layer 12 in a contact manner, and the through hole 1201 on the dielectric layer 12 has a certain height, so that the first portion 1001 of the metal connection channel 10 can be reinforced and supported, so as to enhance the connection reliability of the metal connection channel 10 and the polysilicon field plate 11.
Further, the third portion 1003 of the metal connection channel 10 is in contact electrical connection with the emitter metal 9, and the second portion 1002 is connected between the first portion 1001 and the second portion 1002, such that the metal connection channel 10 communicates the fast recovery diode structure with the insulated gate bipolar transistor structure. The first portion 1001 and the third portion 1003 are extended in the up-down direction, so that the second portion 1002, the emitter metal 9 and the dielectric layer 12 can be spaced apart from each other in the up-down direction, and a short circuit of the semiconductor device 100 due to a false contact between the metal connection channel 10 and other structures between the fast recovery diode structure and the insulated gate bipolar transistor structure can be prevented, so that the operational reliability of the semiconductor device 100 can be improved.
As shown in fig. 1, the widths of the cross sections in the up-down direction of the first portion 1001 and the third portion 1003 are equal, and the width of the cross section in the up-down direction of the second portion 1002 is smaller than the width of the cross section in the up-down direction of the first portion 1001 and the third portion 1003, so that the material of the metal connection channel 10 can be reduced while the fast recovery diode structure is antiparallel to the insulated gate bipolar transistor structure through the metal connection channel 10, which is advantageous in reducing the production cost of the semiconductor device 100.
According to an embodiment of the invention, the doping concentration of the emitter layer 8 is greater than the doping concentration of the drift layer 4. Specifically, in the embodiment of the present invention, electrons need to be injected into the portion of the collector layer 7 corresponding to the voltage-resistant ring 5 to form the emitter layer 8, and the concentration of the electrons doped in the emitter layer 8 must be greater than the doping concentration of the drift layer 4, so that enough electrons can be injected into the emitter layer 8, so that enough current is output from the emitter layer 8, and the semiconductor device 100 is ensured to work normally.
According to an embodiment of the present invention, the semiconductor device 100 further includes: a base region 13 of the second conductivity type, a carrier storage layer 14, a collector metal layer 15, an insulating layer and a gate electrode 16. The following describes the manufacturing flow of the semiconductor device 100:
s1, providing a semiconductor substrate composed of a collector layer 7 of a second conductivity type, a field stop layer 6 of a first conductivity type, a drift layer 4 of the first conductivity type, a carrier storage layer 14 of the first conductivity type, a base layer of the second conductivity type, and an emitter layer 8 of the second conductivity type, the structure being structure one;
s2, injecting hole ions at a designated position on the basis of the first structure, and activating the injected ions in a rapid thermal annealing mode to form a terminal structure of the semiconductor device 100, wherein the operation can form a main junction and a compression-resistant ring 5, and the structure is a second structure;
S3, depositing a layer of oxide on the basis of a structure II to form a field oxide layer, forming a barrier layer in a designated area of the semiconductor device 100 through photoetching, and forming a carrier storage layer 14 through ion implantation, wherein the structure is a structure III;
S4, forming a barrier layer in a photoetching mode on the basis of a structure III, and etching the appointed active region 1 of the semiconductor device 100 to form a groove 18, wherein the structure is a structure IV;
s5, growing an oxide layer on the basis of the groove 18 in the structure IV to form an oxide of the grid electrode 16, wherein the structure is a structure V;
S6, depositing a layer of polysilicon on the basis of the structure V, and taking out the polysilicon in the redundant area through photoetching and etching processes to form a structure V;
S7, forming a base region 13 of a second conductivity type and an emitter region 17 of a first conductivity type in sequence on the basis of a structure six through photoetching, an ion implantation process and a rapid thermal annealing process to form a structure seven;
S8, depositing a dielectric layer 12 on the basis of the structure seven to form a structure eight;
S9, depositing an emitter metal 9 on the basis of the structure eight, and taking out redundant metal through photoetching and etching processes to form a structure nine, so that the conventional part of the semiconductor device 100 is prepared;
S10, on the basis of a structure nine, carrying out photoetching and etching processes on a dielectric layer 12 of the area above a pressure-resistant ring 5 of the semiconductor device 100 to form a through hole 1201, and depositing a layer of metal at the through hole 1201 to form a structure ten;
s11, depositing a layer of insulating medium on the basis of the structure ten, then performing photolithography on the semiconductor device 100, opening holes in a designated area, depositing metal to form a metal connection channel 10, electrically connecting the voltage-resistant ring 5 area and the emitter metal 9, and removing the redundant photoresist. Depositing an insulating layer on the front surface of the semiconductor device 100 to protect the front surface structure of the semiconductor device 100, wherein the front surface process of the semiconductor device 100 is completed to form a structure eleven;
S12, on the basis of the eleventh structure, performing a back surface process of the semiconductor device 100, firstly grinding and polishing the drift layer 4 of the second conductivity type on the back surface to a specified thickness, then sequentially forming the field stop layer 6 and the collector layer 7 of the second conductivity type on the back surface of the drift layer 4 through an ion implantation process and a rapid thermal annealing process, then injecting electrons into the collector layer 7 of the corresponding region under the voltage-resistant ring 5 through a photolithography process, an ion implantation process and a rapid thermal annealing process to form the emitter layer 8 of the first conductivity type, forming a fast recovery diode structure, and finally depositing collector metal on the back surface of the collector layer 7 to form the collector metal layer 15, thereby completing the preparation of the semiconductor device 100.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplify the description, and do not indicate or imply that the device or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples.
While embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the invention, the scope of which is defined by the claims and their equivalents.
Claims (7)
1. A semiconductor device, comprising:
A drift layer (4) of the first conductivity type;
A second conductivity type pressure-resistant ring (5), the pressure-resistant ring (5) being provided at a portion of the drift layer (4) corresponding to a terminal region (3) of the semiconductor device (100), an upper surface of the pressure-resistant ring (5) constituting a portion of an upper surface of the drift layer (4);
A field stop layer (6), wherein the field stop layer (6) is arranged on the lower surface of the drift layer (4);
A collector layer (7), wherein the collector layer (7) is arranged on the lower surface of the field stop layer (6), an emitter layer (8) is arranged in the collector layer (7), and the emitter layer (8) is positioned at a part of the collector layer (7) corresponding to the terminal region (3);
an emitter metal (9) is arranged on the upper surface of the drift layer (4) corresponding to the active region (1) of the semiconductor device (100), and a metal connecting channel (10) is connected between the pressure-resistant ring (5) and the emitter metal (9);
the upper part of the surface of the pressure-resistant ring (5) is provided with a plurality of polysilicon field plates (11), the plurality of pressure-resistant rings (5) are arranged at intervals, the plurality of polysilicon field plates (11) are arranged in a one-to-one correspondence manner with the plurality of pressure-resistant rings (5), and one end of the metal connecting channel (10) is in contact electrical connection with the polysilicon field plates (11) on one of the plurality of pressure-resistant rings (5); or (b)
The number of the pressure-resistant rings (5) is multiple, the number of the polysilicon field plates (11) is multiple, the polysilicon field plates (11) are arranged in one-to-one correspondence with the pressure-resistant rings (5), one end of the metal connecting channel (10) is respectively and electrically connected with the polysilicon field plates (11) on at least two of the plurality of pressure-resistant rings (5).
2. The semiconductor device according to claim 1, wherein a dielectric layer (12) is disposed above the surface of the polysilicon field plate (11), a through hole (1201) is formed in the dielectric layer (12), one end of the metal connection channel (10) penetrates through the through hole (1201) and is in contact electrical connection with the polysilicon field plate (11), and the other end of the metal connection channel (10) is in contact electrical connection with the emitter metal (9).
3. The semiconductor device according to claim 1, characterized in that the emitter layers (8) are at least one, at least one of the emitter layers (8) and at least one of the pressure rings (5) being in one-to-one correspondence.
4. The semiconductor device according to claim 1, characterized in that the semiconductor device (100) has a transition region (2), the transition region (2) being connected between the active region (1) and the terminal region (3), the upper surface of the transition region (2) being provided with a metal layer (201) near the active region (1), the metal layer (201) being connected with the emitter metal (9), the other end of the metal connection channel (10) being in contact electrical connection with the metal layer (201).
5. The semiconductor device according to claim 2, characterized in that the metal connection channel (10) comprises a first portion (1001), a second portion (1002) and a third portion (1003), the first portion (1001) being provided through the through hole (1201) and being in contact electrical connection with the polysilicon field plate (11), the third portion (1003) being in contact electrical connection with the emitter metal (9), the first portion (1001) and the third portion (1003) extending in an up-down direction, the second portion (1002) being connected between the first portion (1001) and the third portion (1003).
6. The semiconductor device according to claim 5, wherein a width of a cross section in a vertical direction of the first portion (1001) and the third portion (1003) is equal, and a width of a cross section in a vertical direction of the second portion (1002) is smaller than a width of a cross section in a vertical direction of the first portion (1001) and the third portion (1003).
7. The semiconductor device according to claim 1, characterized in that the doping concentration of the emitter layer (8) is greater than the doping concentration of the drift layer (4).
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