CN117648209A

CN117648209A - Method and system for high-speed communication of FPGA and ARM

Info

Publication number: CN117648209A
Application number: CN202311661135.8A
Authority: CN
Inventors: 阮家明; 周伯齐; 梁乐荣; 朱雅
Original assignee: Guangzhou Tronlong Electronic Technology Co ltd
Current assignee: Guangzhou Tronlong Electronic Technology Co ltd
Priority date: 2023-12-05
Filing date: 2023-12-05
Publication date: 2024-03-05

Abstract

The invention discloses a method and a system for high-speed communication of an FPGA and an ARM, wherein the method for high-speed communication of the FPGA and the ARM comprises the following steps: s1: the FPGA end is connected with the ARM end through the CSI interface; s2: the FPGA end transmits the data through the CSI interface; s3: the ARM end communicates with the CSI interface through the V4L2 subsystem to acquire data. According to the invention, the FPGA end transmits data through the CS I interface, so that high-speed data transmission can be realized; the ARM end communicates with the CS I interface through the V4L2 subsystem to collect data, so that high-speed collection of FPGA data can be realized, the high-speed communication between the FPGA and the ARM is realized by means of the CSI interface and the V4L2 subsystem, the FPGA does not need to rely on a special I P core, the high-speed communication between the FPGA and the ARM can be realized at low cost, and the FPGA has universality, is simple to realize, is beneficial to transplanting and developing in different ARM and FPGA platforms, and is convenient to expand functions.

Description

Method and system for high-speed communication of FPGA and ARM

Technical Field

The invention relates to the technical field of FPGA and ARM communication, in particular to a method and a system for high-speed communication of an FPGA and an ARM.

Background

In the field of communication, the FPGA and the ARM need to communicate with each other so as to acquire the data of the FPGA through the ARM for further processing. The prior art generally employs the following ways for communication between FPGA and ARM: (1) The parallel IO interface is used for communication, the implementation scheme has no universality and is complex to implement, and the transplanting development of different ARM platforms is not facilitated; (2) For the insensitive occasion of the cost, usually use PCIe (peripheral component interconnect express, high-speed serial computer expansion bus standard) scheme, but for the sensitive occasion of the cost, the chip with PCIe interface is higher in general cost, and the FPGA end needs the specialized PCIE IP core, complex and has limitation to realize; (3) Low cost communication schemes such as SPI (Serial Peripheral interface ), UART (Universal Asynchronous Receiver/transceiver) and the like are used, but the communication bandwidth of this approach is too low to meet the requirements of high speed communication of FPGA and ARM.

Disclosure of Invention

(one) solving the technical problems

Aiming at the defects of the prior art, the invention provides a method and a system for high-speed communication of an FPGA and an ARM, which can solve the technical problems.

(II) technical scheme

In order to solve the technical problems, the invention provides the following technical scheme: a method for high-speed communication of an FPGA and an ARM, comprising the steps of:

s1: the FPGA end is connected with the ARM end through the CSI interface;

s2: the FPGA end transmits the data through the CSI interface;

s3: the ARM end communicates with the CSI interface through the V4L2 subsystem to acquire data.

Preferably, the method for high-speed communication between the FPGA and the ARM further comprises the following steps: the FPGA end stores data through the FIFO.

Preferably, the method for high-speed communication between the FPGA and the ARM further comprises the following steps: the FPGA end generates a PCLK signal, and further, the FPGA end transmits the PCLK signal to the ARM end through the CSI interface.

Preferably, the method for high-speed communication between the FPGA and the ARM further comprises the following steps: the FPGA end generates a line field synchronizing signal, and further, the FPGA end transmits the line field synchronizing signal to the ARM end through the CSI interface.

Preferably, step S3 is followed by step S4: the ARM end processes the data through the application program.

In order to solve the technical problems, the invention provides another technical scheme as follows: a system for FPGA and ARM high speed communications, comprising: the FPGA end is connected with the ARM end through the CSI interface, the FPGA end is used for transmitting data through the CSI interface, and the ARM end is used for communicating with the CSI interface through the V4L2 subsystem to acquire data.

Preferably, the FPGA end comprises a FIFO for storing data.

Preferably, the FPGA end is further used for generating a PCLK signal, and further, the FPGA end is further used for transmitting the PCLK signal to the ARM end through the CSI interface.

Preferably, the FPGA end is further configured to generate a line-field synchronization signal, and further, the FPGA end is further configured to transmit the line-field synchronization signal to the ARM end through the CSI interface.

Preferably, the ARM end comprises an application program for processing data.

(III) beneficial effects

Compared with the prior art, the invention provides a method and a system for high-speed communication of FPGA and ARM, which have the following beneficial effects: the FPGA end transmits the data through the CSI interface, so that the high-speed transmission of the data can be realized; the invention realizes the high-speed communication between the FPGA and the ARM by means of the CSI interface and the V4L2 subsystem, the FPGA can realize the high-speed communication between the FPGA and the ARM with low cost without relying on a special IP core, and the invention has the advantages of universality, simple realization, easy transplanting development in different ARM and FPGA platforms and convenient expansion of functions.

Drawings

FIG. 1 is a flow chart of the steps of a method of high speed communication between an FPGA and an ARM of the present invention;

FIG. 2 is a functional block diagram of a system for high speed communication of an FPGA and ARM of the present invention;

fig. 3 is a circuit configuration diagram of the FPGA side of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The invention provides a method for high-speed communication between an FPGA and an ARM, which comprises the following steps:

s1: the FPGA end is connected with the ARM end through the CSI interface.

The FPGA end, namely an FPGA chip, FPGA (Field Programmable Gate Array) is a product further developed on the basis of programmable devices such as PAL (programmable array logic), GAL (general array logic) and the like, and is used as a semi-custom circuit in the field of Application Specific Integrated Circuits (ASICs), so that the defect of the custom circuit is overcome, and the defect of limited gate circuits of the original programmable devices is overcome.

ARM end, namely ARM chip, ARM (Advanced RISC Machine) is a processor design technology based on a Reduced Instruction Set (RISC) architecture, is developed by Acorn limited company in UK, and is widely used in various embedded systems and mobile devices, such as smart phones, tablet computers, smart watches, game machines, smart home devices and the like, and the ARM chip is characterized by low power consumption, high performance and flexibility.

The CSI (Camera Serial Interface) interface, namely the camera serial interface, is a serial data transmission protocol, and the CSI is an open standard established for a mobile application processor by the MIPI (Mobile Industry Processor Interface ) alliance, and has the advantages of less interfaces, strong EMI resistance, high transmission speed, low power consumption and the like.

S2: the FPGA end transmits the data through the CSI interface.

In addition, the method for high-speed communication between the FPGA and the ARM further comprises the following steps: the FPGA end stores the data through the FIFO; FIFO First In First Out is a first-in first-out data storage buffer, and the structure of the FIFO memory does not need external read-write address, but controls the read-write by automatic addition operation. It should be understood that step S2 is to transmit the data stored in the FIFO outwards through the CSI interface.

V4L (Video for Linux) is an API interface related to video equipment in a Linux kernel, and relates to the collection and processing of audio and video information of the video equipment and the control of the video equipment; V4L appears in the Linux kernel 2.1 version, and the Linux kernel 2.5 version promotes a V4L2 (Video for Linux Two) subsystem with more and more stable functions through modifying bug and adding functions. In the step S3, the ARM end communicates with the CSI interface through the V4L2 subsystem to collect data transmitted by the FPGA end.

Preferably, the method for high-speed communication between the FPGA and the ARM of the invention further comprises the following steps: the FPGA end generates a PCLK signal, and further, the FPGA end transmits the PCLK signal to the ARM end through the CSI interface. The PCLK (Pixelclock) signal is a pixel clock signal, and the PCLK signal is used for providing a communication clock, so as to control the data to be transmitted sequentially in the step S2 through the PCLK signal, and in addition, the correctness of data transmission and data reading is better ensured through the PCLK signal.

Preferably, the method for high-speed communication between the FPGA and the ARM of the invention further comprises the following steps: the FPGA end generates a line field synchronizing signal, and further, the FPGA end transmits the line field synchronizing signal to the ARM end through the CSI interface. The line-field synchronizing signal is used for synchronizing the data transmitted through the CSI interface, and comprises a line synchronizing signal and a field synchronizing signal, so that the ARM end keeps synchronization with the FPGA end on the line scanning rule and the field scanning rule of the data.

In addition, step S3 is followed by step S4: and the ARM end processes the data acquired in the step S3 through an application program.

The invention also provides a system for high-speed communication of the FPGA and the ARM, which comprises: the FPGA end 11 and the ARM end 12, the FPGA end 11 is connected with the ARM end 12 through the CSI interface, the FPGA end 11 is used for transmitting data through the CSI interface, and the ARM end 12 is used for communicating with the CSI interface through the V4L2 subsystem to acquire data.

Specifically, the FPGA side includes a FIFO for storing data.

In addition, the FPGA end is also used for generating a line field synchronizing signal, and further, the FPGA end is also used for transmitting the line field synchronizing signal to the ARM end through the CSI interface.

Preferably, the ARM end comprises an application program for processing data.

It should be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Although embodiments of the present invention have been shown, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A method for high-speed communication between an FPGA and an ARM, comprising the steps of:

s1: the FPGA end is connected with the ARM end through the CSI interface;

s2: the FPGA end transmits data through the CSI interface;

s3: the ARM end communicates with the CSI interface through the V4L2 subsystem to acquire the data.

2. The method of FPGA and ARM high-speed communications of claim 1, further comprising: and the FPGA end stores the data through the FIFO.

3. The method of FPGA and ARM high-speed communications of claim 1, further comprising: the FPGA end generates a PCLK signal, and further, the FPGA end transmits the PCLK signal to the ARM end through the CSI interface.

4. The method of FPGA and ARM high-speed communications of claim 1, further comprising: the FPGA end generates a line field synchronizing signal, and further, the FPGA end transmits the line field synchronizing signal to the ARM end through the CSI interface.

5. The method for high-speed communication between FPGA and ARM according to claim 1, further comprising step S4 after said step S3: and the ARM end processes the data through an application program.

6. A system for high speed communication of an FPGA and an ARM comprising: the FPGA end is connected with the ARM end through the CSI interface, the FPGA end is used for transmitting data through the CSI interface, and the ARM end is used for communicating with the CSI interface through the V4L2 subsystem to acquire the data.

7. The FPGA and ARM high-speed communications system of claim 6, wherein: the FPGA end comprises a FIFO for storing the data.

8. The FPGA and ARM high-speed communications system of claim 6, wherein: the FPGA end is further used for generating a PCLK signal, and further, the FPGA end is further used for transmitting the PCLK signal to the ARM end through the CSI interface.

9. The FPGA and ARM high-speed communications system of claim 6, wherein: the FPGA end is further used for generating a line field synchronizing signal, and further, the FPGA end is further used for transmitting the line field synchronizing signal to the ARM end through the CSI interface.

10. The FPGA and ARM high-speed communications system of claim 6, wherein: the ARM end comprises an application program for processing the data.