CN117637657A

CN117637657A - Semiconductor package

Info

Publication number: CN117637657A
Application number: CN202311072612.7A
Authority: CN
Inventors: 张根豪
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-08-26
Filing date: 2023-08-24
Publication date: 2024-03-01
Also published as: US20240071951A1; KR20240029369A

Abstract

A semiconductor package includes: a substrate including a plurality of vias; stacking chips on a substrate; and a mold layer on the substrate and on at least a portion of the chip stack. The chip stack includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; a third semiconductor chip on an uppermost one of the second semiconductor chips; and a non-conductive layer between the first semiconductor chip and the second semiconductor chip. The first chip pad of the first semiconductor chip is bonded to the substrate pad of the substrate. The second chip pad of the uppermost one of the second semiconductor chips is bonded to the third chip pad of the third semiconductor chip. Each second semiconductor chip is electrically connected to the other or the first semiconductor chip of the second semiconductor chips.

Description

Semiconductor package

Technical Field

The present disclosure relates to a semiconductor package and a method of manufacturing the semiconductor package, and in particular, to a stacked semiconductor package that may include a substrate and a plurality of semiconductor chips stacked thereon and a method of manufacturing the stacked semiconductor package.

Background

With recent advances in the electronics industry, the demand for high performance, high speed, and compact electronic components is growing. In order to meet such a demand, a packaging technology for mounting a plurality of semiconductor chips in a single package is being developed.

Recently, demand for portable electronic devices has rapidly increased in the market, and thus, reduction in size and weight of electronic components constituting the portable electronic devices may be required. For this reason, there is a need to develop a packaging technology that reduces the size and weight of each component and integrates a plurality of individual components into a single package. Multiple adhesive members may be used to attach the components to each other, but increasing the number of adhesive members may cause various technical problems.

Disclosure of Invention

One or more example embodiments provide a semiconductor package having improved structural stability and a method of manufacturing the semiconductor package, and a method of reducing a malfunction in a process of manufacturing the semiconductor package and a semiconductor package manufactured thereby.

According to an aspect of an example embodiment, a semiconductor package includes: a substrate including a plurality of vias; stacking chips on a substrate; and a mold layer on the substrate and on at least a portion of the chip stack, wherein the chip stack comprises: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip; a third semiconductor chip on an uppermost one of the second semiconductor chips; and a non-conductive layer between the first semiconductor chip and the second semiconductor chip, wherein the first chip pad of the first semiconductor chip is bonded to the substrate pad of the substrate, wherein each of the first chip pad and the substrate pad comprises the same metal material and forms a first individual structure or layer, wherein the second chip pad of an uppermost one of the second semiconductor chips is bonded to the third chip pad of the third semiconductor chip, wherein each of the second chip pad and the third chip pad comprises the same metal material and forms a second individual structure or layer, each of the second semiconductor chips is electrically connected to the other one of the second semiconductor chips or the first semiconductor chip using a connection terminal on a bottom surface of each of the second semiconductor chips.

According to an aspect of an example embodiment, a semiconductor package includes: a semiconductor substrate; stacking chips on a semiconductor substrate; and a mold layer on the semiconductor substrate and the chip stack, wherein the chip stack comprises: a first semiconductor chip on the semiconductor substrate; a chip structure stacked on the first semiconductor chip; and a non-conductive layer between the first semiconductor chip and a lowermost one of the chip structures and between adjacent chip structures, wherein each chip structure comprises: a second semiconductor chip; a third semiconductor chip on the second semiconductor chip; and a first connection terminal on a bottom surface of the second semiconductor chip, the bottom surface of the first semiconductor chip being in direct contact with a top surface of the semiconductor substrate, wherein in the chip structure, a bottom surface of the third semiconductor chip is in direct contact with the top surface of the second semiconductor chip, wherein a non-conductive layer is disposed around the first connection terminal between the first semiconductor chip and a lowermost one of the chip structures and between adjacent chip structures, and wherein the non-conductive layer is spaced apart from the semiconductor substrate.

According to an aspect of an example embodiment, a semiconductor package includes: a semiconductor substrate including a substrate pad; a first semiconductor chip on the semiconductor substrate, the first semiconductor chip including a first chip pad bonded to a substrate pad of the semiconductor substrate, each of the first chip pad and the substrate pad including the same metal material and forming a single structure or layer; a second semiconductor chip on the first semiconductor chip and electrically connected to the first semiconductor chip using connection terminals provided on a bottom surface of the second semiconductor chip; a non-conductive layer on a bottom surface of the second semiconductor chip and around the connection terminals; a third semiconductor chip on the second semiconductor chip, the second semiconductor chip and the third semiconductor chip including a second chip pad and a third chip pad, respectively, wherein each of the second chip pad and the third chip pad includes the same metal material and is bonded to each other and forms a single structure or layer; and a mold layer on the semiconductor substrate and the first to third semiconductor chips, wherein the non-conductive layer is spaced apart from the semiconductor substrate and the third semiconductor chip.

According to an aspect of an example embodiment, a method of manufacturing a semiconductor package includes: providing a semiconductor substrate comprising substrate pads; providing a first semiconductor chip including a first chip pad; contacting the first semiconductor chip with the semiconductor substrate such that the first chip pad is vertically aligned with the substrate pad; performing a first heat treatment process on the semiconductor substrate and the first semiconductor chip to bond the first semiconductor chip to the semiconductor substrate; providing a second semiconductor chip including a second chip pad; providing a third semiconductor chip including a third chip pad; contacting the third semiconductor chip with the second semiconductor chip such that the second chip pad is vertically aligned with the third chip pad; performing a second heat treatment process on the second semiconductor chip and the third semiconductor chip to bond the third semiconductor chip to the second semiconductor chip; and mounting the second semiconductor chip on the first semiconductor chip using the first connection terminal, wherein each of the substrate pad and the first chip pad includes the same metal material and forms a single structure or layer through a first heat treatment process, and the second chip pad and the third chip pad form a single structure or layer formed of the same metal material as the substrate pad through a second heat treatment process.

Drawings

The above and other aspects and features will become more apparent from the following description of exemplary embodiments taken in conjunction with the accompanying drawings in which:

fig. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

Fig. 2 is an enlarged cross-sectional view showing a region a of fig. 1.

Fig. 3, 4, 5, 6, 7, and 8 are cross-sectional views each showing a semiconductor package according to an embodiment.

Fig. 9 is a cross-sectional view illustrating a semiconductor module according to an embodiment.

Fig. 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, and 20 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment.

Detailed Description

Example embodiments will be described more fully with reference to the accompanying drawings, in which example embodiments are shown. The embodiments described herein are provided as examples, and thus, the present disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not preclude the association with one or more features of another example or embodiment also or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. Such as "at least one of … …," when following a column of elements, modifies the entire column of elements rather than modifying individual elements of the list. For example, the expression "at least one of a, b and c" should be understood to include a only a, b only, c only, both a and b, both a and c, both b and c, or all of a, b and c.

Fig. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment. Fig. 2 is an enlarged cross-sectional view showing a region a of fig. 1.

The semiconductor package according to an embodiment may be a stacked package implemented using a via pattern. For example, the same kind of semiconductor chips may be stacked on the base substrate and may be electrically connected to each other through a via pattern penetrating the base substrate. The semiconductor chips may be coupled to each other using chip terminals provided on bottom surfaces thereof.

Referring to fig. 1 and 2, a base substrate 100 may be provided. The base substrate 100 may include integrated circuits provided therein. In detail, the base substrate 100 may be a base semiconductor chip including an electronic device (e.g., a transistor). For example, the base substrate 100 may be a wafer level die formed of a semiconductor material, such as silicon (Si). Fig. 1 shows an example in which the base substrate 100 is a base semiconductor chip, but the embodiment is not limited to this example. In an embodiment, the base substrate 100 may be a substrate (e.g., a Printed Circuit Board (PCB)) in which electronic components (e.g., transistors) are not provided. The silicon wafer may be thinner than a Printed Circuit Board (PCB). Hereinafter, the base substrate 100 may be referred to as a base semiconductor chip 100.

The base semiconductor chip 100 may include a first circuit layer 110, a first via 120, a first rear pad 130, a first protective layer 140, and a first front pad 150.

The first circuit layer 110 may be provided on the bottom surface of the base semiconductor chip 100. The first circuit layer 110 may include the aforementioned integrated circuits. For example, the first circuit layer 110 may be a memory circuit, a logic circuit, or a combination thereof. That is, the bottom surface of the base semiconductor chip 100 may be an active surface. The first circuit layer 110 may include, for example, one or more of an electronic component (e.g., a transistor), an insulating pattern, and an interconnect pattern.

The first via 120 may be provided to vertically penetrate and extend through the base semiconductor chip 100. For example, the first via 120 may connect an element provided on the top surface of the base semiconductor chip 100 to the first circuit layer 110. The first via 120 and the first circuit layer 110 may be electrically connected to each other. In an embodiment, a plurality of first passages 120 may be provided. In some embodiments, an insulating layer (not shown) may be provided to surround the first via 120. For example, the insulating layer (not shown) may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a low-k dielectric material.

The first rear pad 130 may be disposed on the top surface of the base semiconductor chip 100. The first rear pad 130 may be coupled to the first via 120. In an embodiment, a plurality of first rear pads 130 may be provided. In this case, the plurality of first rear pads 130 may be coupled to the plurality of first vias 120, respectively, and the first rear pads 130 may be arranged in a shape corresponding to the arrangement of the first vias 120. The first rear pad 130 may be coupled to the first circuit layer 110 through the first via 120. The first rear pad 130 may be formed of or include at least one of various metal materials, such as copper (Cu), aluminum (Al), and/or nickel (Ni).

The first protective layer 140 may be disposed on the top surface of the base semiconductor chip 100 and around a portion of the first rear pad 130. For example, the first protective layer 140 may be disposed around the bottom of the first rear pad 130, which is adjacent to the top surface of the base semiconductor chip 100. In an embodiment, the first protective layer 140 may surround at least a portion of the first rear pad 130. For example, in an embodiment, the first protective layer 140 may surround the bottom of the first rear pad 130 adjacent to the top surface of the base semiconductor chip 100. The first protective layer 140 may be disposed such that at least a portion of the first rear pad 130 is exposed. For example, in an embodiment, the first protective layer 140 may be disposed around the bottom of the first rear pad 130, and the top of the first rear pad 130 may be exposed. In some embodiments, a top surface of the first protective layer 140 may be coplanar with a top surface of the first rear pad 130. The base semiconductor chip 100 may be protected by the first protection layer 140. The first protective layer 140 may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN).

The first front pad 150 may be disposed on the bottom surface of the base semiconductor chip 100. In more detail, the first front pad 150 may be exposed to the outside of the first circuit layer 110 near the bottom surface of the first circuit layer 110. The bottom surface of the first front pad 150 may be coplanar with the bottom surface of the first circuit layer 110. The first front pad 150 may be electrically connected to the first circuit layer 110. In an embodiment, a plurality of first front pads 150 may be provided. The first front pad 150 may be formed of or include at least one of various metal materials, such as copper (Cu), aluminum (Al), and/or nickel (Ni).

Although not shown, in some embodiments, the base semiconductor chip 100 may further include a lower protective layer (not shown). A lower protective layer (not shown) may be disposed on the bottom surface of the base semiconductor chip 100 and the first circuit layer 110. In an embodiment, the lower protection layer may cover the first circuit layer 110. The first circuit layer 110 may be protected by a lower protection layer (not shown). A lower protective layer (not shown) may expose at least a portion of the first front pad 150. The lower protective layer (not shown) may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN).

The external terminal 160 may be provided on the bottom surface of the base semiconductor chip 100. The external terminal 160 may be disposed on the first front pad 150. The external terminal 160 may be electrically connected to the first circuit layer 110 and the first via 120. In an embodiment, the external terminal 160 may be disposed under the first via 120. In this case, the first via 120 may penetrate the first circuit layer 110 and may be exposed to the outside of the first circuit layer 110 near the bottom surface of the first circuit layer 110, and the external terminal 160 may be directly coupled to the first via 120. In one embodiment, a plurality of external terminals 160 may be provided. In this case, the plurality of external terminals 160 may be coupled to the plurality of first front pads 150, respectively. The external terminal 160 may be formed of or include an alloy including at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), and cerium (Ce).

The chip stack CS may be disposed on the base semiconductor chip 100. The chip stack CS may include a plurality of semiconductor chips 210, 220, and 230. The semiconductor chips 210, 220, and 230 may be of the same kind. For example, the semiconductor chips 210, 220, and 230 may be memory chips. The chip stack CS may include a lower semiconductor chip 210 directly connected to the base semiconductor chip 100, an intermediate semiconductor chip 220 disposed on the lower semiconductor chip 210, and an upper semiconductor chip 230 disposed on the intermediate semiconductor chip 220. The lower semiconductor chip 210, the intermediate semiconductor chip 220, and the upper semiconductor chip 230 may be sequentially stacked on the base semiconductor chip 100.

The lower semiconductor chip 210 may include a second circuit layer 211, the second circuit layer 211 being disposed to face the base semiconductor chip 100. The second circuit layer 211 may be provided on the bottom surface of the lower semiconductor chip 210. The second circuit layer 211 may include the aforementioned integrated circuits. For example, the second circuit layer 211 may include a memory circuit. In other words, the bottom surface of the lower semiconductor chip 210 may be an active surface. The second circuit layer 211 may include one or more of an electronic element (e.g., a transistor), an insulating pattern, and an interconnection pattern.

The lower semiconductor chip 210 may include a second protective layer 214 provided opposite to the second circuit layer 211. The second protective layer 214 may be provided on the top surface of the lower semiconductor chip 210. The second protective layer 214 may protect the lower semiconductor chip 210. The second protective layer 214 may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonitride (SiCN).

The lower semiconductor chip 210 may include a second via 212, the second via 212 being provided to penetrate and extend through the lower semiconductor chip 210 in a direction from the second protective layer 214 toward the second circuit layer 211. In an embodiment, a plurality of second passages 212 may be provided. An insulating layer (not shown) may be provided at a portion or all of the second via 212. The insulating layer may surround a portion or all of the second via 212. For example, the insulating layer (not shown) may be formed of or include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a low-k dielectric material. The second via 212 may be electrically connected to the second circuit layer 211.

The second rear pad 213 may be disposed in the second protective layer 214. The second rear pad 213 may have a top surface that is not covered by the second protective layer 214 so that the top surface is exposed and may be connected with other elements. In an embodiment, the second rear pad 213 may have a top surface and the second protective layer 214 may not be disposed on at least a portion of the top surface of the second rear pad 213. The top surface of the second protective layer 214 may be coplanar with the top surface of the second rear pad 213. The second rear pad 213 may be connected to the second via 212. The second front pad 215 may be disposed in the second circuit layer 211. In more detail, the second front pad 215 may be exposed to the outside of the second circuit layer 211 near the bottom surface of the second circuit layer 211. The bottom surface of the second front pad 215 may be coplanar with the bottom surface of the second circuit layer 211. The second front pad 215 may be coupled to the second circuit layer 211. The second rear pad 213 and the second front pad 215 may be electrically connected to each other through the second via 212. In an embodiment, a plurality of second rear pads 213 and a plurality of second front pads 215 may be provided. The second rear pad 213 and the second front pad 215 may be formed of or include at least one of various metal materials, such as copper (Cu), aluminum (Al), and/or nickel (Ni).

The lower semiconductor chip 210 may be mounted on the base semiconductor chip 100. In more detail, the lower semiconductor chip 210 may be disposed on the base semiconductor chip 100. The lower semiconductor chip 210 may be disposed face down on the base semiconductor chip 100. The first rear pad 130 of the base semiconductor chip 100 may be vertically aligned with the second front pad 215 of the lower semiconductor chip 210. The base semiconductor chip 100 and the lower semiconductor chip 210 may contact each other such that the first rear pad 130 is connected to the second front pad 215.

The lower semiconductor chip 210 may be connected to the base semiconductor chip 100. The lower semiconductor chip 210 and the base semiconductor chip 100 may contact each other. At the interface between the lower semiconductor chip 210 and the base semiconductor chip 100, the first rear pad 130 of the base semiconductor chip 100 may be bonded to the second front pad 215 of the lower semiconductor chip 210. Here, the first rear pad 130 and the second front pad 215 may form a metal-to-metal hybrid bonding structure. In this specification, a hybrid joining structure may mean a joining structure in which two materials of the same kind are fused at an interface therebetween. For example, the first rear pad 130 and the second front pad 215 bonded to each other may have a continuous structure, and the first interface IF1 between the first rear pad 130 and the second front pad 215 may be invisible. For example, the first rear pad 130 and the second front pad 215 may be formed of the same material, in which case there may be no interface between the first rear pad 130 and the second front pad 215. In other words, the first rear pad 130 and the second front pad 215 may be provided as a single element. For example, the first rear pad 130 and the second front pad 215 may be bonded or coupled to each other to form a single structure or layer without an interface therebetween.

At the interface between the base semiconductor chip 100 and the lower semiconductor chip 210, the first protective layer 140 of the base semiconductor chip 100 may be bonded to the insulating pattern of the second circuit layer 211 of the lower semiconductor chip 210. Here, the insulating pattern of the second circuit layer 211 and the first protective layer 140 may form a hybrid junction structure of oxide, nitride, or oxynitride. For example, the insulating pattern of the second circuit layer 211 and the first protective layer 140 may be formed of the same material, in which case there may be no interface between the insulating pattern of the second circuit layer 211 and the first protective layer 140. In other words, the insulating pattern of the second circuit layer 211 and the first protective layer 140 may be bonded or coupled to each other to form a single structure or layer without an interface therebetween. However, the embodiment is not limited to this example. The insulating pattern of the second circuit layer 211 and the first protective layer 140 may be formed of different materials and may not have a continuous structure, in which case there may be a visible interface between the insulating pattern of the second circuit layer 211 and the first protective layer 140.

The intermediate semiconductor chip 220 may have substantially the same structure as the lower semiconductor chip 210. For example, the intermediate semiconductor chip 220 may include a third circuit layer 221 provided to face the base semiconductor chip 100, a third protective layer 224 opposite to the third circuit layer 221, a third via 222 provided to penetrate the intermediate semiconductor chip 220 in a direction from the third protective layer 224 toward the third circuit layer 221, a third rear pad 223 provided in the third protective layer 224, and a third front pad 225 provided in the third circuit layer 221. The third circuit layer 221 and the third front pad 225 may be provided on a bottom surface of the intermediate semiconductor chip 220, and the bottom surface of the intermediate semiconductor chip 220 may be an active surface. The third protective layer 224 and the third rear pad 223 may be provided on the top surface of the intermediate semiconductor chip 220.

The upper semiconductor chip 230 may have a substantially similar structure to the lower semiconductor chip 210. For example, the upper semiconductor chip 230 may include a fourth circuit layer 231 provided to face the base semiconductor chip 100 and a fourth front pad 235 provided in the fourth circuit layer 231. In an embodiment, the upper semiconductor chip 230 may not have the via pattern, the rear pad, and the upper protective layer. However, the embodiment is not limited to this example. In an embodiment, the upper semiconductor chip 230 may include at least one of a via pattern, a rear pad, and an upper protective layer. The fourth circuit layer 231 and the fourth front pad 235 may be provided on a bottom surface of the upper semiconductor chip 230, and the bottom surface of the upper semiconductor chip 230 may be an active surface. The upper semiconductor chip 230 may have a greater thickness than the lower semiconductor chip 210 and the middle semiconductor chip 220.

The upper semiconductor chip 230 may be disposed on the middle semiconductor chip 220. In an embodiment, the upper semiconductor chip 230 may be mounted on the middle semiconductor chip 220. In more detail, the upper semiconductor chip 230 may be disposed on the middle semiconductor chip 220 in a face-down manner. The third rear pad 223 of the middle semiconductor chip 220 may be vertically aligned with the fourth front pad 235 of the upper semiconductor chip 230. The upper semiconductor chip 230 and the middle semiconductor chip 220 may contact each other such that the third rear pad 223 is connected to the fourth front pad 235.

The upper semiconductor chip 230 may be connected to the middle semiconductor chip 220. In an embodiment, the upper semiconductor chip 230 and the middle semiconductor chip 220 may contact each other. The third rear pad 223 of the intermediate semiconductor chip 220 may be bonded to the fourth front pad 235 of the upper semiconductor chip 230 at an interface between the upper semiconductor chip 230 and the intermediate semiconductor chip 220. Here, the third rear pad 223 and the fourth front pad 235 may form a metal-to-metal hybrid bonding structure. For example, the third rear pad 223 and the fourth front pad 235 bonded to each other may form a continuous structure, and the second interface IF2 between the third rear pad 223 and the fourth front pad 235 may be invisible. For example, the third rear pad 223 and the fourth front pad 235 may be formed of the same material, in which case there may be no interface between the third rear pad 223 and the fourth front pad 235. In other words, the third rear pad 223 and the fourth front pad 235 may be provided as a single element. For example, the third rear pad 223 and the fourth front pad 235 may be bonded or coupled to each other to form a single structure or layer without an interface therebetween.

At the interface of the upper semiconductor chip 230 and the intermediate semiconductor chip 220, the third protective layer 224 of the intermediate semiconductor chip 220 may be disposed on the insulating pattern of the fourth circuit layer 231 of the upper semiconductor chip 230. In an embodiment, the third protective layer 224 of the intermediate semiconductor chip 220 may be bonded to the insulating pattern of the fourth circuit layer 231 of the upper semiconductor chip 230. The insulating pattern of the fourth circuit layer 231 and the third protective layer 224 may form a hybrid junction structure of one or more of oxide, nitride, oxynitride, and carbonitride, for example. For example, the insulating pattern of the fourth circuit layer 231 and the third protective layer 224 may be formed of the same material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), in which case there may be no interface between the insulating pattern of the fourth circuit layer 231 and the third protective layer 224. In other words, the insulating pattern of the fourth circuit layer 231 and the third protective layer 224 may be bonded or coupled to each other to form a single structure or layer without an interface therebetween. However, the embodiment is not limited to this example. The insulating pattern of the fourth circuit layer 231 and the third protective layer 224 may be formed of different materials and may not have a continuous structure, and a visible interface may exist between the insulating pattern of the fourth circuit layer 231 and the third protective layer 224.

The upper semiconductor chip 230 and the middle semiconductor chip 220 may be bonded or coupled to each other to form a single chip structure.

The intermediate semiconductor chip 220 may be mounted on the lower semiconductor chip 210. For example, the intermediate semiconductor chip 220 may be disposed on the lower semiconductor chip 210 in a face-down manner. The intermediate semiconductor chip 220 may be connected to the lower semiconductor chip 210 through a chip connection terminal 227. The chip connection terminal 227 may be disposed between the second rear pad 213 of the lower semiconductor chip 210 and the third front pad 225 of the intermediate semiconductor chip 220. The lower semiconductor chip 210 and the intermediate semiconductor chip 220 may be spaced apart from each other, and the chip connection terminal 227 may have the same thickness as the distance between the second rear pad 213 and the third front pad 225. In one embodiment, a plurality of chip connection terminals 227 may be provided. The chip connection terminal 227 may electrically connect the lower semiconductor chip 210 to the intermediate semiconductor chip 220. The chip connection terminal 227 may be a solder ball or a solder bump formed of or including an alloy including at least one of tin (Sn), silver (Ag), copper (Cu), nickel (Ni), bismuth (Bi), indium (In), antimony (Sb), and cerium (Ce).

The non-conductive layer 400 may be provided between the lower semiconductor chip 210 and the intermediate semiconductor chip 220. The non-conductive layer 400 may fill at least a portion of a space between the lower semiconductor chip 210 and the intermediate semiconductor chip 220, and may be disposed around the chip connection terminal 227. In an embodiment, the non-conductive layer 400 may surround part or all of the chip connection terminals 227. The non-conductive layer 400 may have an extension portion 405 protruding in an outward direction from the side surface of the lower semiconductor chip 210 and the side surface of the intermediate semiconductor chip 220. The extension portion 405 may be disposed on a portion of the side surface of the lower semiconductor chip 210 and a portion of the side surface of the intermediate semiconductor chip 220. In an embodiment, the extension portion 405 may cover a portion of the side surface of the lower semiconductor chip 210 and a portion of the side surface of the intermediate semiconductor chip 220. The extension portion 405 may extend in a downward direction along a side surface of the lower semiconductor chip 210 and may be spaced apart from a top surface of the base semiconductor chip 100. The extension portion 405 may extend in an upward direction along a side surface of the middle semiconductor chip 220 and may be spaced apart from a bottom surface of the upper semiconductor chip 230. In other words, in an embodiment, the non-conductive layer 400 may not be in contact with the base semiconductor chip 100, and in an embodiment, may not have a portion extending to the upper semiconductor chip 230. The non-conductive layer 400 may be a non-conductive film (NCF) or a non-conductive paste (NCP). The non-conductive layer 400 may be formed of or include an insulating polymer. For example, the non-conductive layer 400 may be formed of an epoxy-based material having no conductive particles therein. Since the non-conductive layer 400 without conductive particles is used, a short problem between the chip connection terminals 227 can be prevented, thereby reducing the pitch of the chip connection terminals 227. In addition, the non-conductive layer 400 may serve as an underfill pattern filling the space between the lower semiconductor chip 210 and the intermediate semiconductor chip 220, and thus, mechanical durability of the chip connection terminal 227 may be improved.

The mold layer 500 may be provided on the base semiconductor chip 100. The mold layer 500 may be disposed on the top surface of the base semiconductor chip 100. In an embodiment, the mold layer 500 may cover the top surface of the base semiconductor chip 100. The side surface of the mold layer 500 may be aligned with the side surface of the base semiconductor chip 100. The mold layer 500 may be disposed around at least a portion of the chip stack CS. The mold layer 500 may be disposed around one or more of the side surface of the lower semiconductor chip 210, the side surface of the middle semiconductor chip 220, and the side surface of the upper semiconductor chip 230. In an embodiment, the mold layer 500 may surround the chip stack CS. The mold layer 500 may cover side surfaces of the lower semiconductor chip 210, the middle semiconductor chip 220, and the upper semiconductor chip 230. The outside surface of the mold layer 500 may be spaced apart from the non-conductive layer 400. The mold layer 500 may be formed of or include an insulating material. For example, the molding layer 500 may be formed of or include an Epoxy Molding Compound (EMC). Although not shown, the mold layer 500 may be disposed around part or all of the lower semiconductor chip 210, the intermediate semiconductor chip 220, and the upper semiconductor chip 230. For example, the mold layer 500 may be disposed around the top surface of the upper semiconductor chip 230. Although not shown, the mold layer 500 may cover the lower semiconductor chip 210, the intermediate semiconductor chip 220, and the upper semiconductor chip 230. The mold layer 500 may cover the top surface of the upper semiconductor chip 230. Although not shown, the mold layer 500 may be formed such that a top surface of the upper semiconductor chip 230 may remain exposed from the mold layer 500.

For a stacked semiconductor package including a plurality of semiconductor chips stacked on a semiconductor substrate, the semiconductor chips 210, 220, and 230 may be vertically stacked on the base semiconductor chip 100. In this case, each of the semiconductor chips 210, 220, and 230 may apply a weight (i.e., gravity due to its mass) to the other chip thereunder, and thus the lowermost one of the semiconductor chips (i.e., the lower semiconductor chip 210) may be subjected to the strongest pressure due to the weight of the other semiconductor chips thereon. In an embodiment in which the non-conductive layer 400 is provided between the semiconductor chips 210, 220, and 230, a portion of the non-conductive layer 400 may laterally protrude from side surfaces of the semiconductor chips 210, 220, and 230 due to the weight of the semiconductor chips. The increase in weight may result in an increase in the horizontal length of the protruding portion of the non-conductive layer 400 and an increase in the area of the side surface of the semiconductor chip covered by the protruding portion of the non-conductive layer 400. As an example, in the case where a non-conductive layer is provided between the lower semiconductor chip 210 and the base semiconductor chip 100, the protruding portion of the non-conductive layer may be formed to have a large protruding length due to the weight of the lower semiconductor chip 210, the intermediate semiconductor chip 220, and the upper semiconductor chip 230. For example, the non-conductive layer may have a protruding portion formed adjacent to or in contact with the outer side surface of the mold layer 500 or extending to a region on the outer side surface of the mold layer 500, in which case there may be a breakage problem between the base semiconductor chip 100 and the mold layer 500. Similarly, in the case where a non-conductive layer is provided between the intermediate semiconductor chip 220 and the upper semiconductor chip 230, the non-conductive layer may have a protruding portion extending to a region on the top surface of the upper semiconductor chip 230, which may cause a breakage problem between the upper semiconductor chip 230 and the mold layer 500.

In an embodiment, the lower semiconductor chip 210 located at the lowermost level of the chip stack CS may be directly connected to the base semiconductor chip 100 without any connection terminal therebetween, and in an embodiment, a non-conductive layer between the lower semiconductor chip 210 and the base semiconductor chip 100 may not be provided. Accordingly, in an embodiment, a malfunction caused by a non-conductive layer between the lower semiconductor chip 210 and the base semiconductor chip 100 may be prevented, thereby realizing a semiconductor package having improved structural stability.

Further, the upper semiconductor chip 230 located at the uppermost level of the chip stack CS may be directly connected to the intermediate semiconductor chip 220 without any connection terminal therebetween, and a non-conductive layer may not be provided between the upper semiconductor chip 230 and the intermediate semiconductor chip 220. Accordingly, in an embodiment, a malfunction caused by the non-conductive layer between the upper semiconductor chip 230 and the middle semiconductor chip 220 may be prevented, thereby realizing a semiconductor package having improved structural stability.

Further, the intermediate semiconductor chip 220 located at the intermediate level of the chip stack CS may be connected to the lower semiconductor chip 210 through the chip connection terminal 227, and a non-conductive layer 400 may be provided between the intermediate semiconductor chip 220 and the lower semiconductor chip 210. The number of non-conductive layers 400 provided in the chip stack CS can be reduced, thereby suppressing warpage problems caused by the non-conductive layers 400 having a large thermal expansion coefficient. In other words, a semiconductor package having improved structural stability can be realized. In the chip stack CS, at least one pair of semiconductor chips (e.g., 100/210 and/or 220/230) may be bonded to each other to form a hybrid bond structure. When each of the semiconductor chips (i.e., 100/210 and/or 220/230) is provided to have a flat contact surface, a better hybrid bonding structure can be achieved, and thus, for the proposed chip stack CS configured to have a suppressed warpage problem, a separation problem can be prevented or suppressed from occurring between the semiconductor chips (e.g., 100/210 and/or 220/230) bonded to each other to form the hybrid bonding structure. Furthermore, according to an embodiment, the number of hybrid bond structures between semiconductor chips (e.g., 100/210 and/or 220/230) provided in the chip stack CS may be reduced. This may facilitate performing a bonding process on semiconductor chips (e.g., 100/210 and/or 220/230) in the chip stack CS.

In the description of the embodiments to be explained below, elements previously described with reference to fig. 1 and 2 may be identified by the same reference numerals for the sake of brevity of description, and overlapping description thereof is not repeated.

Fig. 3 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

Referring to fig. 3, a chip stack CS may be disposed on the base semiconductor chip 100. The chip stack CS may further include an additional semiconductor chip 240, the additional semiconductor chip 240 being disposed between the lower semiconductor chip 210 and the intermediate semiconductor chip 220. The semiconductor chips 210, 220, 230, and 240 of the chip stack CS may be of the same kind. For example, the semiconductor chips 210, 220, 230, and 240 may be memory chips.

The lower semiconductor chip 210 may be mounted on the base semiconductor chip 100. For example, the lower semiconductor chip 210 may be disposed face down on the base semiconductor chip 100, and at an interface of the lower semiconductor chip 210 and the base semiconductor chip 100, the first rear pad 130 of the base semiconductor chip 100 may be bonded to the second front pad 215 of the lower semiconductor chip 210. Here, the first rear pad 130 and the second front pad 215 may form a metal-to-metal hybrid bonding structure.

The additional semiconductor chip 240 may have substantially the same structure as the lower semiconductor chip 210. For example, the additional semiconductor chip 240 may include a fifth circuit layer 241 facing the base semiconductor chip 100, a fifth protective layer 244 opposite to the fifth circuit layer 241, a fifth via 242 provided to penetrate the additional semiconductor chip 240 in a direction from the fifth protective layer 244 toward the fifth circuit layer 241, a fifth rear pad 243 provided in the fifth protective layer 244, and a fifth front pad 245 provided in the fifth circuit layer 241. The fifth circuit layer 241 and the fifth front pad 245 may be provided on a bottom surface of the additional semiconductor chip 240, and the bottom surface of the additional semiconductor chip 240 may be an active surface. A fifth protective layer 244 and fifth rear pads 243 may be provided on the top surface of the additional semiconductor chip 240.

The additional semiconductor chip 240 may be mounted on the lower semiconductor chip 210. For example, the additional semiconductor chip 240 may be disposed face down on the lower semiconductor chip 210. The additional semiconductor chip 240 may be connected to the lower semiconductor chip 210 through the first chip connection terminal 247. The first chip connection terminal 247 may be disposed between the second rear pad 213 of the lower semiconductor chip 210 and the fifth front pad 245 of the additional semiconductor chip 240. The lower semiconductor chip 210 and the additional semiconductor chip 240 may be spaced apart from each other, and the first chip connection terminal 247 may have a thickness substantially equal to a distance between the second rear pad 213 and the fifth front pad 245. The first chip connection terminal 247 may electrically connect the lower semiconductor chip 210 to the additional semiconductor chip 240.

The first non-conductive layer 410 may be provided between the lower semiconductor chip 210 and the additional semiconductor chip 240. The first non-conductive layer 410 may be provided to fill a space between the lower semiconductor chip 210 and the additional semiconductor chip 240 and surround the first chip connection terminal 247. The first non-conductive layer 410 may have a first extension portion 415, the first extension portion 415 protruding in an outward direction from a side surface of the lower semiconductor chip 210 and a side surface of the additional semiconductor chip 240. The first extension portion 415 may be disposed on a portion of the side surface of the lower semiconductor chip 210 and a portion of the side surface of the additional semiconductor chip 240. In an embodiment, the first extension portion 415 may cover a portion of the side surface of the lower semiconductor chip 210 and a portion of the side surface of the additional semiconductor chip 240. The first extension portion 415 may extend in a downward direction along a side surface of the lower semiconductor chip 210 and may be spaced apart from a top surface of the base semiconductor chip 100. In other words, in an embodiment, the first non-conductive layer 410 may not be in contact with the base semiconductor chip 100.

The upper semiconductor chip 230 may be mounted on the middle semiconductor chip 220. For example, the upper semiconductor chip 230 may be disposed face down on the intermediate semiconductor chip 220, and at an interface of the upper semiconductor chip 230 and the intermediate semiconductor chip 220, the third rear pad 223 of the intermediate semiconductor chip 220 may be bonded to the fourth front pad 235 of the upper semiconductor chip 230. Here, the third rear pad 223 and the fourth front pad 235 may form a metal-to-metal hybrid bonding structure.

The intermediate semiconductor chip 220 may be mounted on the additional semiconductor chip 240. For example, the intermediate semiconductor chip 220 may be disposed face down on the additional semiconductor chip 240. The intermediate semiconductor chip 220 may be connected to the additional semiconductor chip 240 through the second chip connection terminal 227. The second chip connection terminal 227 may be disposed between the fifth rear pad 243 of the additional semiconductor chip 240 and the third front pad 225 of the intermediate semiconductor chip 220. The additional semiconductor chip 240 and the intermediate semiconductor chip 220 may be spaced apart from each other, and the thickness of the second chip connection terminal 227 may be substantially equal to the distance between the fifth rear pad 243 and the third front pad 225. The second chip connection terminal 227 may electrically connect the additional semiconductor chip 240 to the intermediate semiconductor chip 220.

The second non-conductive layer 420 may be provided between the additional semiconductor chip 240 and the intermediate semiconductor chip 220. The second non-conductive layer 420 may be provided to fill a space between the additional semiconductor chip 240 and the intermediate semiconductor chip 220 and surround the second chip connection terminal 227. The second non-conductive layer 420 may have a second extension portion 425, the second extension portion 425 protruding in an outward direction from the side surface of the additional semiconductor chip 240 and the side surface of the intermediate semiconductor chip 220. The second non-conductive layer 420 may protrude a distance (i.e., the horizontal width of the second extension portion 425) less than the width of the first extension portion 415. The second extension portion 425 may be disposed on a portion of the side surface of the additional semiconductor chip 240 and a portion of the side surface of the intermediate semiconductor chip 220. In an embodiment, the second extension portion 425 may cover a portion of the side surface of the additional semiconductor chip 240 and a portion of the side surface of the intermediate semiconductor chip 220. The second extension portion 425 may extend in an upward direction along a side surface of the middle semiconductor chip 220 and may be spaced apart from a bottom surface of the upper semiconductor chip 230. In other words, the second non-conductive layer 420 may not extend to a region on the upper semiconductor chip 230.

Fig. 4 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

Referring to fig. 4, a plurality of additional semiconductor chips 240 may be provided. The additional semiconductor chips 240 may be sequentially stacked between the lower semiconductor chip 210 and the intermediate semiconductor chip 220. In the present embodiment, five additional semiconductor chips 240 are shown interposed between the lower semiconductor chip 210 and the intermediate semiconductor chip 220, but the embodiment is not limited to this example. In an embodiment, two or more additional semiconductor chips 240 may be interposed between the lower semiconductor chip 210 and the intermediate semiconductor chip 220.

Two adjacent ones of the additional semiconductor chips 240 may be connected to each other through a third chip connection terminal 249. The third chip connection terminal 249 may be disposed between the fifth rear pad 243 and the fifth front pad 245 facing each other. The thickness of the third chip connection terminal 249 may be equal to the distance between the fifth rear pad 243 and the fifth front pad 245. In an embodiment, a plurality of third chip connection terminals 249 may be provided. The third chip connection terminal 249 may electrically connect adjacent ones of the additional semiconductor chips 240 to each other.

The third non-conductive layer 430 may be provided between adjacent ones of the additional semiconductor chips 240. The third non-conductive layer 430 may be provided to fill a space between adjacent ones of the additional semiconductor chips 240 and surround the third chip connection terminal 249. The third non-conductive layer 430 may have a third extension 435 protruding in an outward direction from a side surface of the additional semiconductor chip 240. The third extension portion 435 may be disposed on a portion of the side surface of the additional semiconductor chip 240 adjacent thereto. In an embodiment, the third extension portion 435 may cover a portion of the side surface of the additional semiconductor chip 240 adjacent thereto. The distance that the third non-conductive layer 430 protrudes (i.e., the horizontal width of the third extension portion 435) may decrease as the distance from the base semiconductor chip 100 increases.

The lowermost one of the additional semiconductor chips 240 may be mounted on the lower semiconductor chip 210. For example, the lowermost one of the additional semiconductor chips 240 may be connected to the lower semiconductor chip 210 through the first chip connection terminal 247. The first non-conductive layer 410 may be provided between the lower semiconductor chip 210 and the lowermost one of the additional semiconductor chips 240. The first non-conductive layer 410 may be provided to fill a space between the lower semiconductor chip 210 and the lowermost one of the additional semiconductor chips 240 and surround the first chip connection terminal 247.

Fig. 5 and 6 are cross-sectional views illustrating a semiconductor package according to an embodiment.

Referring to fig. 5, a chip stack CS may be disposed on the base semiconductor chip 100. The chip stack CS may further include at least one chip structure UCS disposed between the lower semiconductor chip 210 and the intermediate semiconductor chip 220. In the present embodiment, two chip structures UCS are shown interposed between the lower semiconductor chip 210 and the intermediate semiconductor chip 220, but the embodiment is not limited to this example. In an embodiment, one chip structure UCS may be provided between the lower semiconductor chip 210 and the intermediate semiconductor chip 220, or three or more chip structure UCSs may be interposed therebetween.

Each chip structure UCS may include two sub-semiconductor chips 250-1 and 250-2 bonded to each other. The sub-semiconductor chip 250 may be the same kind of semiconductor chip as the lower semiconductor chip 210, the middle semiconductor chip 220, and the upper semiconductor chip 230. For example, the sub-semiconductor chips 250-1 and 250-2 may be memory chips.

The sub-semiconductor chips 250-1 and 250-2 may have substantially the same structure as the lower semiconductor chip 210. For example, each of the sub-semiconductor chips 250-1 and 250-2 may include a sixth circuit layer 251, a sixth protective layer 254 opposite to the sixth circuit layer 251, a sixth via 252 provided to penetrate the sub-semiconductor chip (i.e., 250-1 or 250-2) in a direction from the sixth protective layer 254 toward the sixth circuit layer 251, a sixth rear pad 253 provided in the sixth protective layer 254, and a sixth front pad 255 provided in the sixth circuit layer 251. The sixth circuit layer 251 and the sixth front pad 255 may be provided on the active surfaces of the sub-semiconductor chips 250-1 and 250-2. A sixth protective layer 254 and a sixth rear pad 253 may be provided on the passive surfaces of the sub-semiconductor chips 250-1 and 250-2.

Two sub-semiconductor chips 250-1 and 250-2 may be stacked in each chip structure UCS. An active surface of one of the sub-semiconductor chips (e.g., 250-2) may be bonded to a passive surface of the other of the sub-semiconductor chips (e.g., 250-1). In other words, the sub-semiconductor chips 250-1 and 250-2 may be bonded to each other in a face-to-back manner. In detail, the sub-semiconductor chips 250-1 and 250-2 adjacent to each other may contact each other. The sixth front pad 255 may be bonded to the sixth back pad 253 at the interface of the sub-semiconductor chips 250-1 and 250-2. Here, the sixth front pad 255 and the sixth rear pad 253 may form a metal-to-metal hybrid bonding structure.

In the present embodiment, the chip structure UCS has been described as including two sub-semiconductor chips 250-1 and 250-2, but the embodiment is not limited to this example. For example, as shown in fig. 6, three sub-semiconductor chips 250-1, 250-2, and 250-3 may be sequentially stacked in one chip structure UCS. The active surface of the second sub-semiconductor chip 250-2 may be bonded to the passive surface of the first sub-semiconductor chip 250-1, and the active surface of the third sub-semiconductor chip 250-3 may be bonded to the passive surface of the second sub-semiconductor chip 250-2. In other words, the sub-semiconductor chips 250-1, 250-2, and 250-3 may be bonded to each other in a face-to-back manner. In an embodiment, the chip structure UCS may include four or more sub-semiconductor chips 250. The following description will be given based on the embodiment of fig. 5.

The fourth chip connection terminal 257 may be provided on the bottom surface of the chip structure UCS. For example, the fourth chip connection terminal 257 may be disposed on a sixth front pad 255 provided on the bottom surface of the chip structure UCS (i.e., on the sixth front pad 255 of the lower sub-semiconductor chip 250-1 among the sub-semiconductor chips). Adjacent ones of the lower semiconductor chip 210 and the chip structure UCS may be connected to each other through the fourth chip connection terminal 257. For example, the fourth chip connection terminal 257 may connect the second rear pad 213 and the sixth front pad 255 provided to face each other between the lower semiconductor chip 210 and the chip structure UCS adjacent thereto, or may connect the sixth rear pad 253 and the sixth front pad 255 provided to face each other between adjacent chip structures in the chip structure UCS.

A fourth non-conductive layer 440 may be provided on the bottom surface of the chip structure UCS. For example, a fourth non-conductive layer 440 may be provided under the chip structure UCS to surround the fourth chip connection terminal 257. The fourth non-conductive layer 440 may fill part or all of the space between the lower semiconductor chip 210 and the chip structure UCS adjacent to each other, or may fill all or part of the space between the chip structure UCS adjacent to each other. The fourth non-conductive layer 440 may have a fourth extension portion 445, the fourth extension portion 445 protruding from a side surface of the chip structure UCS in an outward direction.

The intermediate semiconductor chip 220 may be mounted on the chip structure UCS. For example, the intermediate semiconductor chip 220 may be disposed on the uppermost one of the chip structures UCS in a face-down manner. The intermediate semiconductor chip 220 may be connected to an uppermost one of the chip structures UCS through a second chip connection terminal 227. The second chip connection terminal 227 may be disposed between the sixth rear pad 253 of the uppermost one of the chip structures UCS and the third front pad 225 of the intermediate semiconductor chip 220.

The second non-conductive layer 420 may be provided between the uppermost one of the chip structure UCS and the intermediate semiconductor chip 220. The second non-conductive layer 420 may fill all or part of the space between the uppermost one of the chip structure UCS and the intermediate semiconductor chip 220, and may surround the second chip connection terminal 227. The second non-conductive layer 420 may have a second extension portion 425, the second extension portion 425 protruding in an outward direction from a side surface of an uppermost one of the chip structures UCS and a side surface of the intermediate semiconductor chip 220. The length of the protruding portion of the second non-conductive layer 420 (i.e., the horizontal length of the second extension portion 425) may be smaller than the width of the extension portion of the fourth non-conductive layer 440.

Fig. 7 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

Fig. 5 and 6 illustrate an example in which the sub-semiconductor chips 250 in one of the chip structure UCSs are bonded to each other in a face-to-back manner, but the embodiment is not limited to this example.

Referring to fig. 7, an active surface of one sub-semiconductor chip (e.g., 250-2) may be bonded to an active surface of another sub-semiconductor chip (e.g., 250-1). In other words, the sub-semiconductor chips 250 may be bonded to each other in a face-to-face manner. In detail, the sub-semiconductor chips 250-1 and 250-2 adjacent to each other may contact each other. At the interface between the sub-semiconductor chips 250-1 and 250-2, the sixth front pads 255 facing each other may be bonded to each other. Here, the sixth front pad 255 may form a metal-to-metal hybrid bonding structure.

The fourth chip connection terminal 257 may be provided on the bottom surface of the chip structure UCS. For example, the fourth chip connection terminal 257 may be disposed on a sixth rear pad 253 provided on the bottom surface of the chip structure UCS (e.g., on the sixth rear pad 253 of the lower sub-semiconductor chip 250-1 among the sub-semiconductor chips 250-1 and 250-2). Adjacent ones of the lower semiconductor chip 210 and the chip structure UCS may be connected to each other through the fourth chip connection terminal 257. For example, the fourth chip connection terminal 257 may connect the second and sixth rear pads 213 and 253 provided to face each other between the lower semiconductor chip 210 and the chip structure UCS adjacent thereto, or may connect the sixth and rear pads 253 and 253 provided to face each other between adjacent chip structures in the chip structure UCS.

The intermediate semiconductor chip 220 may be mounted on the chip structure UCS. For example, the intermediate semiconductor chip 220 may be disposed face down on an uppermost one of the chip structures UCS. The intermediate semiconductor chip 220 may be connected to an uppermost one of the chip structures UCS through a second chip connection terminal 227. The second chip connection terminal 227 may be disposed between the sixth rear pad 253 of the uppermost one of the chip structures UCS and the third front pad 225 of the intermediate semiconductor chip 220.

According to an embodiment, the semiconductor chips in the chip stack CS may be stacked on the base semiconductor chip 100, where the non-conductive layers may be disposed between the semiconductor chips in an alternating manner or may not be disposed between the semiconductor chips in an alternating manner. When the non-conductive layers protrude from the side surfaces of the chip stack CS, the non-conductive layers may not contact each other, and the protruding portions of the non-conductive layers may be reduced in volume. Thus, a semiconductor package having improved structural stability can be realized.

Fig. 8 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

Referring to fig. 8, a chip stack CS may be disposed on the base semiconductor chip 100. The chip stack CS may include chip structures UCS-1 and UCS-2 and additional semiconductor chips 240 disposed therebetween. The additional semiconductor chip 240 may be provided to have substantially the same or similar features as the additional semiconductor chip 240 described with reference to fig. 3.

The additional semiconductor chip 240 may be mounted on one of the chip structures UCS-1 and UCS-2 (e.g., UCS-1). For example, the additional semiconductor chip 240 may be disposed on the chip structure UCS-1 therebelow in a face-down manner. The additional semiconductor chip 240 may be connected to the chip structure UCS-1 through the first chip connection terminal 247. The first chip connection terminal 247 may be disposed between the sixth rear pad 253 of the chip structure UCS-1 and the fifth front pad 245 of the additional semiconductor chip 240.

The first non-conductive layer 410 may be provided between the additional semiconductor chip 240 and the chip structure UCS-1 thereunder. The first non-conductive layer 410 may be provided to fill a space between the additional semiconductor chip 240 and the chip structure UCS-1 and surround the first chip connection terminal 247.

The other of the chip structures UCS-1 and UCS-2 (e.g., UCS-2) may be mounted on the additional semiconductor chip 240. For example, the chip structure UCS-2 may be disposed on the additional semiconductor chip 240 in a face-down manner. The chip structure UCS-2 may be connected to the additional semiconductor chip 240 through a fourth chip connection terminal 257. The fourth chip connection terminal 257 may be disposed between the fifth rear pad 243 of the additional semiconductor chip 240 and the sixth front pad 255 of the chip structure UCS-2 thereon.

A fourth non-conductive layer 440 may be provided between the additional semiconductor chip 240 and the chip structure UCS-2 thereon. The fourth non-conductive layer 440 may be provided to fill a space between the additional semiconductor chip 240 and the chip structure UCS-2 and surround the fourth chip connection terminal 257.

Fig. 8 shows an example including two chip structures UCS-1 and UCS-2 and one additional semiconductor chip 240 therebetween, but the embodiment is not limited to this example. For example, in one embodiment, a plurality of chip structures and a plurality of additional semiconductor chips 240 may be provided. In this case, the chip structure and the additional semiconductor chip 240 may be stacked on top of each other in an alternating manner.

Referring to fig. 9, a semiconductor module may include, for example, a memory module including a module substrate 910, a chip stack package CS and a Graphics Processing Unit (GPU) 940 mounted on the module substrate 910, and an over mold layer 950 disposed on the chip stack package CS and the graphics processing unit 940. In an embodiment, the over-mold layer 950 may cover the chip stack package CS and the graphics processing unit 940. The semiconductor module may further include an interposer 920 provided on the module substrate 910.

A module substrate 910 may be provided. The module substrate 910 may include a Printed Circuit Board (PCB) having a signal pattern formed on a top surface thereof.

The module terminals 912 may be disposed under the module substrate 910. The module substrate 910 may include solder balls or solder bumps, and the semiconductor module may be classified into a Ball Grid Array (BGA) type, a Fine Ball Grid Array (FBGA) type, or a contact grid array (LGA) type depending on the kind and structure of the module substrate 910.

Interposer 920 may be provided on module substrate 910. The interposer 920 may include first and second substrate pads 922 and 924 located near top and bottom surfaces, respectively, of the interposer 920 and exposed to the exterior of the interposer 920. Interposer 920 may be configured to provide a redistribution structure to chip stack package CS and graphics processing unit 940. Interposer 920 may be flip-chip mounted on module substrate 910. For example, the interposer 920 may be mounted on the module substrate 910 using substrate terminals 926 provided on the second substrate pads 924. The substrate terminals 926 may include solder balls or solder bumps. A first underfill layer 928 may be provided between the module substrate 910 and the interposer 920.

The chip stack package CS may be disposed on the interposer 920. The chip stack package CS may have the same or similar structure as the semiconductor package described with reference to fig. 1, 2, 3, 4, 5, 6, 7, and 8.

The chip stack package CS may be mounted on the interposer 920. For example, the chip stack package CS may be coupled to the first substrate pad 922 of the interposer 920 through the external terminal 160 of the base semiconductor chip 100. A second underfill layer 932 may be provided between the chip stack package CS and the interposer 920. The second underfill layer 932 may be provided to fill a space between the interposer 920 and the base semiconductor chip 100 and surround the external terminals 160 of the base semiconductor chip 100.

Graphics processing unit 940 may be disposed on interposer 920. The graphics processing unit 940 may be disposed spaced apart from the chip stack package CS. The graphic processing unit 940 may be thicker than the semiconductor chips 100, 210, 220, 230, and 240 of the chip stack package CS. Graphics processing unit 940 may include logic circuits. In other words, the graphic processing unit 940 may be a logic chip. Bumps 942 may be provided on the bottom surface of graphics processing unit 940. For example, the graphics processing unit 940 may be coupled to the first substrate pad 922 of the interposer 920 through a bump 942. A third underfill layer 944 may be provided between the interposer 920 and the graphics processing unit 940. A third underfill layer 944 may be provided to fill the space between interposer 920 and graphics processing unit 940 and around bumps 942.

An outer mold layer 950 may be provided on the interposer 920. The outer mold layer 950 may cover the top surface of the interposer 920. The outer mold layer 950 may surround the chip stack package CS and the graphic processing unit 940. The top surface of the outer mold layer 950 may be at the same level as the top surface of the chip stack package CS. The outer mold layer 950 may be formed of or include an insulating material. For example, the outer mold layer 950 may be formed of or include an Epoxy Molding Compound (EMC).

Fig. 10, 11, 12, 13, 14, 15, 16, and 17 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment.

Referring to fig. 10, a base semiconductor chip 100 may be provided. The base semiconductor chip 100 may be provided to have substantially the same or similar features as the base semiconductor chip 100 described with reference to fig. 1. For example, the base semiconductor chip 100 may include a first circuit layer 110 provided on a surface of the base semiconductor chip 100, a first protective layer 140 opposite to the first circuit layer 110, a first via 120 provided to penetrate the base semiconductor chip 100 in a direction from the first protective layer 140 toward the first circuit layer 110, a first rear pad 130 provided in the first protective layer 140, and a first front pad 150 provided in the first circuit layer 110. The first circuit layer 110 may be provided on an active surface of the base semiconductor chip 100, and hereinafter, a surface opposite to the active surface will be referred to as a passive surface of the base semiconductor chip 100.

Although not shown, the base semiconductor chip 100 may be provided on a carrier substrate. The carrier substrate may be: an insulating substrate formed of or comprising glass or polymer; or a conductive substrate formed of or including a metal material. The adhesive member may be provided on a top surface of the carrier substrate. The base semiconductor chip 100 may be attached to the carrier substrate such that the first circuit layer 110 faces the carrier substrate.

The lower semiconductor chip 210 may be provided on the base semiconductor chip 100. The lower semiconductor chip 210 may be provided to have substantially the same or similar features as the lower semiconductor chip 210 described with reference to fig. 1. For example, the lower semiconductor chip 210 may include a second circuit layer 211 provided on a surface of the lower semiconductor chip 210, a second protective layer 214 opposite to the second circuit layer 211, a second via 212 provided to penetrate the lower semiconductor chip 210 in a direction from the second protective layer 214 toward the second circuit layer 211, a second rear pad 213 provided in the second protective layer 214, and a second front pad 215 provided in the second circuit layer 211. The second circuit layer 211 may be provided on an active surface of the lower semiconductor chip 210, and hereinafter, a surface opposite to the active surface will be referred to as a passive surface of the lower semiconductor chip 210.

The lower semiconductor chip 210 may be bonded to the base semiconductor chip 100. The lower semiconductor chip 210 and the base semiconductor chip 100 may be bonded to each other in a chip-to-chip manner. The lower semiconductor chip 210 may be disposed on the base semiconductor chip 100. For example, the active surface of the lower semiconductor chip 210 may face the passive surface of the base semiconductor chip 100. The lower semiconductor chip 210 may be disposed on the base semiconductor chip 100 such that the first rear pad 130 of the base semiconductor chip 100 is vertically aligned with the second front pad 215 of the lower semiconductor chip 210.

A heat treatment process may be performed on the base semiconductor chip 100 and the lower semiconductor chip 210. As a result of the heat treatment process, the first rear pad 130 and the second front pad 215 may be bonded to each other. For example, the first rear pad 130 and the second front pad 215 may be bonded or coupled to each other to form a single structure or layer without an interface therebetween. The bonding of the first rear pad 130 and the second front pad 215 may be achieved in a natural manner. In detail, the first rear pad 130 and the second front pad 215 may be formed of the same material, for example, copper (Cu), in which case the first rear pad 130 and the second front pad 215 may be bonded to each other through a surface activation phenomenon at an interface of the first rear pad 130 and the second front pad 215 that are in contact with each other, or through a subsequent metal-to-metal hybrid bonding process. The insulating pattern of the second circuit layer 211 and the first protective layer 140 may be bonded to each other through a heat treatment process.

Fig. 10 shows an example in which one lower semiconductor chip 210 is bonded to one base semiconductor chip 100 or in which the base semiconductor chip 100 and the lower semiconductor chip 210 are bonded to each other in a chip-to-chip shape, but the embodiment is not limited to this example. In an embodiment, the base semiconductor chip 100 and the lower semiconductor chip 210 may be bonded to each other in a chip-to-wafer shape. For example, the lower semiconductor chip 210 may be bonded to a semiconductor wafer provided with the base semiconductor chip 100, and then a sawing process may be performed on the semiconductor wafer to form a plurality of base semiconductor chips 100 separated from each other.

Referring to fig. 11, an additional semiconductor chip 240 may be provided. The additional semiconductor chip 240 may be provided to have substantially the same or similar features as the additional semiconductor chip 240 described with reference to fig. 4. For example, the additional semiconductor chip 240 may include a fifth circuit layer 241 provided on a surface of the additional semiconductor chip 240, a fifth protective layer 244 opposite to the fifth circuit layer 241, a fifth via 242 provided to penetrate the additional semiconductor chip 240 in a direction from the fifth protective layer 244 toward the fifth circuit layer 241, a fifth rear pad 243 provided in the fifth protective layer 244, and a fifth front pad 245 provided in the fifth circuit layer 241. The fifth circuit layer 241 may be provided on an active surface of the additional semiconductor chip 240, and hereinafter, a surface opposite to the active surface will be referred to as a passive surface of the additional semiconductor chip 240.

Referring to fig. 12, an additional semiconductor chip 240 may be provided on the lower semiconductor chip 210. In more detail, the first chip connection terminal 247 and the first non-conductive layer 410 surrounding it may be provided on the bottom surface (i.e., active surface) of the additional semiconductor chip 240. For example, the first chip connection terminal 247 may be provided on the fifth front pad 245 of the additional semiconductor chip 240. The first non-conductive layer 410 may be a non-conductive film (NCF) or a non-conductive paste (NCP). In the case where the first non-conductive layer 410 is a non-conductive paste, the first non-conductive layer 410 may be formed by a dispensing process of coating the additional semiconductor chip 240 with a liquid non-conductive adhesive. In the case where the first non-conductive layer 410 is a non-conductive film, the first non-conductive layer 410 may be formed by attaching the non-conductive film to the additional semiconductor chip 240. In other words, the first non-conductive layer 410 may be provided on the passive surface of the lower semiconductor chip 210, and the additional semiconductor chip 240 may be provided on the first non-conductive layer 410.

Referring to fig. 13, a thermocompression bonding process may be performed to bond the additional semiconductor chip 240 to the lower semiconductor chip 210. The first chip connection terminal 247 may be provided to electrically connect the lower semiconductor chip 210 to the additional semiconductor chip 240. As an example, the bonding tool 1000 used in the bonding process may have a width smaller than that of the additional semiconductor chip 240. In the case where the additional semiconductor chip 240 is pressed toward the lower semiconductor chip 210, the first non-conductive layer 410 may protrude in an outward direction from a side surface of the lower semiconductor chip 210. The protruding portion of the first non-conductive layer 410 may form a first extension 415 (e.g., of fig. 4). Here, a portion of the first extension portion 415 may extend to a side surface of the lower semiconductor chip 210 to cover a portion of the side surface of the lower semiconductor chip 210. The thickness of the first extension portion 415 may be greater than the distance between the lower semiconductor chip 210 and the additional semiconductor chip 240.

In the case where the thermal compression process is continued, the first non-conductive layer 410 may be partially cured by heat supplied to the additional semiconductor chip 240.

The lower semiconductor chip 210 may be separated from the base semiconductor chip 100 due to the protrusion of the non-conductive layer in the thermocompression bonding process with the non-conductive layer interposed therebetween when the lower semiconductor chip 210 is mounted on the base semiconductor chip 100. According to an embodiment, the lower semiconductor chip 210 may be bonded to the base semiconductor chip 100 to be in direct contact with each other, and then the additional semiconductor chip 240 may be mounted on the lower semiconductor chip 210 with the first non-conductive layer 410 interposed therebetween. Since the first non-conductive layer 410 is formed to be spaced apart from the base semiconductor chip 100, the semiconductor chips 210 and 240 may be prevented from being separated from the base semiconductor chip 100 due to the protrusion of the first non-conductive layer 410. This can reduce failures in the process of manufacturing the semiconductor package.

Referring to fig. 14, the processes described with reference to fig. 11, 12 and 13 may be repeatedly performed to sequentially stack and mount additional semiconductor chips 240 on the lower semiconductor chip 210. For example, a third chip connection terminal 249 and a third non-conductive layer 430 surrounding the same may be provided on a bottom surface (i.e., active surface) of the additional semiconductor chip 240. The additional semiconductor chips 240 may be bonded to each other through a thermocompression bonding process. The third chip connection terminal 249 may be provided to electrically connect the additional semiconductor chips 240 to each other. In case the additional semiconductor chip 240 is pressed, the third non-conductive layer 430 may protrude in an outward direction from a side surface of the additional semiconductor chip 240.

In an embodiment, the thermocompression bonding process may be performed simultaneously on the additional semiconductor chip 240. For example, the additional semiconductor chip 240 may be stacked on the lower semiconductor chip 210, and then a thermocompression bonding process may be performed on the additional semiconductor chip 240 to reflow the first and third chip connection terminals 247 and 249. In the thermocompression bonding process, the first and third non-conductive layers 410 and 430 may protrude to areas outside the side surfaces of the additional semiconductor chip 240. Here, the lower the height of each of the first and third non-conductive layers 410 and 430, the greater the pressure applied by the weight of the semiconductor chips 210 and 240 and the greater the distance protruding from the side surface of the additional semiconductor chip 240.

With the lower semiconductor chip 210 mounted on the base semiconductor chip 100 with the non-conductive layer interposed therebetween, the non-conductive layer may protrude excessively in the thermocompression bonding process. For example, the non-conductive layer may extend to an area outside the side surface of the base semiconductor chip 100. In an embodiment, the non-conductive layer may not be provided between the lower semiconductor chip 210 and the base semiconductor chip 100. Thus, the non-conductive layers 410 and 430 may not protrude excessively. This may reduce failures in the process of manufacturing the conductor package.

Referring to fig. 15, an intermediate semiconductor chip 220 may be provided. The intermediate semiconductor chip 220 may be provided to have substantially the same or similar features as the intermediate semiconductor chip 220 described with reference to fig. 1. For example, the intermediate semiconductor chip 220 may include a third circuit layer 221 provided on a surface of the intermediate semiconductor chip 220, a third protective layer 224 opposite to the third circuit layer 221, a third via 222 provided to penetrate the intermediate semiconductor chip 220 in a direction from the third protective layer 224 toward the third circuit layer 221, a third rear pad 223 provided in the third protective layer 224, and a third front pad 225 provided in the third circuit layer 221. The third circuit layer 221 may be provided on an active surface of the intermediate semiconductor chip 220, and hereinafter, a surface opposite to the active surface will be referred to as a passive surface of the intermediate semiconductor chip 220.

An upper semiconductor chip 230 may be provided. The upper semiconductor chip 230 may be provided to have substantially the same or similar features as the upper semiconductor chip 230 described with reference to fig. 1. For example, the upper semiconductor chip 230 may include a fourth circuit layer 231 provided on a surface of the upper semiconductor chip 230 and a fourth front pad 235 provided in the fourth circuit layer 231. The fourth circuit layer 231 may be provided on an active surface of the upper semiconductor chip 230, and hereinafter, a surface opposite to the active surface will be referred to as a passive surface of the upper semiconductor chip 230.

The upper semiconductor chip 230 may be bonded to the middle semiconductor chip 220. The upper semiconductor chip 230 and the middle semiconductor chip 220 may be bonded to each other in a chip-to-chip shape. The upper semiconductor chip 230 may be disposed on the middle semiconductor chip 220. For example, the active surface of the upper semiconductor chip 230 may face the passive surface of the middle semiconductor chip 220. The upper semiconductor chip 230 may be disposed on the middle semiconductor chip 220 such that the third rear pad 223 of the middle semiconductor chip 220 is vertically aligned with the fourth front pad 235 of the upper semiconductor chip 230.

A heat treatment process may be performed on the intermediate semiconductor chip 220 and the upper semiconductor chip 230. As a result of the heat treatment process, the third rear pad 223 and the fourth front pad 235 may be bonded to each other. For example, the third rear pad 223 and the fourth front pad 235 may be bonded or coupled to each other to form a single structure or layer. The engagement of the third rear pad 223 and the fourth front pad 235 may be achieved in a natural manner. In detail, the third rear pad 223 and the fourth front pad 235 may be formed of the same material, for example, copper (Cu), in which case the third rear pad 223 and the fourth front pad 235 may be bonded to each other through a surface activation phenomenon at an interface of the third rear pad 223 and the fourth front pad 235 that are in contact with each other, or through a subsequent metal-to-metal hybrid bonding process. The insulating pattern of the fourth circuit layer 231 and the third protective layer 224 may be bonded to each other through a heat treatment process.

Fig. 15 shows an example in which one upper semiconductor chip 230 is bonded to one intermediate semiconductor chip 220 or in which the intermediate semiconductor chip 220 and the upper semiconductor chip 230 are bonded to each other in a chip-to-chip shape, but the embodiment is not limited to this example. Referring to fig. 16, a plurality of intermediate semiconductor chips 220 may be formed in a first semiconductor wafer WF 1. In other words, the middle semiconductor chip 220 and the upper semiconductor chip 230 may be bonded to each other in a wafer-to-wafer shape. For example, the intermediate semiconductor chip 220 may be formed on the active surface of the first semiconductor wafer WF 1. In one embodiment, a plurality of upper semiconductor chips 230 may be formed in the second semiconductor wafer WF 2. The upper semiconductor chip 230 may be formed on the active surface of the second semiconductor wafer WF 2. The second semiconductor wafer WF2 may be disposed on the first semiconductor wafer WF1 such that each upper semiconductor chip 230 is aligned with a corresponding one of the intermediate semiconductor chips 220. The active surface of the first semiconductor wafer WF1 may be in contact with the active surface of the second semiconductor wafer WF 2. The thermocompression bonding process may be performed on the first semiconductor wafer WF1 and the second semiconductor wafer WF 2. As a result of the thermocompression bonding process, the intermediate semiconductor chip 220 and the upper semiconductor chip 230 may be bonded to each other. Thereafter, a dicing process may be performed on the first semiconductor wafer WF1 and the second semiconductor wafer WF2 along the sawing lines SL. Accordingly, structures each including the middle semiconductor chip 220 and the upper semiconductor chip 230 may be separated from each other.

Referring to fig. 17, an intermediate semiconductor chip 220 may be provided on the uppermost one of the additional semiconductor chips 240. In more detail, the second chip connection terminal 227 and the second non-conductive layer 420 surrounding the same may be provided on a bottom surface (i.e., active surface) of the intermediate semiconductor chip 220. For example, the second chip connection terminal 227 may be provided on the third front pad 225 of the intermediate semiconductor chip 220. The second non-conductive layer 420 may be a non-conductive film (NCF) or a non-conductive paste (NCP). The second non-conductive layer 420 may be provided on the passive surface of the uppermost one of the additional semiconductor chips 240, and the intermediate semiconductor chip 220 may be provided on the second non-conductive layer 420.

A thermocompression bonding process may be performed to bond the intermediate semiconductor chip 220 to the uppermost one of the additional semiconductor chips 240. The second chip connection terminal 227 may be provided to electrically connect the intermediate semiconductor chip 220 to an uppermost one of the additional semiconductor chips 240. In the case where the intermediate semiconductor chip 220 is pressed toward the uppermost one of the additional semiconductor chips 240, the second non-conductive layer 420 may protrude from the side surface of the intermediate semiconductor chip 220 in an outward direction. The protruding portion of the second non-conductive layer 420 may form a second extension 425 (e.g., of fig. 4). A portion of the second extension portion 425 may extend to a side surface of the intermediate semiconductor chip 220 and be disposed on a portion of the side surface of the intermediate semiconductor chip 220. In an embodiment, a portion of the second extension portion 425 covers a portion of a side surface of the intermediate semiconductor chip 220.

The non-conductive layer may protrude excessively in the thermocompression bonding process in a case where the upper semiconductor chip 230 is mounted on the intermediate semiconductor chip 220 with the non-conductive layer interposed therebetween. For example, the non-conductive layer may extend along a side surface of the upper semiconductor chip 230 and be disposed on at least a portion of the upper semiconductor chip 230. In an embodiment, the non-conductive layer may cover at least a portion of the upper semiconductor chip 230. In an embodiment, a non-conductive layer may not be provided between the upper semiconductor chip 230, which is the uppermost one of the semiconductor chips 210, 220, 230, and 240, and the middle semiconductor chip 220. Therefore, any non-conductive layer may not be provided on the upper semiconductor chip 230 or cover the upper semiconductor chip 230. This can reduce failures in the process of manufacturing the semiconductor package.

Referring back to fig. 4, a mold layer 500 may be formed on the base semiconductor chip 100. The mold layer 500 may be disposed on the chip stack CS. In an embodiment, the mold layer 500 may cover the chip stack CS. The mold layer 500 on the base semiconductor chip 100 may be provided to encapsulate the lower semiconductor chip 210, the additional semiconductor chip 240, the intermediate semiconductor chip 220, the upper semiconductor chip 230, and the non-conductive layers 410, 420, and 430. In an embodiment, the mold layer 500 may be formed by forming an insulating member on the base semiconductor chip 100 and on the chip stack CS (e.g., using a coating process) and curing the insulating member. In an embodiment, the mold layer 500 may cover the chip stack CS. After the mold layer 500 is formed, if necessary, a planarization process may be performed on the mold layer 500 to expose the top surface of the upper semiconductor chip 230.

The external terminal 160 may be provided on the bottom surface of the base semiconductor chip 100.

Fig. 18, 19 and 20 are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an embodiment.

Referring to fig. 18, a sub-semiconductor chip 250 may be provided. The sub-semiconductor chip 250 may be provided to have substantially the same or similar features as the sub-semiconductor chip 250 described with reference to fig. 5. For example, the sub-semiconductor chip 250 may include a sixth circuit layer 251 provided on a surface of the sub-semiconductor chip 250, a sixth protective layer 254 opposite to the sixth circuit layer 251, a sixth via 252 provided to penetrate the sub-semiconductor chip 250 in a direction from the sixth protective layer 254 toward the sixth circuit layer 251, a sixth rear pad 253 provided in the sixth protective layer 254, and a sixth front pad 255 provided in the sixth circuit layer 251. The sixth circuit layer 251 may be provided on an active surface of the sub-semiconductor chip 250, and hereinafter, a surface opposite to the active surface will be referred to as a passive surface of the sub-semiconductor chip 250.

The sub-semiconductor chips 250 may be bonded to each other. The sub-semiconductor chips 250 may be bonded to each other in a chip-to-chip manner. Each sub-semiconductor chip 250 may be stacked on top of another. For example, one of the sub-semiconductor chips 250 may be provided such that its active surface faces the passive surface of the other sub-semiconductor chip 250. The sub-semiconductor chips 250 may be stacked such that the sixth rear pads 253 and the sixth front pads 255 thereof are vertically aligned with each other.

A heat treatment process may be performed on the sub-semiconductor chip 250. The sixth rear pad 253 and the sixth front pad 255 may be bonded to each other through a heat treatment process. For example, the sixth rear pad 253 and the sixth front pad 255 may be bonded or coupled to each other to form a single structure or layer. The bonding of the sixth rear pad 253 and the sixth front pad 255 may be achieved in a natural manner. In detail, the sixth rear pad 253 and the sixth front pad 255 may be formed of the same material, for example, copper (Cu), in which case the sixth rear pad 253 and the sixth front pad 255 may be bonded to each other through a surface activation phenomenon at an interface between the sixth rear pad 253 and the sixth front pad 255 that are in contact with each other and a subsequent metal-to-metal hybrid bonding process. In one embodiment, each chip structure UCS may be formed by the aforementioned process.

The above description relates to an example in which one of the sub-semiconductor chips 250 is bonded to another of the sub-semiconductor chips 250 or the sub-semiconductor chips 250 are bonded to each other in a chip-to-chip shape, but the embodiment is not limited to this example. In one embodiment, the sub-semiconductor chips 250 may be bonded to each other in a wafer-to-wafer shape. For example, semiconductor wafers having the sub-semiconductor chips 250 may be bonded to each other, and then a dicing process may be performed to separate the sub-semiconductor chips 250 from each other.

A fourth chip connection terminal 257 and a fourth non-conductive layer 440 surrounding the same may be provided on a bottom surface (i.e., an active surface) of the chip structure UCS. For example, the fourth chip connection terminal 257 may be provided on the sixth front pad 255 of the sub-semiconductor chip 250 of the chip structure UCS. The fourth non-conductive layer 440 may be a non-conductive film (NCF) or a non-conductive paste (NCP).

Referring to fig. 19, a chip structure UCS may be provided on the lower semiconductor chip 210 in the structure of fig. 10. A thermocompression bonding process may be performed to bond the chip structure UCS to the lower semiconductor chip 210. The fourth chip connection terminal 257 may electrically connect the lower semiconductor chip 210 to the chip structure UCS. In the case where the chip structure UCS is pressed toward the lower semiconductor chip 210, the fourth non-conductive layer 440 may protrude in an outward direction from a side surface of the lower semiconductor chip 210.

Referring to fig. 20, an intermediate semiconductor chip 220 and an upper semiconductor chip 230 may be provided, as described with reference to fig. 2, in which case the upper semiconductor chip 230 may be bonded to the intermediate semiconductor chip 220.

The intermediate semiconductor chip 220 may be mounted on the chip structure UCS. The process of mounting the intermediate semiconductor chip 220 may be substantially the same as or similar to the process of mounting the intermediate semiconductor chip 220 on the additional semiconductor chip 240 described with reference to fig. 17.

Referring back to fig. 5, a mold layer 500 may be formed on the base semiconductor chip 100. The mold layer 500 may be formed on the chip stack CS. In an embodiment, the mold layer 500 may cover the chip stack CS. The external terminal 160 may be provided on the bottom surface of the base semiconductor chip 100.

In the semiconductor package according to an embodiment, it is possible to prevent a malfunction that may be caused by the non-conductive layer between the lower semiconductor chip and the base semiconductor chip and between the upper semiconductor chip and the intermediate semiconductor chip, thereby realizing a semiconductor package having improved structural stability. Further, the warpage problem in the chip stack can be reduced, thereby preventing the occurrence of separation problem between the semiconductor chips bonded to each other in the hybrid bonding manner. Further, the number of hybrid bonding structures provided between the semiconductor chips in the chip stack can be reduced, so that the bonding process can be easily performed on the semiconductor chips in the chip stack.

While aspects of the example embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

The present application claims priority from korean patent application No. 10-2022-0107717 filed at korean intellectual property office on month 8 and 26 of 2022, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor package, comprising:

a substrate including a plurality of vias;

a chip stack on the substrate; and

a mold layer on the substrate and on at least a portion of the chip stack,

wherein the chip stack comprises:

a first semiconductor chip;

a second semiconductor chip stacked on the first semiconductor chip;

a third semiconductor chip on an uppermost one of the second semiconductor chips; and

a non-conductive layer between the first semiconductor chip and the second semiconductor chip, wherein a first die pad of the first semiconductor chip is bonded to a substrate pad of the substrate, wherein each of the first die pad and the substrate pad comprises the same metallic material and forms a first single structure or layer,

wherein the uppermost one of the second semiconductor chips is bonded to a third chip pad of the third semiconductor chip,

Wherein each of the second and third chip pads comprises the same metallic material and forms a second individual structure or layer, an

Wherein each of the second semiconductor chips is electrically connected to the other of the second semiconductor chips or the first semiconductor chip using a connection terminal on a bottom surface of each of the second semiconductor chips.

2. The semiconductor package according to claim 1, wherein the non-conductive layer is disposed around the connection terminals between the first semiconductor chip and the second semiconductor chip.

3. The semiconductor package of claim 1, wherein the non-conductive layer protrudes to an area on a side surface of the chip stack, and

the non-conductive layer is spaced apart from the substrate and the third semiconductor chip.

4. The semiconductor package according to claim 1, wherein a bottom surface of the first semiconductor chip is in direct contact with a top surface of the substrate, and

wherein a bottom surface of the third semiconductor chip is in direct contact with a top surface of the uppermost one of the second semiconductor chips.

5. The semiconductor package of claim 1, wherein the connection terminals comprise at least one of solder balls and solder bumps on the bottom surface of the second semiconductor chip.

6. The semiconductor package according to claim 1, further comprising a fourth semiconductor chip between the first semiconductor chip and the third semiconductor chip,

wherein each of the fourth semiconductor chips is provided on a top surface of a corresponding one of the second semiconductor chips,

wherein one of the second semiconductor chips and one of the fourth semiconductor chips thereon constitute a single chip structure, and

wherein the second semiconductor chip and the fourth semiconductor chip constituting each of the chip structures are in contact with each other.

7. The semiconductor package of claim 6, wherein in the chip configuration, the second semiconductor chip has an active surface facing the substrate and the fourth semiconductor chip has an active surface facing the substrate.

8. The semiconductor package of claim 6, wherein in the chip configuration, the second semiconductor chip has an active surface facing the third semiconductor chip and the fourth semiconductor chip has an active surface facing the substrate.

9. The semiconductor package of claim 6, wherein each of the chip structures is electrically connected to another of the chip structures using the connection terminals on the bottom surface of the second semiconductor chip.

10. The semiconductor package of claim 1, wherein a width of the non-conductive layer increases with decreasing distance from the substrate.

11. A semiconductor package, comprising:

a semiconductor substrate;

a chip stack on the semiconductor substrate; and

a mold layer on the semiconductor substrate and the chip stack,

wherein the chip stack comprises:

a first semiconductor chip on the semiconductor substrate;

a chip structure stacked on the first semiconductor chip; and

a non-conductive layer between the first semiconductor chip and a lowermost one of the chip structures and between adjacent ones of the chip structures,

wherein each of the chip structures comprises:

a second semiconductor chip;

a third semiconductor chip on the second semiconductor chip; and

a first connection terminal on a bottom surface of the second semiconductor chip,

the bottom surface of the first semiconductor chip is in direct contact with the top surface of the semiconductor substrate,

wherein, in the chip structure, the bottom surface of the third semiconductor chip is in direct contact with the top surface of the second semiconductor chip,

wherein the non-conductive layer is provided around the first connection terminal between the first semiconductor chip and the lowermost one of the chip structures and between adjacent chip structures, and

Wherein the non-conductive layer is spaced apart from the semiconductor substrate.

12. The semiconductor package of claim 11, wherein the non-conductive layer is spaced apart from the third semiconductor chip in an uppermost one of the chip structures.

13. The semiconductor package of claim 11, wherein a first die pad of the first semiconductor die is bonded to a substrate pad of the substrate, and

each of the first chip pad and the substrate pad includes the same metal material and forms a single structure or layer.

14. The semiconductor package of claim 11, wherein in the chip configuration, a second chip pad of the second semiconductor chip is bonded to a third chip pad of the third semiconductor chip, each of the second and third chip pads comprising the same metallic material and forming a single structure or layer.

15. The semiconductor package of claim 11, wherein the non-conductive layer protrudes to an area on a side surface of the chip stack, and

the width of the non-conductive layer increases with decreasing distance from the substrate.

16. The semiconductor package of claim 11, wherein the first connection terminal comprises at least one of a solder ball and a solder bump on the bottom surface of the second semiconductor chip.

17. The semiconductor package of claim 11, wherein in each of the chip structures, an active surface of the second semiconductor chip and an active surface of the third semiconductor chip face the substrate, the active surface of the third semiconductor chip contacting a passive surface of the second semiconductor chip.

18. The semiconductor package of claim 11, wherein in each of the chip structures, an active surface of the second semiconductor chip and an active surface of the third semiconductor chip face each other, the active surface of the third semiconductor chip and the active surface of the second semiconductor chip being in contact with each other.

19. The semiconductor package of claim 11, wherein each of the chip structures further comprises a fourth semiconductor chip on the third semiconductor chip, and

wherein, in the chip structure, a bottom surface of the fourth semiconductor chip is in direct contact with a top surface of the third semiconductor chip.

20. A semiconductor package, comprising:

a semiconductor substrate including a substrate pad;

a first semiconductor chip on the semiconductor substrate, the first semiconductor chip including a first chip pad bonded to the substrate pad of the semiconductor substrate, each of the first chip pad and the substrate pad including the same metal material and forming a single structure or layer;

A second semiconductor chip on the first semiconductor chip and electrically connected to the first semiconductor chip using a connection terminal provided on a bottom surface of the second semiconductor chip;

a non-conductive layer on the bottom surface of the second semiconductor chip and around the connection terminals;

a third semiconductor chip on the second semiconductor chip, the second and third semiconductor chips including a second chip pad and a third chip pad, respectively, wherein each of the second and third chip pads includes the same metal material and is bonded to each other and forms a single structure or layer; and

a mold layer on the semiconductor substrate and the first to third semiconductor chips,

wherein the non-conductive layer is spaced apart from the semiconductor substrate and the third semiconductor chip.