CN117637448A - Side wall manufacturing method and device, chip and electronic equipment - Google Patents
Side wall manufacturing method and device, chip and electronic equipment Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 78
- 239000000463 material Substances 0.000 claims abstract description 299
- 238000002161 passivation Methods 0.000 claims abstract description 45
- 238000002834 transmittance Methods 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 8
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 61
- 238000000034 method Methods 0.000 claims description 32
- 239000011787 zinc oxide Substances 0.000 claims description 30
- 238000002360 preparation method Methods 0.000 claims description 26
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 14
- 229910052733 gallium Inorganic materials 0.000 claims description 14
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
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- 239000010410 layer Substances 0.000 description 153
- 230000006870 function Effects 0.000 description 31
- 238000010586 diagram Methods 0.000 description 20
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 14
- 239000010453 quartz Substances 0.000 description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 239000011651 chromium Substances 0.000 description 11
- 229910052804 chromium Inorganic materials 0.000 description 10
- WGLPBDUCMAPZCE-UHFFFAOYSA-N Trioxochromium Chemical compound O=[Cr](=O)=O WGLPBDUCMAPZCE-UHFFFAOYSA-N 0.000 description 9
- 229910000423 chromium oxide Inorganic materials 0.000 description 9
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- 238000005516 engineering process Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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Abstract
The invention provides a side wall manufacturing method, a side wall manufacturing device, a chip and electronic equipment, wherein the side wall manufacturing method comprises the following steps: adding at least one intermediate material with lower light transmittance than the second layer material between the opaque first layer material and the light-transmitting second layer material of the photomask of the passivation protection layer; according to the functional requirement of the chip, the first length of the first layer of material and the second length of the intermediate material are adjusted, a plurality of light cover structures are obtained through combination, and the plurality of light cover structures are arranged to obtain a target light cover structure; using the target photomask structure to photoetching and manufacture a passivation layer of the semiconductor chip, and respectively etching and photoresist removing the semiconductor chip to obtain various side wall shapes of the passivation layer of the chip; the invention can simplify the manufacturing process of the chip passivation layer side wall, reduce the manufacturing cost of the side wall morphology and improve the chip production efficiency.
Description
Technical Field
The present invention relates to the field of chip sidewall manufacturing technologies, and in particular, to a sidewall manufacturing method and apparatus, a chip, and an electronic device.
Background
The last Process (Process) of manufacturing the chip in a FAB (manufacturing integrated circuit) factory is to cover a Passivation protection layer (passage), and then open the place where pins (Pin pins) are needed by etching to form a chip Pin (PAD), so as to bond (bond) on the PAD to connect the Pin pins with circuits inside the chip. With the development of the semiconductor industry, the variety of chips is more and more, and the chip manufacturing industry is more and more challenged, and the traditional process and method are difficult to expect. The PAD mentioned above has not been used for bonding only, such as filling the PAD with other characteristic materials (photoelectric materials/or piezoelectric materials), such as implementing a Chip (Chip) and interconnecting the Chip through the PAD, and the like, and the functions to be achieved have been increasing. When PAD requirements of multiple functions exist on one chip, the same sidewall Profile (Profile) is still not used to meet the process requirements.
In the prior art, a vertical PAD side wall morphology is adopted to fill photoelectric material/or piezoelectric material, or a PAD side wall morphology with a non-vertical included angle with a horizontal plane is adopted to connect a plurality of chips, or a step-type PAD side wall morphology is adopted to make pin bonding. However, in the prior art, PAD sidewall morphology in the prior art is to be achieved, multiple photomasks are required to be respectively performed on each PAD with different functions, and then different sidewall morphologies are formed by using different processes. The number of layers of the photomask and the number of steps of the process are increased, so that the cost is increased.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a side wall manufacturing method, a side wall manufacturing device, a chip and electronic equipment, which can simplify the manufacturing process of the chip side wall, reduce the manufacturing cost of the side wall morphology and improve the chip production efficiency.
In a first aspect, the present invention provides a method for manufacturing a sidewall, including:
adding at least one intermediate material with lower light transmittance than the second layer material between the opaque first layer material and the light-transmitting second layer material of the photomask of the passivation protection layer;
according to the functional requirement of the chip, the first length of the first layer of material and the second length of the intermediate material are adjusted, a plurality of light cover structures are obtained through combination, and the plurality of light cover structures are arranged to obtain a target light cover structure;
and photoetching the target photomask structure to manufacture a passivation layer of the semiconductor chip, and respectively etching and photoresist removing the semiconductor chip to obtain various side wall shapes of the passivation layer of the chip.
According to the invention, the intermediate material with lower light transmittance than that of the second layer material is added in the passivation protection layer, so that the light intensity on a semiconductor chip can be conveniently changed by changing the light transmittance of the target photomask structure, the length of the intermediate material and the length of the first layer material can be adjusted according to the functional requirement of the chip, the target photomask structure meeting various PAD functions can be prepared, etching and photoresist removal can be carried out based on the target photomask structure, and various chip passivation layer side wall morphology prepared by one multifunctional target photomask structure can be obtained, so that the steps of a preparation process for respectively using the number of layers and the sum of different photomasks for preparing different PAD side wall morphology are simplified, the chip production efficiency is further improved, and the cost for preparing the side wall morphology is reduced.
With reference to the first aspect, in one possible implementation manner, the adjusting the first length of the first layer of material and the second length of the intermediate material according to the chip function requirement combines to obtain a plurality of light cover structures, including:
according to the functional requirement of the chip, regulating the first distance between the first end of the first layer of material and the first end of the first intermediate material and the second distance between the first end of the first layer of material and the first end of the second intermediate material, and combining to obtain various light cover structures according to the first distance and the second distance; wherein the intermediate material is a two-layer material obtained by placing a first intermediate material on a second intermediate material.
According to the invention, the first distance between the first end of the first layer of material and the first end of the first intermediate material and the second distance between the first end of the first layer of material and the first end of the second intermediate material are adopted to obtain the multi-layer multi-functional target photomask structure, so that the light intensity of the wafer on the chip is changed differently after exposure, the PAD side wall morphology with different functions is prepared, the steps of the preparation process for preparing different PAD side wall morphology by using the number of layers of different photomasks respectively are simplified, the chip production efficiency is improved, and the cost for preparing the side wall morphology is reduced.
With reference to the first aspect, in one possible implementation manner, the adjusting, according to a chip function requirement, a first distance between a first end of the first layer of material and a first end of the first intermediate material, and a second distance between the first end of the first layer of material and a first end of the second intermediate material, and combining according to the first distance and the second distance, to obtain multiple light cover structures includes:
and according to the requirement of connection between the chips, or the requirement of pin bonding of the chips, or the requirement of filling piezoelectric materials or photoelectric materials on the chip PAD, adjusting the first distance to be larger than or equal to the second distance, wherein the first distance is larger than or equal to a first distance threshold value, and combining to obtain various light cover structures.
According to the invention, the first distance and the second distance are adjusted according to whether the chip needs to be connected with other chips, whether pin bonding is performed or whether filling pressure or photoelectric materials are needed, so that various light cover structures with different functions are prepared, and the PAD side wall morphology with different functions is conveniently obtained according to the light cover structures obtained after the various light cover structures are arranged.
With reference to the first aspect, in one possible implementation manner, the adjusting the first distance to be greater than or equal to the second distance and the first distance to be greater than or equal to a first distance threshold according to whether the chips need to be connected, or whether the chips need to be bonded by pins, or whether the chip PAD needs to be filled with piezoelectric material or photoelectric material, and combining to obtain multiple light cover structures includes:
When the chip PAD is required to be filled with piezoelectric materials or photoelectric materials, the first distance is adjusted to be equal to the second distance, and the first distance is adjusted to be equal to the first distance threshold value, so that a first light cover structure is obtained;
when the chips are required to be connected, the first distance is adjusted to be larger than a first distance threshold value, and the second distance is adjusted to be larger than the first distance, so that a second light cover structure is obtained;
when the chip is required to be subjected to pin bonding, the first distance is adjusted to be larger than a first distance threshold value, and the second distance is equal to the first distance, so that a third light cover structure is obtained;
and combining the first light cover structure, the second light cover structure and the third light cover structure to obtain the multiple light cover structures.
With reference to the first aspect, in one possible implementation manner, the intermediate material includes: a first material that is doped with aluminum or gallium, or a second material that is undoped.
With reference to the first aspect, in a possible implementation manner, the first material doped with aluminum or gallium, or the second material undoped, includes:
the first material comprises: aluminum-doped zinc oxide or gallium-doped zinc oxide;
The second material comprises: zinc oxide.
With reference to the first aspect, in one possible implementation manner, the interval of light transmittance of the intermediate material is [40%,50% ].
In a second aspect, the present invention provides a sidewall manufacturing apparatus, including: the device comprises an intermediate material preparation unit, a photomask structure preparation unit and a chip side wall morphology preparation unit; wherein,
the intermediate material preparation unit is used for adding at least one layer of intermediate material with lower light transmittance than the second layer of material between the opaque first layer of material and the light-transmitting second layer of material of the photomask of the passivation protection layer;
the photomask structure preparation unit is used for adjusting the first length of the first layer of material and the second length of the intermediate material according to the functional requirement of the chip, combining the first length of the first layer of material and the second length of the intermediate material to obtain a plurality of photomask structures, and arranging the plurality of photomask structures to obtain a target photomask structure;
the chip side wall morphology preparation unit is used for photoetching the passivation layer of the semiconductor chip by using the target photomask structure, and respectively etching and photoresist removing the semiconductor chip to obtain various chip passivation layer side wall morphologies.
In a third aspect, the present invention provides a chip comprising: various chip passivation layer side wall morphology; wherein,
The side wall morphology of the chip passivation layers at least comprises any two of a first light cover structure, a second light cover structure and a third light cover structure; the sidewall morphology of the passivation layers of the chips is obtained according to the sidewall manufacturing method of the first aspect.
According to the embodiment of the application, the corresponding chip is manufactured based on the side wall manufacturing method, and the obtained chip has more and more complex application scenes due to different side wall functions, and the method comprises the following steps: the piezoelectric material or the photoelectric material can be filled, the piezoelectric material or the photoelectric material can be connected with other chips, and the pin bonding function can be realized, so that the piezoelectric material or the photoelectric material has higher applicability and practicability; in addition, the chip obtained by the side wall morphology of the passivation layer of the various chips prepared by the multifunctional target photomask structure simplifies the steps of the manufacturing process for manufacturing different PAD side wall morphology by using the layer numbers of different photomasks respectively, thereby improving the production efficiency of the chip and reducing the manufacturing cost of the chip.
In a fourth aspect, the present invention provides an electronic device, including a circuit board and a chip obtained based on the sidewall morphology according to the first aspect; the chip is arranged on the circuit board and is electrically connected with the circuit board.
According to the embodiment of the application, the chip which is prepared based on the side wall manufacturing method and corresponds to the side wall manufacturing method is applied to specific electronic equipment, and the chip can be applied to the specific products to meet the requirements of different products, so that the application has higher applicability and practicability.
Drawings
Fig. 1 is a schematic diagram of PAD sidewall morphology provided in an embodiment of the present application;
FIG. 2 is a schematic diagram of obtaining PAD sidewall morphology by the prior art provided in the embodiments of the present application;
fig. 3 is a schematic flow chart of a method for manufacturing a side wall according to an embodiment of the present application;
FIG. 4 is a schematic view of a division of a first distance and a second distance on a light cover structure according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of the embodiment of the present invention for preparing different light cover structures according to different values of the first distance and the second distance;
FIG. 6 is a schematic illustration of the change in light intensity after exposure through a photomask structure in accordance with the prior art provided by the embodiments of the present application;
FIG. 7 is a schematic diagram of the variation of the light intensity after exposure of the target mask structure according to the embodiment of the present application;
FIG. 8 is a schematic diagram of a PAD sidewall morphology obtained by the sidewall manufacturing method according to the embodiment of the present application;
fig. 9 is a schematic structural diagram of a sidewall manufacturing apparatus according to an embodiment of the present disclosure.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It is worth to say that, different PAD side wall morphology is designed to meet different functional requirements of the same chip, PAD is a circuit leading-out device, also called a pin or a pin, is packaged inside the chip, see fig. 1, is a schematic diagram of PAD side wall morphology provided by the embodiment of the present application, and includes three PAD side wall morphology: right angle sidewall topography 11, outwardly sloped sidewall topography 12, and stepped sidewall topography 13. In the figure, the first PAD side wall morphology is used for filling piezoelectric or photoelectric materials, and the required PAD side wall morphology is relatively straight in angle; the second PAD side wall morphology is used for depositing Metal (Metal) to connect a plurality of chips, and the required angle cannot be too straight and needs to form a certain included angle with the horizontal plane; the third PAD sidewall morphology is to better bond the leads, so it is needed to make a step sidewall morphology.
It should be noted that, conventionally, a chip only needs to have a PAD, which is a PAD bond, for connecting a circuit and a pin in the chip. And PADs for signal induction exist for the sensor chip, piezoelectric materials or photoelectric materials are required to be filled in the PADs to realize signal conversion, and the side wall morphology of the PADs is different from that of conventional PADs in terms of process requirements. At present, a plurality of methods for packaging chips are adopted, and when different PADs on one chip need different packaging modes, the side walls of the required PADs are also different.
When different PAD side wall shapes are realized to meet different functional requirements of a chip, a Mask (Mask) needs to be separated from each PAD side wall shape, one Mask needs to be separated from each PAD for realizing the three different functions, and then different side wall shapes are formed by using different processes, however, the number of layers of the masks and the number of steps of the process are increased by adopting the method, so that the cost is increased.
Referring to fig. 2, a schematic diagram of obtaining PAD sidewall morphology by using the existing process provided in the embodiment of the present application is shown. The mask of passivation layer is typically Binary mask (Binary mask) with opaque chromium (Cr) and/or chromium oxide (CrO) 2 ) And Quartz (Quartz) having a light transmittance of more than 85%. In the drawing, in fig. 2, the passivation protection layer includes: structure 1 and structure 4, structure 1 is the first layer material, the first layer material is chromium and/or chromium oxide layer with light transmittance of 0%, structure 4 is the second layer material, the second layer material is quartz with light transmittance of 85%, structure 1 is placed above structure 4, and there is interval between a plurality of chromium and/or chromium oxide layers, through the photomask formed by chromium and/or chromium oxide layer and quartz layer, when light shines on the Wafer (Wafer) through the photomask, because the light transmittance of chromium and/or chromium oxide layer and quartz layer is different, the part under the protection of chromium and/or chromium oxide layer is not exposed, and the part under the protection of high light transmittance quartz layer is exposed more, both ends of chromium and/or chromium oxide layer are perpendicular to horizontal plane in the figure, therefore, after exposing, imaging (After develop inspection, ADI) and imaging after etching and photoresist removing (After ETCH inspection, AEI), the obtained is used for filling the side wall of the first Wafer or the side wall graph of the change of the present technology profile of the piezoelectric profile of the Wafer 2; at present The developed image after exposure to light is processed as structure 6 and the etched and photoresist removed is processed as structure 7.
Fig. 2 is a graph showing the preparation of the same PAD sidewall morphology, and when the PAD sidewall morphology with two other functions needs to be prepared, a photomask needs to be manufactured again to obtain the PAD sidewall morphology with multiple functions. The invention aims to solve the defects of the prior art and provides a side wall manufacturing method, a side wall manufacturing device, a chip and electronic equipment. In order to more clearly illustrate the technical aspects of the present invention, the following examples will be described in detail.
It is worth noting that the embodiments of the present invention may be combined with each other without conflict.
Example 1
Referring to fig. 3, a flow chart of a method for manufacturing a side wall according to an embodiment of the present application includes: steps S11 to S13 include:
step S11, adding at least one intermediate material with lower light transmittance than the second layer material between the opaque first layer material and the light-transmitting second layer material of the photomask of the passivation protection layer.
In one embodiment of the present application, the intermediate material comprises: a first material that is doped with aluminum or gallium, or a second material that is undoped.
In one embodiment of the present application, the aluminum-or gallium-containing doped first material, or undoped second material, comprises: the first material comprises: aluminum-doped zinc oxide or gallium-doped zinc oxide; the second material comprises: zinc oxide.
It is worth noting that the first material is a first layer material composed of doped zinc oxide, and the second material is a first layer material composed of complementary doped zinc oxide; a plurality of first layer materials are spaced apart from and overlying the second layer material.
In one embodiment of the present application, the interval of light transmittance of the intermediate material is [40%,50% ].
In one embodiment of the present application, the second layer of material is a material composed of quartz having a light transmittance of 85%.
In one embodiment of the present application, the first layer material is a material composed of chromium element, the second layer material is a material composed of quartz, the intermediate material is a layer of material composed of any one of aluminum doped zinc oxide (AZO), gallium doped zinc oxide (GZO) or zinc oxide (ZnO), and the light transmittance of the intermediate material is [40%,50% ].
In one embodiment of the present application, the first layer of material is a material consisting of elemental chromium comprising: consists of chromium and/or chromium oxide.
In one embodiment of the present application, the first layer material is a material composed of chromium element, the second layer material is a material composed of quartz, the intermediate material is two layers of materials composed of any two of aluminum doped zinc oxide, gallium doped zinc oxide or zinc oxide, respectively, and the light transmittance of the two layers of materials is [40%,50% ].
In one embodiment of the present application, the first layer material is a material composed of chromium element, the second layer material is a material composed of quartz, the intermediate material is two layers of materials composed of any two of aluminum doped zinc oxide, gallium doped zinc oxide or zinc oxide, respectively, the light transmittance of the first intermediate material bonded to the first layer material is 40%, and the light transmittance of the second intermediate material bonded to the second layer material is 50%.
It should be noted that the first intermediate material and the second intermediate material are an upper layer material and a lower layer material of the two layers of materials, respectively; wherein the upper layer of the first intermediate material is a first layer of material, the lower layer of the first intermediate material is a second intermediate material, and the lower layer of the second intermediate material is a second layer of material.
In one embodiment of the present application, the first layer material is a material composed of chromium element, the second layer material is a material composed of quartz, the intermediate material is a three-layer material composed of three kinds of materials respectively, i.e., aluminum doped zinc oxide, gallium doped zinc oxide and zinc oxide, and the light transmittance of the three-layer material is [40%,50% ].
And step S12, according to the functional requirement of the chip, regulating the first length of the first layer material and the second length of the intermediate material, combining to obtain a plurality of light cover structures, and arranging the plurality of light cover structures to obtain the target light cover structure.
Specifically, according to the functional requirement of the chip, a first distance between the first end of the first layer of material and the first end of the first intermediate material and a second distance between the first end of the first layer of material and the first end of the second intermediate material are adjusted, and according to the first distance and the second distance, a plurality of light cover structures are obtained through combination; wherein the intermediate material is a two-layer material obtained by placing a first intermediate material on a second intermediate material.
It should be noted that the first end of the first layer of material is the end point of the first layer of material, and may be the left end point and/or the right end point; the first end of the first intermediate material is the end point of the first intermediate material, which can be the left end point and/or the right end point; the first end of the second intermediate material is the end point of the second intermediate material, which can be the left end point and/or the right end point; the first distance is the distance between the first end of the first layer of material and the first end of the first intermediate material, and the second distance is the distance between the first end of the first layer of material and the first end of the second intermediate material, wherein the first distance and the second distance are on the same side of the same light cover structure; namely: the first distance is the distance between the left end of the first layer of material and the left end of the first intermediate material on the left side of the same light cover structure, and the second distance is the distance between the left end of the first layer of material and the left end of the second intermediate material on the left side of the same light cover structure; alternatively, the first distance is the distance between the right end of the first layer of material and the right end of the first intermediate material on the right side of the same light cover structure, and the second distance is the distance between the right end of the first layer of material and the right end of the second intermediate material on the right side of the same light cover structure.
According to the method, the first distance between the first end of the first layer material and the first end of the first intermediate material is adjusted, and the second distance between the first end of the first layer material and the first end of the second intermediate material is adjusted, so that after the multi-layer multifunctional target photomask structure is obtained for exposure, the light intensity of the wafer on the chip changes differently, the PAD side wall morphology with different functions is prepared, the steps of the preparation process for respectively using the layers of different photomasks for preparing different PAD side wall morphology are simplified, the chip production efficiency is improved, and the cost for preparing the side wall morphology is reduced.
In an embodiment of the present application, according to the requirement of connection between chips, or the requirement of pin bonding of chips, or the requirement of filling piezoelectric material or photoelectric material on the chip PAD, the first distance is adjusted to be greater than or equal to the second distance, and the first distance is greater than or equal to a first distance threshold, so as to obtain multiple light cover structures by combining.
It should be noted that, according to the adjustment of the first distance and the second distance, a structure of one end of the light cover structure can be obtained, the other end of the light cover structure adopts the same manufacturing method, the one end and the other end of the light cover structure may refer to the left end and/or the right end of the light cover structure, and the one end in this embodiment may refer to the light cover structure which is the same as the left end or the light cover structure which is the same as the right end. Therefore, if 1 of the first, second, and third light cover structures that are the same as the left end is selected as the left end of the light cover structure to be combined, and 1 of the first, second, and third light cover structures that are the same as the right end is selected as the right end of the light cover structure to be combined, then one complete light cover structure can be obtained, and a plurality of light cover structures having different structures can be obtained.
In one embodiment of the present application, when the chip PAD is required to be filled with a piezoelectric material or a photoelectric material, the first distance is adjusted to be equal to the second distance, and the first distance is equal to the first distance threshold, so as to obtain a first light cover structure; when the chips are required to be connected, the first distance is adjusted to be larger than a first distance threshold value, and the second distance is adjusted to be larger than the first distance, so that a second light cover structure is obtained; when the chip is required to be subjected to pin bonding, the first distance is adjusted to be larger than a first distance threshold value, and the second distance is equal to the first distance, so that a third light cover structure is obtained; and combining the first light cover structure, the second light cover structure and the third light cover structure to obtain the multiple light cover structures.
According to the PAD side wall morphology adjusting method and device, whether the chips are connected with other chips, whether pin bonding is performed or whether filling pressure or photoelectric materials are needed is adjusted according to whether the chips are connected with the other chips, whether the pins are bonded with the other chips or not, and therefore multiple light cover structures with different functions are manufactured, the light cover structures obtained after the chips are arranged according to the multiple light cover structures are convenient to obtain the PAD side wall morphology with different functions.
In one embodiment of the present application, the first distance threshold is 0.
It is worth to say that, according to the convenience that the chip side wall was used, can arrange the combination with multiple light cover structure, obtain a target light cover structure, be convenient for obtain customized chip according to side wall appearance position, a target light cover structure contains multiple light cover structure promptly, and each kind of light cover structure can realize different functions, according to the light cover structure of different arrangements, can realize the different functions in different positions for the chip.
Referring to fig. 4, a schematic diagram of dividing a first distance from a second distance on a light cover structure is provided in an embodiment of the present application. In this embodiment, the light-transmitting material comprises two layers of intermediate materials, wherein the first layer of intermediate material is aluminum doped zinc oxide or gallium doped zinc oxide, and the light transmittance is 40%; the second layer is made of zinc oxide, and the light transmittance is 50%; the first layer of material is aluminum doped zinc oxide or gallium doped zinc oxide, and the light transmittance is 0%; the second layer is made of quartz, and the light transmittance is 85%. In the figure, the structure 1 is a first layer of material, the structure 2 is a first intermediate material, the structure 3 is a second intermediate material, the structure 4 is a second layer of material, the left side is the left end of the light cover structure, the right side is the right end of the light cover structure, and the left end and the right end are at a certain distance so as to facilitate exposure and generate a second PAD side wall morphology. The first distance between one end of the first layer of material and one end of the first intermediate material is denoted as a, and the first distance between one end of the first layer of material and one end of the second intermediate material is denoted as B; wherein the first distance and the second distance are both adjusted on the same side of the same light cover structure. Referring to fig. 5, schematic diagrams of different values of the first distance and the second distance provided in the embodiments of the present application correspond to different light cover structures. In the figure, when the distance A and the distance B adjusted on the same side of the same light cover structure are both 0 (namely a first distance threshold), a first PAD side wall morphology is obtained; when the distance A adjusted by the same side of the same light cover structure is not 0 and the distance B is larger than the distance A, obtaining a second PAD side wall morphology; when the distance A and the distance B adjusted on the same side of the same light cover structure are equal, but are not 0, a third PAD side wall morphology is obtained. In fig. 4, the values of the distance a and the distance B of the second PAD sidewall morphology prepared in fig. 5 are adopted to obtain a second PAD sidewall morphology.
According to the method, after a layer of intermediate material with the light transmittance of 40% and 50% is added, the distance between the end points of the two layers of intermediate material and the end points of the first layer of material is regulated, so that a target photomask structure is manufactured, different PAD side wall morphologies can be obtained through a target photomask structure process, the steps of manufacturing the different PAD side wall morphologies by using the number of layers of different photomasks and the manufacturing process of the different photomasks respectively are simplified, the operation efficiency is improved, the chip production efficiency and the chip yield are further improved, the side wall morphology manufacturing cost is reduced, and the energy consumption is reduced; and the parameters of the PAD side wall morphology with different functions are obtained simply, the control is convenient, and the applicability and the practicability are stronger.
And S13, photoetching the target photomask structure to manufacture a passivation layer of the semiconductor chip, and respectively etching and photoresist removing the semiconductor chip to obtain various chip passivation layer side wall morphologies.
In some embodiments, the passivation layer of the semiconductor chip is manufactured by using the target photomask structure through photoetching, and etching and photoresist removing are respectively carried out on the passivation layer to obtain various side wall morphologies.
It is worth to say that, by exposing the target photomask structure, different light intensities are formed on the surface of the wafer on the semiconductor chip, so that the PAD side wall morphology with different functions can be obtained after imaging after exposure and development and imaging after etching and photoresist removal.
According to the method, the intermediate material with the light transmittance lower than that of the second layer material is added in the passivation protection layer, the light intensity on the semiconductor chip is conveniently changed by changing the light transmittance of the target photomask structure, the length of the intermediate material and the length of the first layer material are adjusted according to the functional requirement of the chip, the target photomask structure meeting various PAD functions can be manufactured, etching and photoresist stripping are carried out on the basis of the target photomask structure, various chip passivation layer side wall morphology manufactured by the multifunctional target photomask structure can be obtained, and therefore steps of manufacturing processes for manufacturing different PAD side wall morphology by using the number of layers of different photomasks respectively are simplified, the production efficiency of the chip is improved, and the manufacturing cost of the side wall morphology is reduced.
Example 2
Referring to fig. 6, a schematic diagram of light intensity variation after exposure through a photomask structure in the prior art according to the embodiment of the present application is shown. In the figure, the prior art separates the light cover according to the functions for the light cover structure with multiple functions, and comprises 3 identical light cover structures, so that only one light cover structure can be obtained at the same time, and in the figure, only the first PAD side wall morphology is obtained due to the light intensity of the light passing through the surface of the wafer by the same light cover. Referring to fig. 7, a schematic diagram of light intensity variation after exposure of the target mask structure according to the present application is provided in an embodiment of the present application.
In fig. 7, the target mask structure includes 2 different mask structures, wherein one mask structure is structure 5, and the target mask structure is formed by structure 1, structure 2, structure 3, structure 4 and structure 5, and the light intensity change of the wafer surface after exposure is represented by a line graph in fig. 7 due to different light intensities of the masks, wherein the light transmittance of the second layer material is 85%, and the light intensity of the corresponding wafer surface is 85%; the light transmittance of the first intermediate material is 40% and the light transmittance of the second intermediate material is 50%, so that the light intensity of the surface of the wafer corresponding to the exposed light is linearly increased along with the increase of the light transmittance, the light intensity of the wafer corresponding to the first intermediate material is about 50%, and the light intensity of the wafer corresponding to the second intermediate material is about 20%. By linearly transforming the light intensity, the more complex second PAD side wall morphology can be obtained,
in fig. 7, since the distances between the first intermediate material and the second intermediate material at the right end of the second light cover structure and the left end of the third light cover structure are the same from the first layer material, the light intensity of the corresponding wafer after exposure is stepped at the ends of the first intermediate material and the second intermediate material, and the light intensity is about 20%. Therefore, according to the step-type changing light intensity, the more complex third PAD side wall morphology can be obtained.
According to the comparison of the light intensity data, compared with the prior art, the embodiment of the application adopts the intermediate material with different light transmittance added in the photomask, and a plurality of PAD side wall morphologies can be obtained according to one photomask at the same time.
According to the embodiment of the application, one or more layers of materials with light transmittance lower than that of quartz and light transmittance of 40% -50% are added between the photomask chromium layer and the quartz layer, and edge light intensity of PADs with different functions is regulated, so that different side wall shapes with different PADs are obtained. On the basis of not increasing the number of process steps and the number of photomask layers and not increasing the process cost, the requirements of different PADs of customers on different side wall shapes due to different using purposes are met.
Example 3
Referring to fig. 8, a schematic diagram of obtaining PAD sidewall morphology by using the sidewall manufacturing method according to the embodiment of the present application is shown. In the figure, can arrange after carrying out different configurations to the photomask structure, obtain a target photomask structure, shading through target photomask structure respectively, obtain wafer surface light intensity numerical distribution, structure 6 is the formation of image after exposing and developing, and structure 7 is the formation of image after sculpture and photoresist removal, and the part that the circle outlined in the figure is just the side wall appearance, can obtain 4 3 kinds of side wall appearances respectively, from left to right includes: 2 first PAD sidewall features, 1 second PAD sidewall feature and 1 third PAD sidewall feature.
The 4 side wall morphologies obtained at the same time are respectively used as four sides of the chip to execute corresponding functions, including: the 2 first PAD side wall shapes are used for filling piezoelectric or photoelectric materials, the 1 second PAD side wall shape is used for depositing metal, connection with another chip is facilitated, and the 1 third PAD side wall shape is used for more standard pin bonding.
According to the embodiment of the application, 3 PAD side wall morphologies can be obtained through one target photomask structure process, so that the steps of manufacturing processes for manufacturing different PAD side wall morphologies by using the number of layers of different photomasks respectively are simplified, the operation efficiency is improved, the production efficiency and the yield of a chip are further improved, the manufacturing cost of the side wall morphology is reduced, and the energy consumption is reduced; and the parameters of the PAD side wall morphology with different functions are obtained simply, the control is convenient, and the applicability and the practicability are stronger.
Example 4
Referring to fig. 9, a schematic structural diagram of a sidewall manufacturing apparatus according to an embodiment of the present application includes: an intermediate material preparation unit 41, a photomask structure preparation unit 42 and a chip side wall morphology preparation unit 43.
It should be noted that, the intermediate material preparation unit 41 is mainly configured to dispose an intermediate material in the middle of the protective layer, and transmit the passivation protective layer after disposing the intermediate material to the photomask structure preparation unit 42; after receiving the passivation layer after the intermediate material is configured, the photomask structure preparing unit 42 adjusts the length of the intermediate material according to the functional requirement of the chip, and transmits the obtained photomask structure to the chip side wall morphology preparing unit 43 for preparing the side wall morphology.
An intermediate material preparation unit 41 for adding at least one intermediate material having a lower light transmittance than the second layer material between the opaque first layer material and the light transmissive second layer material of the mask of the passivation protection layer.
In one embodiment of the present application, the intermediate material comprises: a first material that is doped with aluminum or gallium, or a second material that is undoped.
In one embodiment of the present application, the aluminum-or gallium-containing doped first material, or undoped second material, comprises: the first material comprises: aluminum-doped zinc oxide or gallium-doped zinc oxide; the second material comprises: zinc oxide.
In one embodiment of the present application, the interval of light transmittance of the intermediate material is [40%,50% ].
The photomask structure preparing unit 42 is configured to adjust the first length of the first layer material and the second length of the intermediate material according to the functional requirement of the chip, combine to obtain a plurality of photomask structures, and arrange the plurality of photomask structures to obtain the target photomask structure.
Specifically, according to the functional requirement of the chip, a first distance between the first end of the first layer of material and the first end of the first intermediate material and a second distance between the first end of the first layer of material and the first end of the second intermediate material are adjusted, and according to the first distance and the second distance, a plurality of light cover structures are obtained through combination; wherein the intermediate material is a two-layer material obtained by placing a first intermediate material on a second intermediate material.
In an embodiment of the present application, according to the requirement of connection between chips, or the requirement of pin bonding of chips, or the requirement of filling piezoelectric material or photoelectric material on the chip PAD, the first distance is adjusted to be greater than or equal to the second distance, and the first distance is greater than or equal to a first distance threshold, so as to obtain multiple light cover structures by combining.
In one embodiment of the present application, when the chip PAD is required to be filled with a piezoelectric material or a photoelectric material, the first distance is adjusted to be equal to the second distance, and the first distance is equal to the first distance threshold, so as to obtain a first light cover structure; when the chips are required to be connected, the first distance is adjusted to be larger than a first distance threshold value, and the second distance is adjusted to be larger than the first distance, so that a second light cover structure is obtained; when the chip is required to be subjected to pin bonding, the first distance is adjusted to be larger than a first distance threshold value, and the second distance is equal to the first distance, so that a third light cover structure is obtained; and combining the first light cover structure, the second light cover structure and the third light cover structure to obtain the multiple light cover structures.
And the chip side wall morphology preparation unit 43 is used for photoetching the target photomask structure to prepare a passivation layer of the semiconductor chip, and respectively etching and photoresist removing the semiconductor chip to obtain various chip passivation layer side wall morphologies.
According to the embodiment of the application, the intermediate material preparation unit 41 is adopted to add the intermediate material with the light transmittance lower than that of the second layer material in the passivation protection layer, so that the light intensity on a semiconductor chip can be conveniently changed by changing the light transmittance of the target photomask structure, the photomask structure preparation unit 42 can conveniently obtain the target photomask structure, the length of the intermediate material and the length of the first layer material can be adjusted according to the functional requirement of the chip, the target photomask structure meeting multiple PAD functions can be prepared, and the chip side wall morphology preparation unit 43 performs etching and photoresist removal based on the target photomask structure, so that the number of layers and the manufacturing process steps for manufacturing different PAD side wall morphologies by using different photomasks respectively can be simplified, the chip production efficiency can be improved, and the side wall morphology manufacturing cost can be reduced.
Example 5
The chip provided by the embodiment of the application has the side wall morphology of the passivation layer of various chips; the side wall morphology of the chip passivation layer at least comprises any two of a first light cover structure, a second light cover structure and a third light cover structure; the sidewall morphology of the passivation layers of the various chips was obtained according to the sidewall manufacturing method described in example 1.
According to the embodiment of the application, the corresponding chip is manufactured based on the side wall manufacturing method, and the obtained chip has more and more complex application scenes due to different side wall functions, and the method comprises the following steps: the piezoelectric material or the photoelectric material can be filled, the piezoelectric material or the photoelectric material can be connected with other chips, and the pin bonding function can be realized, so that the piezoelectric material or the photoelectric material has higher applicability and practicability; in addition, the chip obtained by the side wall morphology of the passivation layer of the various chips prepared by the multifunctional target photomask structure simplifies the steps of the manufacturing process for manufacturing different PAD side wall morphology by using the layer numbers of different photomasks respectively, thereby improving the production efficiency of the chip and reducing the manufacturing cost of the chip.
Example 6
The electronic equipment provided by the embodiment of the application comprises a circuit board and a chip obtained based on the side wall morphology as described in the embodiment 1; the chip is arranged on the circuit board and is electrically connected with the circuit board.
The electronic device includes a printed circuit board (Printedcircuit board, PCB; may also be referred to as a circuit board) and a chip disposed on the PCB and electrically connected to the PCB.
The embodiment of the application does not particularly limit the specific form of the electronic device. The electronic device may be an electronic product such as a mobile phone, a tablet computer, a notebook computer, a vehicle-mounted computer, a smart watch, a Virtual Reality (VR) product, or a smart bracelet, for example.
According to the embodiment of the application, the chip which is prepared based on the side wall manufacturing method and corresponds to the side wall manufacturing method is applied to specific electronic equipment, and the chip can be applied to the specific products to meet the requirements of different products, so that the application has higher applicability and practicability.
It will be appreciated by those skilled in the art that embodiments of the present application may also provide a computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
Claims (10)
1. The side wall manufacturing method is characterized by comprising the following steps of:
adding at least one intermediate material with lower light transmittance than the second layer material between the opaque first layer material and the light-transmitting second layer material of the photomask of the passivation protection layer;
according to the functional requirement of the chip, the first length of the first layer of material and the second length of the intermediate material are adjusted, a plurality of light cover structures are obtained through combination, and the plurality of light cover structures are arranged to obtain a target light cover structure;
and photoetching the target photomask structure to manufacture a passivation layer of the semiconductor chip, and respectively etching and photoresist removing the semiconductor chip to obtain various side wall shapes of the passivation layer of the chip.
2. The method for manufacturing a side wall according to claim 1, wherein the adjusting the first length of the first layer of material and the second length of the intermediate material according to the functional requirement of the chip, combining to obtain a plurality of light cover structures, comprises:
according to the functional requirement of the chip, regulating the first distance between the first end of the first layer of material and the first end of the first intermediate material and the second distance between the first end of the first layer of material and the first end of the second intermediate material, and combining to obtain various light cover structures according to the first distance and the second distance; wherein the intermediate material is a two-layer material obtained by placing a first intermediate material on a second intermediate material.
3. The method for manufacturing a sidewall according to claim 2, wherein said adjusting the first distance between the first end of the first layer of material and the first end of the first intermediate material and the second distance between the first end of the first layer of material and the first end of the second intermediate material according to the functional requirement of the chip, and combining to obtain a plurality of light cover structures according to the first distance and the second distance, comprises:
and according to the requirement of connection between the chips, or the requirement of pin bonding of the chips, or the requirement of filling piezoelectric materials or photoelectric materials on the chip PAD, adjusting the first distance to be larger than or equal to the second distance, wherein the first distance is larger than or equal to a first distance threshold value, and combining to obtain various light cover structures.
4. The method for manufacturing a sidewall as set forth in claim 3, wherein the adjusting the first distance to be greater than or equal to the second distance and the first distance to be greater than or equal to a first distance threshold according to the connection between chips, or the bonding of pins on the chips, or the filling of piezoelectric material or photoelectric material on the PAD of the chip, comprises:
when the chip PAD is required to be filled with piezoelectric materials or photoelectric materials, the first distance is adjusted to be equal to the second distance, and the first distance is adjusted to be equal to the first distance threshold value, so that a first light cover structure is obtained;
When the chips are required to be connected, the first distance is adjusted to be larger than a first distance threshold value, and the second distance is adjusted to be larger than the first distance, so that a second light cover structure is obtained;
when the chip is required to be subjected to pin bonding, the first distance is adjusted to be larger than a first distance threshold value, and the second distance is equal to the first distance, so that a third light cover structure is obtained;
and combining the first light cover structure, the second light cover structure and the third light cover structure to obtain the multiple light cover structures.
5. The sidewall manufacturing method of claim 1, wherein said intermediate material comprises: a first material that is doped with aluminum or gallium, or a second material that is undoped.
6. The method of claim 5, wherein the aluminum-or gallium-containing doped first material or undoped second material comprises:
the first material comprises: aluminum-doped zinc oxide or gallium-doped zinc oxide;
the second material comprises: zinc oxide.
7. The method of manufacturing a sidewall according to claim 5, wherein the intermediate material has a light transmittance in the interval of [40%,50% ].
8. A side wall manufacturing apparatus, comprising: the device comprises an intermediate material preparation unit, a photomask structure preparation unit and a chip side wall morphology preparation unit; wherein,
the intermediate material preparation unit is used for adding at least one layer of intermediate material with lower light transmittance than the second layer of material between the opaque first layer of material and the light-transmitting second layer of material of the photomask of the passivation protection layer;
the photomask structure preparation unit is used for adjusting the first length of the first layer of material and the second length of the intermediate material according to the functional requirement of the chip, combining the first length of the first layer of material and the second length of the intermediate material to obtain a plurality of photomask structures, and arranging the plurality of photomask structures to obtain a target photomask structure;
the chip side wall morphology preparation unit is used for photoetching the passivation layer of the semiconductor chip by using the target photomask structure, and respectively etching and photoresist removing the semiconductor chip to obtain various chip passivation layer side wall morphologies.
9. A chip, comprising: various chip passivation layer side wall morphology; wherein,
the side wall morphology of the chip passivation layers at least comprises any two of a first light cover structure, a second light cover structure and a third light cover structure; the sidewall morphology of the passivation layers of the chips is obtained according to the sidewall manufacturing method of any one of claims 1-7.
10. An electronic device is characterized by comprising a circuit board and a chip; the side wall morphology of the chip is obtained based on the side wall manufacturing method according to any one of claims 1 to 7; the chip is arranged on the circuit board and is electrically connected with the circuit board.
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| CN101025566A (en) * | 2006-02-22 | 2007-08-29 | Hoya株式会社 | Pattern forming method and gray-tone mask manufacturing method |
| CN105047614A (en) * | 2015-06-07 | 2015-11-11 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of semiconductor memory |
| CN115202146A (en) * | 2021-04-14 | 2022-10-18 | 上海传芯半导体有限公司 | Phase-shifting mask and manufacturing method thereof |
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