CN117634407A - Integrated circuit layout position searching method and device and electronic equipment - Google Patents

Abstract

The invention discloses a method, a device and electronic equipment for searching an integrated circuit layout position. S1, determining a specific search area for searching a vacancy according to key parameters; s2, selecting an effective area from the specific search areas according to additional conditions; s3, removing the laid-out area from the effective area to obtain a vacancy; s4, classifying and sequencing the space bits to obtain a search result. The invention does not need manual advanced precision planning, has high flexibility, does not need to move the laid-out units, protects the original time sequence, improves the searching efficiency, avoids the influence of layout density, and has extremely high accuracy.

Description

Integrated circuit layout position searching method and device and electronic equipment

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to a method, an apparatus, and an electronic device for searching an integrated circuit layout position.

Background

The digital integrated circuits such as the high-performance and high-reliability processors have the characteristics of high performance, high reliability, high main frequency, high bandwidth and the like, and have higher requirements on physical design. Some scenes that utilize the remaining free area (empty space) and precisely determine the position on the laid-out layout are often encountered in digital layout designs, such as replacing standard cells of key modules with custom high-performance cells at the layout stage; cell reorganization of a local layout; adding redundancy units directionally after layout; the accurate layout of the hierarchical design boundary interface unit; automatic repair of design rule violations; a position rearrangement of a critical timing path, and the like.

Existing EDA layout tools have two ways in which position limits can be set for the layout. One is to manually plan the exact location before layout, for example, using SDP (Structured Data Path), setting layout Guide, region, etc.; the other is to squeeze out a free position by swaying other standard cells on the laid-out layout.

In high performance designs, these functions of the EDA tool tend to handle the above-mentioned scenarios or inefficiencies. The manual planning mode before layout has extremely high requirements on the capability of engineers, lacks flexibility, needs long iteration and can weaken the position limitation under the condition of high layout density. By moving other standard units to squeeze out the idle position, the tool can move other units when squeezing out the position and does not fully consider the time sequence condition of other units, the time sequence is often destroyed first, then the time sequence is optimized and recovered additionally, and under the limit frequency, the time sequence is often difficult to recover, so that the performance of a critical path is reduced. In addition, under the condition of high layout density, the optimization capability of the EDA layout and wiring tool is drastically reduced, and the purpose of optimizing the reliability and the performance is further achieved by continuously utilizing scattered layout free areas without effective means.

Disclosure of Invention

The invention aims to provide a method, a device and electronic equipment for searching the layout position of an integrated circuit, which can avoid the influence of layout density, quickly and efficiently search for a vacant position without moving a laid-out unit, and accurately plan a circuit in advance without an engineer, thereby improving the flexibility of positioning search.

The technical scheme adopted is as follows:

in a first aspect, the present invention provides a method for searching for an integrated circuit layout position, the method comprising the steps of:

s1, determining a specific search area for searching a vacancy according to key parameters;

s2, selecting an effective area from the specific search areas according to additional conditions;

s3, removing the laid-out area from the effective area to obtain a vacancy;

s4, classifying and sequencing the space bits to obtain a search result.

The layout position searching method adopted by the invention can search the vacancy of the laid-out circuit without planning in advance, has higher flexibility, removes the influence of the laid-out area in the searching and positioning process, namely does not destroy the time sequence of the laid-out unit, protects the performance of the original circuit, saves the step of moving the laid-out unit, and accelerates the searching speed.

Preferably, in step S1, the method of determining the specific search area follows the steps of:

s11, obtaining a specific area or a subarea list with any shape through key parameters, and storing the specific area in the subarea list in a list form to obtain an area list, namely a specific search area. By converting the region into a list form, the list data can be directly used for calculation in subsequent searches, and the data can be easily processed.

Preferably, after obtaining the region list, the following steps are performed:

s111, quantifying a layout area list space by using Site and Row, and acquiring a Row list covered by an area list through the area list;

s112, acquiring a Site list which can be searched in the area list through the Row list.

The Site and Row quantization layouts are selected to correspond to the circuit layout and the characteristics of the gaps, and the data can be effectively processed and screened.

Preferably, the method of step S2 specifically includes the following steps:

s21, establishing an additional condition library according to design elements in the circuit design process, wherein the additional condition library at least comprises one additional condition;

s22, selecting at least one additional condition as a judging condition, judging whether the Site in the Site list is effective, if not, reselecting the additional condition as a judging condition, if so, further judging whether the Row in the Row list is effective according to the effective Site, if not, reacquiring the Row list, and if so, performing AND operation on the effective Row and the region list to obtain a Row Box list;

s23, removing the Row Box fragments which do not meet the Site standard from the Row Box list;

s24, selecting unused additional conditions by using a multiple additional condition filter to screen the Row Box list to obtain an effective Row Box list, namely an effective area.

Through multiple times of data screening, the searching range can be continuously reduced, and the accuracy of the searching result is improved.

Preferably, the following steps are performed after obtaining the vacancies:

s31, filtering vacancy fragments unsuitable for layout according to layout design rule information of a process plant to obtain a vacancy list, vacancy information and vacancy attributes;

and S32, storing the vacancy information and the vacancy attribute in a data structure.

And the accuracy of obtaining the vacancy data is ensured through filtering and screening again, and the vacancy data is stored in a proper data structure, so that the vacancy data is convenient to call during subsequent processing.

Preferably, in step S4, the method for classifying and sorting the space bits includes the following steps:

s41, classifying the vacancies according to vacancy information and vacancy attributes to obtain at least one category, wherein the vacancy information is at least one;

s42, constructing a coordinate system for each category, and carrying out sequencing calculation on the gaps of the category in each coordinate system.

By establishing a coordinate system and calculating under each category of the empty spaces, the searching result can be clearly displayed, the ordering errors among the empty spaces of different categories can be reduced, and the ordering accuracy is improved.

Preferably, when the number of the categories is at least two, weights are set for the corresponding categories, and the weighted summation obtains a score, and the score is ranked according to the score. By setting the weighted summation mode, the vacant sites under different categories can be ranked together, the vacant sites are not required to be ranked under each category independently, and the obtained result is more simplified.

In a second aspect, the present invention provides an apparatus comprising:

the searching region calculating module is used for determining a specific searching region for searching the empty space according to the key parameters;

an effective area calculation module for selecting an effective area from the specific search areas according to the additional condition;

the vacancy calculating module is used for removing the laid-out area in the effective area to obtain a vacancy;

and the vacancy classifying and sorting module is used for classifying and sorting the vacancies to obtain search results.

In a third aspect, the present invention provides an electronic device comprising a memory and a processor, the processor being coupled to the memory; wherein the memory is configured to store a program and the processor is configured to invoke the stored program to perform the method of integrated circuit layout position searching in the first aspect.

Compared with the prior art, the invention has the following beneficial effects:

aiming at the scene of incremental layout on the laid-out layout, the invention accurately searches the rest vacant sites according to different attributes of the layout and the wiring under the condition of not moving the laid-out units in the layout, inquires the accurate coordinates of the vacant sites, and can sort the vacant sites according to different requirements. In the searching process of the invention, the method is not influenced by the layout density to find out the gaps, can be further used for improving the area utilization rate and optimizing the time sequence, and can ensure that the original time sequence is not destroyed to the greatest extent because the positions of the laid-out units near the gaps are not changed, and the searching process is independent and has short searching time.

Drawings

FIG. 1 is a flowchart of an integrated circuit layout position searching method according to an embodiment of the present application;

FIG. 2 is a flow chart of calculating and processing a specific search area provided in an embodiment of the present application;

FIG. 3 is a flowchart of calculating a specific search area according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an additional condition selection provided in an embodiment of the present application;

FIG. 5 is a flowchart of an effective area calculation according to an embodiment of the present application;

fig. 6 is a schematic diagram of an integrated circuit layout position searching device according to an embodiment of the present application.

Reference numerals illustrate: 8. a device; 80. a bus; 81. a search area determination module; 82. an effective area calculation module; 83. a vacancy calculating module; 84. a vacancy classification and ordering module; 811. a basic input unit; 812. a storage unit; 813. a quantization unit; 821. a condition judgment unit; 822. an AND operation unit; 823. a filtering unit; 831. a laid-out area counting unit; 832. a removing unit; 833. a vacancy storage unit; 841. a vacancy classifying unit; 842. and a vacancy ordering unit.

Detailed Description

The following describes the technical solution in the embodiment of the present invention in detail with reference to the drawings in the embodiment of the present invention.

As shown in fig. 1, the present embodiment is a method for searching the layout position of an integrated circuit, which uses parameters to delineate the area where the gaps are located and eliminates the laid-out portion, and then performs multiple screening, classification and sorting to obtain the accurate position of the gaps.

A method of integrated circuit layout position searching, comprising the steps of:

s1, determining a specific search area for searching a vacancy according to key parameters;

s2, selecting an effective area from the specific search areas according to additional conditions;

s3, removing the laid-out area from the effective area to obtain a vacancy;

and S4, classifying and sequencing the gaps to obtain a search result.

The method is capable of inquiring the positions of the vacant sites under the condition that the laid-out units in the layout are not moved, classifying and sorting the vacant sites according to different requirements, high in flexibility, free from the influence of layout density in the searching process, short in searching time and high in efficiency, and the process of moving the laid-out units is omitted.

It should be noted that the key parameters are set according to the known conditions of the circuit or the requirement of the available space, and the number of the key parameters can be one, two or more, so long as the specific search area where the space is located can be selected.

FIG. 2 illustrates a flow chart for computing and processing a particular search area in accordance with at least one embodiment of the present invention.

As shown in fig. 2, the calculation step of this embodiment includes S11, and the processing steps include S111 and S112.

In step S11, a specific region or a sub-region list with any shape is obtained through the key parameters, and then the specific region is stored in the sub-region list in the form of a list, so as to obtain a region list, namely a specific search region. The regions are converted into a list form, so that subsequent data calculation and screening are facilitated.

In step S111, the layout area list space is quantized using Site and Row, and Row covered by the area list is acquired by the area list, thereby obtaining a Row list.

In step S112, the Site list is obtained by acquiring the sites that can be searched in the region list through the Row list.

In the integrated circuit layout, site and Row are used as layout and wiring tools, so that the height is kept unchanged, the layout is arranged in the transverse direction and the longitudinal direction, the information and the attribute of the empty space correspond to the information and the attribute of the empty space, the actual circuit layout requirements are met, the layout space is convenient to quantify, the data screening is convenient to use by using the height standard, and the searching accuracy is improved.

In the embodiment, three key parameters of a search center, a search radius and a search area are used as basic inputs to obtain a plurality of specific areas with arbitrary shapes, each specific area is segmented into rectangular and triangular shapes, each segmented shape is merged into a subarea list in a list form, and repeated parts are removed to obtain a final area list, namely the specific search area. Furthermore, if the specific coordinates related to the null are known in the circuit, the specific coordinates may be used as key parameters, or the specific coordinates may be used as key parameters together with other parameter conditions, and the above-described process may be repeated. The specific area is segmented, so that the data can be conveniently combined and stored, the processing speed can be increased, and the efficiency of positioning search can be improved; and in the process of segmentation and merging, the duplicate removal processing is also performed, so that useless redundant data is reduced, the running speed is increased, and the efficiency of positioning search is improved.

As shown in fig. 4 and 5, in step S2, additional conditions are selected to determine the effective area from the specific search area, and steps S21, S22, S23, and S24 are required to be followed.

In step S21, additional conditions are determined according to design elements in the integrated circuit layout design process, and an additional condition library is built according to the additional conditions, wherein at least one additional condition is required in the additional condition library. The additional conditions may be a void size, a void type, a greedy region, an invalid region, a power domain, a voltage drop condition, a wiring blocking condition, a timing condition, a laid-out cell avoiding condition, a laid-out cell preference condition, a laid-out function module avoiding condition, a laid-out function module preference condition, etc., and design elements closely related to layout are selected as the additional conditions, so that the data can be better screened and judged when the additional conditions are used.

In step S22, at least one additional condition is selected as a judging condition, and if the additional condition is invalid, the additional condition is selected again as a judging condition, if the additional condition is valid, the Row in the Row list is further judged to be valid according to the valid condition, if the Row is invalid, the Row list is obtained again, and if the Row is valid, the valid Row and the region list are subjected to an and operation to obtain a Row Box list. When the additional conditions are selected for judgment, one or a plurality of additional conditions can be selected for limiting according to the requirement of the incremental layout scene in the circuit, and the range of the area where the empty position is located is further reduced.

In an embodiment, as shown in fig. 4, when a specific type of slot needs to be obtained, the type of slot is selected from the additional condition library as a judging condition, so that the waste of search time on other types of slots and the influence on efficiency are avoided.

In some embodiments, the circuit is designed with multiple voltage domains, a gap is required to be searched at the junction of multiple power domains, the power domains are selected as judging conditions, the range of the area where the gap is located is reduced, and the searching speed can be increased.

In some embodiments, the required space has more than one feature, if a certain type of space is searched at the junction of multiple power domains, the power domains and the space types are selected as judging conditions, and the search speed is faster when the range is reduced twice.

In step S23, the Row Box fragment needs to be removed from the Row Box list.

In conjunction with fig. 5, in the embodiment, when the effective Row and region list are and-calculated, a number of Row Box fragments not conforming to the Site standard may be generated, especially, incomplete Row boxes with a height smaller than the Site height near the boundary of the search region may affect the calculation result, and after the fragments are removed, the Row Box list is more compact and the data is more accurate.

In step S24, the multiple additional condition filters are used to select the additional conditions that are not used to filter the Row Box list, so as to obtain an effective Row Box list, i.e. an effective area.

In combination with fig. 5, in the embodiment, the multiple additional condition filters select additional conditions which are not used in the searching process, screen the data again, further reject the data which do not meet the conditions, and can form multi-azimuth optimization and screening for the data with the additional conditions which have been used before, thereby improving the accuracy of positioning searching in depth.

As shown in fig. 5, in the embodiment, the method for calculating the effective area from the specific search area first determines whether the Site in the obtained Site list is effective, if not, the Site list is abandoned and the Site list is reselected, if so, whether the Row in the Row list is effective is further determined according to the effective Site, if the Row is not effective, the Row list is reacquired, and if the Row is effective, the effective Row and the area list are subjected to an and operation to obtain a Row Box list, namely an effective area; and generating a plurality of Row Box fragments which do not meet the Site standard in the operation process, removing the fragments from the Row Box list, and continuously screening out data which do not meet the additional conditions by using a plurality of additional condition filters, thereby obtaining an effective area after multiple screening and filtering. Through multiple judgment, filtration and screening, the position of the area where the vacancy is located can be continuously reduced, the effective area is simplified, and the accuracy of vacancy searching is improved.

In step S3, the laid-out area is removed from the effective area to obtain a vacancy, the laid-out unit in the effective area needs to be searched according to the coordinate information of the effective area, the position information of the coordinate, shape, size, area and the like of the laid-out unit is counted, and the laid-out area is calculated, so that the laid-out area can be removed, the influence on the laid-out area in the positioning search process is avoided, the tedious process of moving the laid-out unit is omitted, the searching speed is increased, and the time sequence and performance of the original circuit are protected.

In step S3, after obtaining the empty space, steps S31 and S32 need to be performed:

s31, filtering vacancy fragments unsuitable for layout according to layout design rule information of a process plant to obtain a vacancy list, vacancy information and vacancy attributes;

s32, storing the vacancy information and the vacancy attribute in a data structure.

In the embodiment, in step S31, after the vacancy is obtained, a part of vacancy fragments still exist in the vacancy, and the vacancy fragments unsuitable for layout are filtered according to the layout design rule information of the process plant, and the rest is the final effective vacancy and the corresponding vacancy list, vacancy information and vacancy attribute thereof, and the data are stored in the multidimensional hash data structure. The vacancy information includes a vacancy name, a vacancy coordinate, a vacancy size, a vacancy type, and the like, and the vacancy attribute is data such as option content described in the additional condition library, and each boolean value, maximum value, minimum value, mean value, variance, and the like calculated according to the additional condition in the region where the vacancy is located. By filtering the vacancy fragments again, the searching range is further reduced, the accuracy of searching data is improved, and the vacancy information and the vacancy attribute are stored in the data structure, so that the vacancies can be classified and ordered by using the data later.

In step S4, the empty bits are classified and ordered to obtain empty bits, including two steps of S41 and S42:

s41, classifying the vacancies according to the vacancy information and the vacancy attribute to obtain at least one category, wherein the vacancy information is at least one;

s42, constructing a coordinate system for each category, and carrying out sequencing calculation on the gaps of the category in each coordinate system.

In step S41, the slot information and the slot attribute need to be extracted from the data structure as classified categories, and then the slots are sorted under each classified category, for example, different slots may be sorted separately by the slot type, different power domains may be sorted separately, different time sequences may be sorted separately, and so on. Sorting is performed according to the categories, and then sorting is performed, so that the sorting process is clearer and clearer, the sorting result is simpler, and the positioning search time is short.

It should be noted that there is no fixed number relationship between the vacancy information and the vacancy attribute, and at least one of the vacancy information is based on the nature of the vacancy itself, and the vacancy attribute may be zero.

In step S42, a coordinate system needs to be constructed for each category, and the coordinate system may be a cartesian coordinate system, a polar coordinate system, a cylindrical coordinate system, or the like, without being limited thereto.

In step S4, when the number of categories is at least two, a weight is further required to be set for each category, a score is obtained by adopting a weighted summation method, and then the scores are sorted according to the numerical value of the score. By adopting a weighted summation mode, the empty spaces of a plurality of categories can be selected to be ranked together, and a simplified ranking result is obtained.

It should be noted that, when the number of the categories is at least two, weighted summation may be adopted, or each category may be separately ordered, and selected according to actual requirements.

In the embodiment, a space rectangular coordinate system is constructed by taking a search center as an origin, the X axis and the Y axis are in the same direction as the plane coordinates of the integrated circuit digital layout, the X value is the linear distance between the projection of the vacancy position on the X axis and the search center, the Y value is the linear distance between the projection of the vacancy position on the Y axis and the search center, the Z axis is the weighted calculation score of the mean value or the maximum value or the minimum value of the selected vacancies, the obtained vacancies are calculated in the space rectangular coordinate system, and the vacancies are ordered according to the numerical value of the Z axis, so that an accurate layout search result can be obtained.

In the embodiment, in the scene that the redundant units are added after the layout, a space rectangular coordinate system is constructed, and the wiring blocking value above the empty position is selected as the Z axis, so that the influence of the redundant units on the existing wiring can be avoided as much as possible.

As shown in fig. 5, an apparatus 8 for searching for an integrated circuit layout position, the apparatus 8 includes four modules:

a search area calculation module 81, configured to determine a specific search area for searching for a space according to the key parameter;

an effective area calculation module 82 for selecting an effective area from the specific search areas according to additional conditions;

a vacancy calculating module 83, configured to remove the laid-out area from the effective area, so as to obtain a vacancy;

a slot classification and ranking module 84, configured to classify and rank the slots to obtain search results.

In an embodiment, as shown in fig. 6, the apparatus 8 is used for searching the layout position of the integrated circuit, and includes a search area calculation module 81, an effective area calculation module 82, a vacancy calculation module 83, and a vacancy classification and sorting module 84, where data is transmitted between the four modules through a bus 80. In the search area calculation module 81, the basic input unit 811 is configured to input key parameters, store the obtained area list in the storage unit 812, and then quantize the layout space that needs to be processed by the apparatus 80 by using the quantization unit 813 with Site and Row, to obtain a Site list of the area list in the storage unit 812; the processing result of the quantization unit 813 is transmitted to the condition judgment unit 821 in the effective region calculation module 82 through the bus 80, the judgment unit 821 further narrows the range of the layout position by using additional conditions, obtains an effective Row and transmits the effective Row to the and operation unit 822, performs graph and operation on the effective Row and the region list to obtain a Row Box list, and then transmits the Row Box list to the filtering unit 823 to screen out fragment data which does not meet the standard, so as to obtain an effective Row Box list, namely an effective region; the data of the effective area is transmitted to a vacancy calculating module 83 through a bus 80, a laid-out area counting unit 831 is arranged in the vacancy calculating module 83, the laid-out area in the effective area is obtained, and then calculation is performed in a removing unit 832, so that a vacancy is obtained and is put in a vacancy storing unit 833; the data of the gaps are transmitted to the gap classifying and sorting module 84 through the bus, the gaps are classified into one or more categories in the gap classifying unit 841, and the classified data are transmitted to the gap sorting unit 842 to construct a coordinate system for calculation and sorting, so as to obtain the layout search result.

In some embodiments, the device 8 is provided with a search area calculation module 81, an effective area calculation module 82, a vacancy calculation module 83, and a vacancy classification and sorting module 84, wherein each module is divided into a plurality of functional units, and the device is further provided with a cache storage unit for storing data generated by other units when the device 8 is operated, and each module directly reads the required data from the cache storage unit, so as to finally complete the search.

It should be noted that, the transmission between the modules in the device 8 may be performed by using a bus or a cache storage unit, or may be other transmission devices, or may be wired or wireless, so long as the data transmission between the modules can be completed. In addition, the technical effects of the apparatus 8 may be referred to the above description of the method for searching the layout position of the integrated circuit, which is not repeated here.

The present invention also provides an electronic device for integrated circuit layout position searching, the electronic device comprising a memory and a processor, the memory and the processor being interconnected, the memory being adapted to store a program, the program in the stored program being the program code described above in relation to the integrated circuit layout position searching method, the processor being adapted to invoke the stored program to perform one or more steps in the integrated circuit layout position searching method as described above.

The processor employed in this embodiment may be a central processing unit, a graphics processor or other form of processing unit with data processing capabilities, and the memory may be any combination of one or more computer program products.

It should be noted that, in embodiment 3 of the present invention, specific functions and technical effects of the electronic device may refer to the description of the method for searching the layout position of the integrated circuit in embodiment 1, which is not repeated here.

In summary, in the method, the device and the electronic equipment for searching the layout position of the integrated circuit, the quantization processing of the integrated circuit is performed, accurate layout planning is not needed in advance, flexibility is higher, the laid-out units are removed in the effective area, vacancy searching can be completed under the condition that the laid-out units are not moved, the original time sequence is protected, the step of recalculating the moving time sequence is reduced, the searching process is shortened, the searching efficiency is improved, in addition, the screening and filtering of data are performed for a plurality of times, the influence of layout density is avoided in the searching process, the efficient searching of vacancies is realized, incremental layout is performed by utilizing the vacancies, and the searching accuracy and the layout area utilization rate are improved.

Explanation of terms in the examples:

1) Search Center (Search Center): the reference point for the vacancy distance metric, a coordinate system is established centered around this point.

2) Search Radius (Search Radius): chebyshev (Chebyshev) is the furthest search distance near the search center.

3) Search Area (Search Area): the polygon searching range can be a square area determined by a searching center and a searching radius, or can be a custom area.

4) Site: the type of void, which determines the height of the standard cell into which the void is placed. There may be multiple types of gaps in the search area at the same time, which need to be classified for screening.

5) Row: the Row is also the basic search area, which is determined by site and has a standard cell layout area with a specific arrangement rule.

6) Gap Distance (gap Distance): the gap boundary is the shortest Manhattan distance from the search center. It measures how far from the reference point the null is.

7) Vacancy coordinates (vacancies Distance): the coordinates of the empty space in the selected coordinate system are selectable according to the specific application scenario, and are not limited to a Cartesian coordinate system, a polar coordinate system, a cylindrical coordinate system and the like.

8) Greedy region: and 2, adding a condition to the step 2, wherein the priority ordering of the specific area with high priority ordering can be a one-gear or multi-gear threshold judgment method.

9) Invalid region: the step 2 is provided with the additional condition that the specific area or the area list is not judged to be valid.

10 Power Domain): step 2, with the additional condition of valid or invalid power domain range.

11 Voltage drop condition): and 2, dividing the partitions according to the adjustable granularity, wherein each partition has voltage drop range information, and judging whether the partition is an effective area according to the voltage drop range information.

12 Wiring blocking condition): and 2, dividing the subareas according to the adjustable granularity, wherein each subarea is provided with wiring blocking information, judging whether the subareas are effective areas according to the blocking information, and the blocking information can be, but is not limited to, a representation form of the use proportion of winding resources.

13 Timing conditions): step 2, under the additional condition that the partitions are divided according to the adjustable granularity, each partition is provided with Pin timing information, whether the partition is an effective area is judged according to the timing information, and the timing information can be but is not limited to a representation form of a Pin timing violation (Pin slot) range.

14 A laid out cell avoidance condition): step 2, additional conditions, set the list of laid out cells and the avoidance distance. And is regarded as an ineffective area within the avoiding distance of the laid-out cells.

15 Layout cell preference conditions): step 2, additional conditions, set the list of laid out cells and the preference distance. The effective area with higher priority is considered in the preference distance of the laid out cells.

16 A laid out functional module avoidance condition): step 2, with the additional condition, a list of function modules (modules) is set as the avoidance condition, and the area in the list, in which the function modules are laid out, is regarded as an invalid area.

17 Laid out functional module preference: step 2, with the additional condition that a list of function modules (modules) is set as a preference, and the area in the list, in which the function modules are laid out, is regarded as an effective area, i.e. a space is searched for in or near the area in the list, in which the function modules are laid out.

The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention.

Claims (9)

1. A method for searching for an integrated circuit layout position, comprising the steps of:

s1, determining a specific search area for searching a vacancy according to key parameters;

s2, selecting an effective area from the specific search areas according to additional conditions;

s3, removing the laid-out area from the effective area to obtain a vacancy;

and S4, classifying and sequencing the gaps to obtain a search result.

2. The method of claim 1, wherein in step S1, the method of determining the specific search area follows the steps of:

s11, obtaining a specific area or a subarea list with any shape through key parameters, and storing the specific area in the subarea list in a list form to obtain an area list, namely a specific search area.

3. The method of claim 2, wherein after obtaining the region list, performing the steps of:

s111, quantifying a layout area list space by using Site and Row, and acquiring a Row list covered by an area list through the area list;

s112, acquiring a Site list which can be searched in the area list through the Row list.

4. A method for searching for an integrated circuit layout position according to claim 3, wherein the step S2 comprises the steps of:

s21, establishing an additional condition library according to design elements in the circuit design process, wherein the additional condition library at least comprises one additional condition;

s22, selecting at least one additional condition as a judging condition, judging whether the Site in the Site list is effective, if not, reselecting the additional condition as a judging condition, if so, further judging whether the Row in the Row list is effective according to the effective Site, if not, reacquiring the Row list, and if so, performing AND operation on the effective Row and the region list to obtain a Row Box list;

s23, removing the Row Box fragments which do not meet the Site standard from the Row Box list;

s24, selecting unused additional conditions by using a multiple additional condition filter to screen the Row Box list to obtain an effective Row Box list, namely an effective area.

5. The method of claim 1, wherein the steps of obtaining the gaps are performed as follows;

s31, filtering vacancy fragments unsuitable for layout according to layout design rule information of a process plant to obtain a vacancy list, vacancy information and vacancy attributes;

and S32, storing the vacancy information and the vacancy attribute in a data structure.

6. The method of claim 1, wherein in step S4, the method of classifying and ordering the slots comprises the steps of:

s41, classifying the vacancies according to vacancy information and vacancy attributes to obtain at least one category, wherein the vacancy information is at least one;

s42, constructing a coordinate system for each category, and carrying out sequencing calculation on the gaps of the category in each coordinate system.

7. The method of claim 6, wherein when the number of categories is at least two, weights are set for the categories, and a weighted sum results in a score, and the ranking is based on the score.

8. An apparatus for searching for an integrated circuit layout position, comprising:

the searching region calculating module is used for determining a specific searching region for searching the empty space according to the key parameters;

an effective area calculation module, configured to select an effective area from the specific search areas according to an additional condition;

the vacancy calculating module is used for removing the laid-out area from the effective area to obtain a vacancy;

and the vacancy classifying and sorting module is used for classifying and sorting the vacancies to obtain search results.

9. An electronic device, comprising:

the device comprises a memory and a processor, wherein the processor is connected with the memory;

wherein the memory is for storing a program and the processor is for invoking the stored program to perform the method of any of claims 1-7.