CN117632611A - General testing device for microprocessor chip - Google Patents

General testing device for microprocessor chip Download PDF

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Publication number
CN117632611A
CN117632611A CN202311655128.7A CN202311655128A CN117632611A CN 117632611 A CN117632611 A CN 117632611A CN 202311655128 A CN202311655128 A CN 202311655128A CN 117632611 A CN117632611 A CN 117632611A
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test
pcb substrate
tested
board
chip
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CN117632611B (en
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胡文懿
陈小波
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Beijing Zhongtian Xingkong Science & Technology Development Co ltd
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Beijing Zhongtian Xingkong Science & Technology Development Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The application discloses a general testing device of a microprocessor chip, which comprises a testing sub-board, a testing bottom board and a T800 digital testing machine table, wherein the testing sub-board is in a multi-mode shape, each mode comprises a testing seat, and each testing seat can be matched with a group of microprocessor chips to be tested with the same pin number; fixing the microprocessor chip to be tested through the test seat on the test daughter board, and connecting pins of the microprocessor chip to be tested to the test bottom plate; the upper part of the test bottom plate is connected with the test daughter board, the lower part of the test bottom plate is connected with the resource leading-out board of the T800 digital test machine, 176 pin resources are arranged on the test bottom plate according to the pin distribution rule of the STM32F407IGTX chip, and the resource leading-out board connected to the T800 digital test machine is led out; and serial communication is used between the T800 digital test machine and the microprocessor chip to be tested.

Description

General testing device for microprocessor chip
Technical Field
The present disclosure relates to chip testing technologies, and in particular, to a general testing apparatus for a microprocessor chip.
Background
The traditional microprocessor chip testing method comprises the following steps: the test vector of the microprocessor chip is converted into the test vector of the test machine on the T800 digital machine for testing, but the number of pins of the microprocessor chips with different models is different due to the fact that the models of the microprocessor chips on the market are more and more at present, so that the existing test system and test method cannot simultaneously meet the number of pins of each model, and the defects of no portability, high test development difficulty, long period and the like are caused.
In view of the above-mentioned testing difficulties, the present invention aims to automatically test the most of the microprocessor chips on the market, which have different pin numbers, different packages and different capacities, by using one set of testing system. The method is convenient for program transplantation and reduces the difficulty and period of test development.
In view of the foregoing, there is a need for a general testing device for microprocessor chips, which can automatically test the microprocessor chips with different pin numbers, different packages and different capacities by one set of testing device for the mainstream microprocessor chips in the market.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present application proposes a general testing device for microprocessor chips, which solves the problem that the prior art cannot automatically test microprocessor chips with different pin numbers, different packages and different capacities by using a set of testing system.
The application specifically adopts the following technical scheme for realizing the purposes:
a general testing device for microprocessor chip includes a testing sub-board, a testing bottom board and a T800 digital testing machine, wherein:
the test sub-board is in a multi-mode shape, each mode comprises a test seat, and each test seat can be matched with a group of microprocessor chips to be tested, the pins of which are the same in number; fixing the microprocessor chip to be tested through the test seat on the test daughter board, and connecting pins of the microprocessor chip to be tested to the test bottom plate;
the upper part of the test bottom plate is connected with the test daughter board, the lower part of the test bottom plate is connected with the resource leading-out board of the T800 digital test machine, 176 pin resources are arranged on the test bottom plate according to the pin distribution rule of the STM32F407IGTX chip, and the resource leading-out board connected to the T800 digital test machine is led out; the resource leading-out board leads out the test resources of the T800 digital test machine;
the T800 digital test machine is communicated with the microprocessor chip to be tested by using a serial port, and the serial port can automatically download a test program and an erase program to test the direct current parameter, the alternating current parameter and the chip function of the microprocessor chip to be tested.
As an optional technical scheme, the test sub-board is a first PCB substrate and comprises an upper surface and a lower surface which are opposite, wherein the upper surface is provided with a test seat capable of fixing a microprocessor chip to be tested, and the lower surface is provided with an European type connector plug.
As an optional technical scheme, the test seat comprises a fixed base and a cover plate, wherein an accommodating cavity for placing a microprocessor chip to be tested is formed in the upper surface of the fixed base, and the cover plate is hinged to the fixed base.
As an optional technical scheme, the test base plate is a second PCB substrate, and an european style connector socket matched with the european style connector plug on the first PCB substrate is disposed on the upper surface of the second PCB substrate;
the second PCB substrate is provided with a plurality of connecting holes, and the lower surface of the second PCB substrate is provided with a pogo pin connector.
As an optional technical scheme, the resource extraction plate is a third PCB substrate, a plurality of connection holes are formed in the third PCB substrate and correspond to the connection holes in the second PCB substrate one by one, and the third PCB substrate and the second PCB substrate are detachably connected through a connecting piece;
the third PCB substrate comprises an upper surface and a lower surface which are opposite, the upper surface comprises a pogo pin connection area matched with the pogo pin connector on the second PCB substrate, and the lower surface is connected with the T800 digital test machine.
As an optional technical solution, the dc parameter includes an input high-level voltage threshold VIH, an input low-level voltage threshold VIL, an output high-level voltage value VOH, an output low-level voltage value VOL, a PULL-up-resistance, a PULL-DOWN-resistance, a dc parameter in the ADC, a dc parameter in the DAC, and an operating current PWR in various modes.
As an alternative solution, the ac parameters include an ac parameter in the high-speed external clock signal HSE, the low-speed external clock signal LSE, the high-speed internal clock signal HSI, the low-speed internal clock signal LSI, the TIMER, and an ac parameter in the watchdog WDG.
As an alternative technical scheme, the chip functions comprise Boot loader, CAN communication, I2C communication, SPI communication, USART/UART communication, a random number generator RNG and a Cyclic Redundancy Check (CRC).
The beneficial effects of this application include:
a set of universal testing device can test microprocessor chips with different pin numbers, different packages and different capacities. The difficulty of using vectors for testing is solved.
Other benefits or advantages of the present application will be described in detail with reference to specific structures in the detailed description.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive faculty for a person skilled in the art. Furthermore, it should be understood that the scale of each component in the drawings in this specification is not represented by the scale of actual material selection, but is merely a schematic diagram of structures or positions, in which:
FIG. 1 is a schematic view of a test socket according to the present application;
fig. 2 is a schematic diagram of an upper surface of a second PCB in the present application;
fig. 3 is a schematic view of a lower surface of a second PCB in the present application;
fig. 4 is a schematic view of an upper surface of a first PCB in the present application;
fig. 5 is a schematic view of the lower surface of the first PCB in the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
In the description of the present application, it should be noted that terms such as "top" and "bottom" are used to refer to a portion of the present application that is close to the upper side in the use state as a top, and a portion that is close to the lower side as a bottom; the use of terms such as "first" and "second" is for the purpose of distinguishing between similar elements and not necessarily for the purpose of indicating or implying any particular importance or order of such elements; terms such as "inner", "outer" and "inner and outer" are used to refer to specific contours. The above terms are used only for the sake of clarity and simply to describe the technical solutions of the present application, and should not be construed as limiting the present application.
Example 1:
the invention provides a general testing device of at least one microprocessor chip, which comprises a testing daughter board, a testing bottom board and a T800 digital testing machine, wherein:
the test sub-board is in a multi-mode shape, each mode comprises a test seat, and each test seat can be matched with a group of microprocessor chips to be tested, the pins of which are the same in number; fixing the microprocessor chip to be tested through the test seat on the test daughter board, and connecting pins of the microprocessor chip to be tested to the test bottom plate;
the upper part of the test bottom plate is connected with the test daughter board, the lower part of the test bottom plate is connected with the resource leading-out board of the T800 digital test machine, 176 pin resources are arranged on the test bottom plate according to the pin distribution rule of the STM32F407IGTX chip, and the resource leading-out board connected to the T800 digital test machine is led out; the resource leading-out board leads out the test resources of the T800 digital test machine;
the T800 digital test machine is communicated with the microprocessor chip to be tested by using a serial port, and the serial port can automatically download a test program and an erase program to test the direct current parameter, the alternating current parameter and the chip function of the microprocessor chip to be tested.
It can be understood that: the T800 digital test machine has rich I/O channels, flexible time sequence configuration, sufficient depth and high test speed, and meets the test requirement of the micro processor. 176 pin resources are set on the testing bottom plate according to the pin distribution rule of the STM32F407IGTX chip, and the resource leading-out plate connected to the T800 digital testing machine is led out for testing direct current parameters, alternating current parameters and chip functions.
The self-contained resource leading-out board on the T800 digital test machine has no test function, and can only lead out the test resource from the T800 digital test machine, and the test can be started only by being connected with the test base plate. The STM32F407ZET6 chip is used as an auxiliary test microprocessor chip for testing communication functions. The T800 digital test machine and the microprocessor chip to be tested are communicated by using a serial port, and meanwhile, the serial port can also automatically download a test program and an erase program.
The test sub-board is in a multi-mode shape, each mode comprises a test seat, each test seat can be matched with a group of microprocessor chips to be tested with the same pin number, and the test sub-board is used for connecting pins of different types of microprocessor chips to a test base plate. If the microprocessor chips with different models are to be tested, only different test sub-boards need to be replaced, so that the difficulty and period of test development are reduced.
Furthermore, one test daughter board can be matched with a plurality of chips with the same pin number and different types, so that the difficulty and period of test development are further reduced, and the multi-mode meaning is that: all pin counts including maximum pin down compatibility, one modality being involved according to each pin count;
it should be noted that: the conventional test does not use a universal test board, and each time a chip of one model is tested, a large bottom plate is required to be drawn, and a plurality of chips are welded.
At present, only a small test daughter board needs to be replaced, and it can be understood that the main categories of the microprocessor chip are 48 pins, 64 pins, 100 pins and 144 pins, so that the number of the daughter boards is not too large, a plurality of test daughter boards can achieve the test purpose by matching with a fixed bottom test board, and the difficulty and the period of test development are reduced.
As an exemplary embodiment, as shown in fig. 2 to 5, the test sub-board is a first PCB substrate, and includes an upper surface and a lower surface opposite to each other, where the upper surface is provided with a test socket capable of fixing a microprocessor chip to be tested, and the lower surface is provided with an euro-type connector plug; the test base plate is a second PCB substrate, and the upper surface of the second PCB substrate is provided with an European connector socket matched with the European connector plug on the first PCB substrate; the second PCB substrate is provided with a plurality of connecting holes, and the lower surface of the second PCB substrate is provided with a pogo pin connector; the resource leading-out board is a third PCB substrate, a plurality of connecting holes are formed in the third PCB substrate and correspond to the connecting holes in the second PCB substrate one by one, and the third PCB substrate is detachably connected with the second PCB substrate through connecting pieces; the third PCB substrate comprises an upper surface and a lower surface which are opposite, the upper surface comprises a pogo pin connection area matched with a pogo pin connector on the second PCB substrate, and the lower surface is connected with the T800 digital test machine;
further explaining how three PCB substrates are connected, namely a first PCB substrate, a second PCB substrate and a third PCB substrate from top to bottom, wherein the first PCB substrate and the second PCB substrate are specially designed for realizing the purpose of the scheme, and the first PCB substrate and the second PCB substrate are designed to realize that microprocessor chips with different types to be tested only need to be replaced by different test sub-boards, so that the difficulty and period of test development are reduced; because of the chip characteristics on the second PCB substrate, the test base plate of the scheme accommodates 176 pins at most; the third PCB substrate is a resource extraction board provided on a T800 digital test machine, wherein the T800 digital test machine is an existing product and is provided by Beijing Yue core; the test bottom plate of this scheme is just to T800 digital test board one-to-one design.
When the first PCB substrate and the second PCB substrate are specifically designed, only the above purpose needs to be met, for example, it may be designed as follows:
the upper surface core of the test sub-board, namely the first PCB substrate comprises a test seat, a resistor and an LED lamp, and the lower surface core comprises an 8MHz crystal oscillator, a 32.768KHz crystal oscillator, a resistor, a capacitor and a relay;
the upper surface core of the test bottom plate, namely the second PCB substrate, comprises an STM32F407ZET6 chip, an 8MHz crystal oscillator, a 32.768KHz crystal oscillator, a USB connector, a resistor and an LED lamp; the lower surface core comprises a CH340C chip, a TJA1050 chip, a relay, a resistor, a capacitor, an 8MHz crystal oscillator and a 32.768KHz crystal oscillator;
the test seat has the functions of: placing a microprocessor chip to be tested;
the resistor comprises a pull-up resistor, a pull-down resistor and a current limiting resistor, wherein the pull-up resistor is a resistor connected in series between a power supply voltage and a pin, and the state of the current pin defaults to 1; the pull-down resistor is a resistor connected in series between the ground and the pin, and the state of the current pin defaults to 0; the current limiting resistor is a resistor connected in series between the power supply voltage and the LED, so that the current flowing through the LED is reduced, and the LED is prevented from being burnt out due to overlarge current;
the capacitor comprises a filter capacitor and an energy storage capacitor, wherein the filter capacitor is as follows: clutter on the power supply voltage is filtered, so that the power supply voltage is kept in a stable state, and a filter capacitor is required to be connected in parallel at a power supply pin. Energy storage capacitor: when the load current of the chip suddenly increases, the power supply current also suddenly increases, and in order to prevent the power supply voltage from suddenly and suddenly decreasing at this time, an energy storage capacitor needs to be connected in parallel at the power supply pin. The method comprises the steps of carrying out a first treatment on the surface of the
The LED lamp has the following functions: displaying the switch state of the relay;
the 8MHz crystal oscillator has the following functions: providing an external high-speed clock reference for the microprocessor chip;
the 32.768KHz crystal oscillator has the following functions: providing an external low-speed clock reference for the microprocessor chip;
the relay has the functions that: and controlling connection and disconnection between the pins of the microprocessor chip to be tested and the pins of the auxiliary test microprocessor chip, and controlling connection and disconnection between the crystal oscillator and the pins of the microprocessor chip to be tested.
The STM32F407ZET6 chip has the following functions: as an auxiliary test microprocessor chip, the communication test is carried out between the auxiliary test microprocessor chip and the microprocessor chip to be tested;
the USB connector has the functions of: the test base plate is connected with the T800 digital test machine through a data line, and is used for data connection between the microprocessor chip to be tested and the processing terminal of the T800 digital test machine, so that the purposes of automatic downloading and communication of the test program are realized;
the CH340C chip has the following functions: converting the USB signal into a serial port signal;
the TJA1050 chip functions as: as a bus between 2 CAN communications.
As an alternative embodiment, as shown in fig. 1: the test seat comprises a fixed base 1 and a cover plate 2, wherein the upper surface of the fixed base 1 is provided with a containing cavity for placing a microprocessor chip to be tested, the cover plate 2 is hinged with the fixed base, the test seat is integrally placed on a test daughter board, the specific position can be placed in the middle, and European connectors are uniformly arranged around the test seat as the center, so that the test daughter board and the test bottom plate can be connected more firmly;
from the structural point of view, the cover plate 2 rotates on the fixed base 1 around the hinge, can close and fix the base 1 when testing is needed, and can open and fix the base 1 when the microprocessor chip to be tested needs to be replaced.
In summary, the shape of the test socket is changed at any time as long as the purpose of fixing the microprocessor chip to be tested on the test base plate can be achieved.
As an implementation manner, the dc parameters include an input high-level voltage threshold VIH, an input low-level voltage threshold VIL, an output high-level voltage value VOH, an output low-level voltage value VOL, a PULL-up resistance value PULL-up-resistance, a PULL-DOWN resistance value PULL-DOWN-resistance, a dc parameter in the analog-to-digital converter ADC, a dc parameter in the digital-to-analog converter DAC, and an operating current PWR in various modes.
The ac parameters include ac parameters in the high-speed external clock signal HSE, the low-speed external clock signal LSE, the high-speed internal clock signal HSI, the low-speed internal clock signal LSI, the TIMER, and ac parameters in the watchdog WDG.
The chip functions include Boot loader, CAN communication, I2C communication, SPI communication, USART/UART communication, a random number generator RNG and a Cyclic Redundancy Check (CRC).
It will be appreciated that the dc parameter class, ac parameter class and chip function class are all mentioned in the data manual of most chips in the industry, and that this solution also collects these specific data.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (8)

1. The utility model provides a general testing arrangement of microprocessor chip which characterized in that includes test daughter board, test bottom plate and T800 digital test board, wherein:
the test sub-board is in a multi-mode shape, each mode comprises a test seat, and each test seat can be matched with a group of microprocessor chips to be tested, the pins of which are the same in number; fixing the microprocessor chip to be tested through the test seat on the test daughter board, and connecting pins of the microprocessor chip to be tested to the test bottom plate;
the upper part of the test bottom plate is connected with the test daughter board, the lower part of the test bottom plate is connected with the resource extraction plate of the T800 digital test machine, and the test bottom plate comprises 176 pin resources which are arranged according to the pin distribution rule of the STM32F407IGTX chip and are extracted and connected to the resource extraction plate of the T800 digital test machine; the resource leading-out board leads out the test resources of the T800 digital test machine;
the T800 digital test machine is communicated with the microprocessor chip to be tested by using a serial port, and the serial port can automatically download a test program and an erase program to test the direct current parameter, the alternating current parameter and the chip function of the microprocessor chip to be tested.
2. The apparatus of claim 1, wherein the test sub-board is a first PCB substrate and comprises an upper surface and a lower surface opposite to each other, the upper surface is provided with a test socket for fixing a microprocessor chip to be tested, and the lower surface is provided with an euro-type connector plug.
3. The device according to claim 2, wherein the test socket comprises a fixed base (1) and a cover plate (2), the upper surface of the fixed base (1) is provided with a containing cavity for placing a microprocessor chip to be tested, and the cover plate (2) is hinged with the fixed base.
4. The apparatus of claim 2, wherein the test base is a second PCB substrate having an upper surface provided with an euro-type connector receptacle that mates with an euro-type connector plug on the first PCB substrate;
the second PCB substrate is provided with a plurality of connecting holes, and the lower surface of the second PCB substrate is provided with a pogo pin connector.
5. The device of claim 4, wherein the resource extraction board is a third PCB substrate, a plurality of connection holes are formed in the third PCB substrate and correspond to the connection holes in the second PCB substrate one by one, and the third PCB substrate and the second PCB substrate are detachably connected through a connecting piece;
the third PCB substrate comprises an upper surface and a lower surface which are opposite, the upper surface comprises a pogo pin connection area matched with the pogo pin connector on the second PCB substrate, and the lower surface is connected with the T800 digital test machine.
6. The apparatus of claim 1, wherein the dc parameters comprise an input high voltage threshold VIH, an input low voltage threshold VIL, an output high voltage value VOH, an output low voltage value VOL, a PULL-up resistance value PULL-up-resistance, a PULL-DOWN resistance value PULL-DOWN-resistance, a dc parameter in an analog-to-digital converter ADC, a dc parameter in a digital-to-analog converter DAC, and an operating current PWR in various modes.
7. The apparatus of claim 1, wherein the ac parameters comprise ac parameters in a high speed external clock signal HSE, a low speed external clock signal LSE, a high speed internal clock signal HSI, a low speed internal clock signal LSI, a TIMER, and ac parameters in a watchdog WDG.
8. The apparatus of claim 1 wherein the chip functions include Boot loader, CAN communication, I2C communication, SPI communication, USART/UART communication, random number generator RNG, and cyclic redundancy check, CRC.
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CN116026232A (en) * 2023-02-21 2023-04-28 北京京瀚禹电子工程技术有限公司 Giant magnetoresistance angle sensor test system based on singlechip and ATE
CN116580757A (en) * 2023-07-12 2023-08-11 悦芯科技股份有限公司 Virtual ATE test method and system

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