CN117632084A - Large integer power modular rapid computing method and system based on three-value optical processor - Google Patents
Large integer power modular rapid computing method and system based on three-value optical processor Download PDFInfo
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Abstract
The invention provides a large integer power modular rapid computing method and system based on a three-value optical processor, the method comprises the steps of setting modular condition large integer modular asWill beZero padding to AND is started at the rightmost end of the frameIs equal in number of bits toAndsending the obtained product into a three-value optical computer mold extractor for mold extraction to obtain a mold extraction resultOrder-makingWill beAnd (3) withRepeating the zero padding and the modulus taking operations to obtain a modulus taking resultRe-orderAnd recordThen let the following stepsAnd so on untilThe cyclic period is s, and the result is obtained by expanding n bits according to the bit number of b and the periodAccording to the cycle number s, willAndsplit intoA block to be splitAndandsubstitution into correspondingParallel computation is carried out in a three-value optical computer fast power modulo device, and the obtained modulo results are respectivelyAnd then willSubstituting into a three-value optical computer parallel multiplication modulus taker to obtain a final result。
Description
Technical Field
The invention belongs to the technical field of ternary optical computers, and particularly relates to a large integer power modulus rapid computing method and system based on a ternary optical processor.
Background
At the current stage, the main difficulty faced by the traditional electronic computer for performing large integer power modular computation is the rapid increase of the computational complexity, and along with the increase of the exponent size, the time and the computational resources required for computation increase exponentially. This exponential growth stage makes it difficult to rapidly handle large integer power modulo in practical applications, limiting computational efficiency and practicality.
The three-value optical computer is a photoelectric hybrid computer using a mature liquid crystal technology, and an MSD representation method is applied in combination with a light state. Three-value optical computers have been developed for twenty years, which can maintain excellent performance of processing mass data with high parallelism at extremely low power consumption, and which are constantly playing their great advantages.
Although three-value optical computers possess powerful computational power, there is still a lack of effective solutions in three-value optical computers to address the problem of rapid expansion of data due to exponential growth in large integer power modulo calculations. This problem makes us still problematic in dealing with complex computing processes, thereby limiting the application of this technology in this field.
Disclosure of Invention
In view of the above, the present invention is directed to a method and a system for fast computing a large integer power modulus based on a three-value optical processor, so as to solve the above-mentioned problems.
The invention provides a rapid calculation method for big integer power modulus based on a three-value optical processor, which comprises the following steps:
step 1, setting a mode taking condition large integer mode taking as mode takingWherein->，，/>And n is>m；
Step 2, willTo zero padding and +.>Equal number of bits, i.e->Will beAnd->Sending the obtained product into a three-value optical computer mold extractor for mold extraction to obtain a mold extraction result +.>；
Step 3, orderWill->And->Repeating step 2 to obtain the modulo result +.>Let->And record +.>Then let->And so on until ++>The cyclic period is s, and n bits are extended according to the number of bits and the period of b to obtain a result ∈>；
Step 4, according to the cycle period sAnd->Split intoBlocks, i.e.)>In the same way, the device can be used for the treatment of the heart failure,split +.>And->Andsubstitution of the corresponding +.>Parallel computation is carried out in a rapid power modular exponentiation device of a three-value optical computer, and the obtained modular exponentiation results are +.>Then->Substituting into a three-value optical computer parallel multiplication modular extractor to obtain a final result +.>。
The invention also provides a rapid computing system based on the large integer power modulus of the three-value optical processor, the system applies the rapid computing method based on the large integer power modulus of the three-value optical processor, and the system comprises:
the parameter setting module is used for:
setting the modulus taking condition as a large integer modulus takingWherein->，，/>And n is>m；
The three-value optical computer module is used for:
will beTo zero padding and +.>Equal number of bits, i.e->Will be，/>Feeding into MSD mold extractor for mold extraction to obtain mold extraction result +.>；
Order theWill->And->Repeating the zero filling and the modulus taking operations to obtain a modulus taking result +.>Re-orderAnd record +.>Then let->And so on until ++>The cyclic period is s, and n bits are extended according to the number of bits and the period of b to obtain a result ∈>；
The three-value optical computer rapid power modulus module is used for:
according to cycle periodThe period number s, willAnd->Split into->Blocks, i.e.)>In the same way, the device can be used for the treatment of the heart failure,split +.>And-> And->Substitution of the corresponding +.>Parallel computation is carried out in a rapid power modular exponentiation device of a three-value optical computer, and the obtained modular exponentiation results are +.>；
And the three-value optical computer parallel multiplication modulus taking module is used for:
and then will beSubstituting into a three-value optical computer parallel multiplication modular extractor to obtain a final result +.>。
Compared with the prior art, the invention has the following beneficial effects:
firstly, constructing a three-value optical computer modulus taker by utilizing a three-value optical path structure and an MSD multiplier, and then obtaining the minimum cycle period according to regular iterationThe big integer exponentiation modulus calculation is disassembled into +.>Block and bring the result +.>And the three-value optical computer fast power modulo device carries out parallel calculation. Thereby subtly converting the exponential growth problem into a series of specific modulo operations and multiplication operations. At the same time, it takes care of +.>Too large a number of simplest MSDs results in insufficient data bits, and too many parallel multiplications of multiple bits can result in challenges with too large a number of bit requirements, and multiple modules split for periodicity of data.
The whole calculation process is simple and easy to implement, and the calculation process is only required to be executed according to specified operation steps. Increasing the number of data bits only causes an increase in the number of modules and an increase in the number of basic operations, without increasing the complexity of the calculation process.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a flow chart of a fast calculation method based on large integer power modulo a three-valued optical processor of the present invention;
FIG. 2 is a schematic diagram of the optical path structure of the redundancy judging device of the present invention;
FIG. 3 is an optical path structure of the misalignment detector of the invention;
FIG. 4 is a basic frame diagram of a three-value optical computer modular extractor of the present invention;
FIG. 5 is a diagram showing the construction of an optical path of an n-bit G-determiner of the present invention
FIG. 6 is a basic frame diagram of a three-value optical computer fast power modulo device of the present invention;
FIG. 7 is a schematic diagram of a three-value optical computer parallel multiplication modulo device of the present invention;
FIG. 8 is a block diagram of a fast computing system based on large integer power modulo a ternary optical processor in accordance with the present invention;
in the figure, h1, h2, second, H3., fourth, fifth, sixth, H7., seventh, eighth, ninth, h10, tenth, h11, eleventh, h12, twelfth, h13, thirteenth, h14, fourteen, h15, fifteen, h16, sixteenth, h17, seventeen, eighteen, and nineteenth;
v1, v2, second, V3., third, V4., fourth, V5., fifth, V6., sixth, V7., seventh, V8., eighth, V9., ninth, v10, tenth, v11, eleventh, v12, twelfth, v13, thirteenth, v14, fourteen, v15, fifteen;
LC1, LC2, LC3, LCIII, LC4, LCIV, LC5, LCfive, LC6, LCsix, LC7, LC8, eight;
lcv1, lcv2, lcv3, lcv4, lcv5, lcv five, lcv6, lcv six, lcv7, lcv seven, lcv8, lcv eight, lcv9, lcv10, lcv ten, lcv11, lcv eleven.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
These and other aspects of embodiments of the invention will be apparent from and elucidated with reference to the description and drawings described hereinafter. In the description and drawings, particular implementations of embodiments of the invention are disclosed in detail as being indicative of some of the ways in which the principles of embodiments of the invention may be employed, but it is understood that the scope of the embodiments of the invention is not limited correspondingly.
Referring to fig. 1, the embodiment of the invention provides a fast calculation method based on big integer power modulo of a three-valued optical processor, comprising the following steps:
step 1, setting a mode taking condition large integer mode taking as mode takingWherein->，，/>And n is>m；
Step 2, willTo zero padding and +.>Equal number of bits, i.e->Will beAnd->Sending the obtained product into a three-value optical computer mold extractor for mold extraction to obtain a mold extraction result +.>；
Referring to fig. 4 to 5, further, in the step 2, the following steps are performedAndsending the obtained product into a three-value optical computer mold extractor for mold extraction to obtain a mold extraction result +.>The method of (1) comprises the following steps:
the three-value optical computer modulus taker comprises an n-bit G judgment device, two n-bit one-step MSD adders, two n-bit M transposition operators and a signal manager,
will beAnd->The data is sent to a G judging device to be compared according to the bit whether a is larger than c,
if a is greater than c, sending a signal to one of the M transpose operators through the signal manager to perform inverting operation so that the inverting operation of c becomes-c;
if a is smaller than c, the signal manager sends a signal to another M transpose operator, and the M transpose operator is used to perform zero padding operation in front of c, namelyThen performing the reversing operation;
will beAnd->Is input into one of the one-step MSD adders together to obtain an intermediate result +.>The method comprises the steps of carrying out a first treatment on the surface of the And then->Continuing the next round of calculation until the result +.>Obtaining the modulo result->。
The light from the three-value optical computer mode extractor can be used as the input light state again in the next calculation, until the light state is unchanged, the final result can be output.
In the one-step MSD adder, two light states are needed for input, the inversion of the two front sides is used for controlling the two alternative light states by comparing the results, so that only one light state is output, and when the one-step MSD adder does not receive the other light state, the result is not output.
The three-value optical computer modulus taker of the present embodiment is according to the formulaWherein->. Based on the theory, the complex problems are continuously subjected to exponential simplification to realize modulo calculation. By skillfully adopting the back-end 0 supplementing operation, 2 is subtracted from a at one time n And c, the calculation is convenient to a certain extent.
Further, in the step 2, when the zero padding operation is performed, it is necessary to first perform the zero padding operation、/>Respectively converted into MSD numbers.
Further, in the step 2, inThe right-most operation of (c) is to make up 0 by adding 0 at the lowest bit of c, the 0 at the lowest bit is realized by adding no-light data bit at the lowest bit of data, the zero-filling operation is to make up 0 at the highest bit of c by using M transposition operator before c, and the 0 at the highest bit is realized by adding no-light data bit at the highest bit.
Step 3, orderWill->And->Repeating step 2 to obtain the modulo result +.>Let->And record +.>Then let->And so on until ++>The cyclic period is s, and n bits are extended according to the number of bits and the period of b to obtain a result ∈>；
Further, in the step 3, the n/s block module is input into a three-value optical computer fast power modulo device, and the n bits are accumulated through different MSD multipliers, the number of bits of the following MSD multiplier is gradually increased only by n bits, and if the number of bits is too large, the modulo device can be adopted in advance to simplify the number, and then the accumulation is continued.
Step 4, according to the cycle period sAnd->Split intoBlocks, i.e.)>In the same way, the device can be used for the treatment of the heart failure,split +.>And->Andsubstitution of the corresponding +.>Parallel computation is carried out in a rapid power modular exponentiation device of a three-value optical computer, and the obtained modular exponentiation results are +.>Then->Substituting into a three-value optical computer parallel multiplication modular extractor to obtain a final result +.>。
Further, in the step 4, the calculation process of the three-value optical computer fast power modulo device specifically includes the following steps:
will beAnd->Respectively sending the encoded signals to a simplest MSD encoding module to obtain encoding results>And->；
Will encode the resultAnd->Carrying the two corresponding coding results into corresponding MSD multipliers to carry out multiplication operation to obtain n multiplication results;
performing cumulative multiplication operation on the n multiplication results to obtain a final multiplication resultWill->Sending the code to the simplest MSD coding module for coding, and adding the coding result and multiplication result ++>Feeding into MSD mould extractor for mould extraction to obtain result +.>。
The three-value optical computer fast power modulo device of this embodiment is according to the following formula:
the derivation is performed as follows:
。
it can be seen from the derivation that the higher power can be converted stepwise to the lower power while the lower power is converted to the higher power. Can be deduced
（The superscript of a in a is MSD number, while the D sequence has a unique period s) designed according to the above theory, converting b into +.>According to the number n of bits converted into MSD number by b, expanding according to period to obtain ++>。
Can be divided into according to the minimum cycle number sA block. The disassembly principle is as follows:
length n +.>And->Disassembled into->Blocks, i.e. . Then carrying it into the assembly to perform a series of multiplication and modulus operations to obtain +.>. Finally letEnters a designed three-value optical computer parallel multiplication modular extractor, and after a series of multiplication modular extraction and multiplication modular extraction operations, the final result ∈can be obtained>。
Referring to fig. 6, further in the step 4, each of the three-value optical computer fast power modulo devices includes a number of MSD multipliers related to a minimum period s, and if s is an odd number, each of the three-value optical computer fast power modulo devices needs 3s-2 MSD multipliers, and if s is an even number, each of the three-value optical computer fast power modulo devices needs 3s-1 MSD multipliers.
Referring to fig. 7, in step 4, the modulus-taking result is further obtainedSubstituting into a three-value optical computer parallel multiplication modular extractor to obtain a final result +.>The method of (1) comprises the following steps:
will take the modulus resultInputting to a three-value optical computer parallel multiplication modular extractor and integrating the modular extractorFruit (herba Cichorii)>Dividing into two groups, respectively utilizing MSD multiplier to make multiplication operation so as to obtain two multiplication results, then respectively making said two multiplication results and +.>Coding result of->Performing modulo operation to obtain result multiplication and modulo again to obtain final result +.>。
Referring to fig. 2 to 3, the present embodiment also relates to a simplest MSD encoding module, and before this, the basic implementation of the method is first described.
MSD is a redundant counting method in which three counting symbols of 0,1 and u (representing-1) are used. Because of redundancy, a value in an MSD may have several representations. Given a decimal number X, the MSD expression is:
；
wherein,the value range of (1) is { u,0,1}, u representing-1; />It is explained that MSD is still a binary counting method. Due to the fact thereinThere are three different possible values, so there may be multiple different MSD representations for the same numerical MSD. For example:
however, in computation, the biggest obstacle to parallel addition is that the uncertainty of carry generation and carry transfer, symmetric MSD coding can eliminate continuous 1 s or continuous-1 s in data, so that addition of symmetric MSD numbers does not generate carry transfer, and then parallelization of addition of the symmetric MSD numbers is easy to achieve. However, in the symmetric MSD encoding, there is also a problem that a plurality of values converted from each other exist even after encoding by the number of symmetric MSDs, and there may be different symmetric MSD encoding corresponding to the same number in the encryption process. In order to solve this problem, the design herein proposes a simplest MSD code, which is the most specific one of the symmetrical MSD codes.
The simplest MSD coding module comprises a redundancy judging device for redundancy judgment and a dislocation detector for dislocation detection;
when the simplest MSD coding module codes, firstly, carrying out symmetrical MSD coding on MSD numbers;
inputting the MSD number after the symmetrical MSD coding into a redundancy judging device to detect whether 1u and u1 are contained, and if the MSD number does not contain 1u and u1, conforming to the simplest MSD coding result;
if the error detection unit comprises 1u and u1, redundancy judgment is carried out, and a redundancy judgment result is input to the dislocation detector;
detecting whether 1 or u appears in the redundancy judgment result by using a dislocation detector, and if 1 or u appears in the redundancy judgment result, performing coding processing on the MSD number after symmetrical MSD coding and the redundancy judgment result by using the dislocation detector so as to accord with the simplest MSD coding result;
if 1 or u does not appear in the redundancy judgment result, adding 0 before and after the MSD number after the symmetrical MSD coding, and then inputting the 0 into a redundancy judgment device to carry out redundancy judgment, wherein the two redundancy judgment results do not appear 1 or u, and the MSD number after the symmetrical MSD coding has passed the simplest MSD coding.
The design principle of the simplest MSD code is as follows:
in the simplest MSD symmetric coding, two key operation parts are provided, one is a redundancy judging device, and when the MSD number after symmetric MSD coding is required to be judged whether the MSD number is the simplest MSD coding or not. The main criterion is to check whether the MSD number contains 1u and u1. The redundancy determiner truth table is shown in table 1.
TABLE 1 truth table for redundancy judger
According to the reduced value design theory and the truth table shown in table 1, the optical path structure of the redundancy arbiter can be designed, as shown in fig. 2.
As shown in fig. 2, a and b are input light states, and are the symmetrical msd numbers to be determined, that is, the detection is performed in the manner of abs. When the inputs a, b are in the no light state, the output c is in the no light state. When the input b is in a vertical light state, b passes through the vertical polarizer V1 to the normally non-optically controlled liquid crystal unit LC1, if the input a is in a horizontal light state, a passes through the horizontal polarizer H1 to the optically controlled end of the normally non-optically controlled liquid crystal unit LC1, the input light source b deflects to the horizontal light state, b can pass through the horizontal polarizers three H3 to c, and the output c is in the horizontal light state. If the input a is in a vertical light state or a no light state, the a cannot pass through the horizontal polarizer one H1, the light control end of the liquid crystal unit one LC1 is not optically controlled to be in a no light state, the input light source b does not deflect, the b cannot pass through the horizontal polarizer three H3, and the output c is in a no light state.
Similarly, when the input a is in the horizontal light state, a passes through the horizontal polarizer II H2 to the liquid crystal cell II LC2 which is not optically controlled. When b is in a vertical light state, b reaches the light control end of the normally non-optically controlled liquid crystal unit II LC2 through the vertical polarizing plate II V2, the input light source a deflects to the vertical light state, and the output c is in the vertical light state after the input light source a passes through the normally non-optically controlled liquid crystal unit II LC2 and the vertical polarizing plates III V3 to C. If the input b is in a horizontal light state or a non-light state, b cannot pass through the vertical polarizer two V2, the light control end of the liquid crystal unit two LC2 is not optically controlled in a non-light state, the input light source a does not deflect, a cannot pass through the vertical polarizer three V3, and the output c is in a non-light state.
The other is a misalignment detector, and the initial state is detected in the manner of abab. For example, for 010u01u1001u, where there are 1u and u1, but the redundant portion 000u01 is missing in the result. To solve this problem, misalignment detection is required. First, the simplest symmetric MSD encoding is performed, and if 1 or u appears in the first detection, the encoding process is performed. If 1 or u does not appear in the first detection, a 0 is added before and after the detection, and then the detection is performed. If either 1 or u does not appear for both detections, this indicates that the MSD number has passed the simplest MSD encoding. Taking 010u01u1001u as an example, its simplest symmetric MSD code is 010u 010u 0001.
The dislocation detector truth table is shown in table 2.
TABLE 2 truth table for misalignment detectors
The optical path structure of the error bit detector can be designed according to the reduced value design theory and the truth table shown in table 2, as shown in fig. 3.
According to the double rotation reconstruction instruction rule and the truth table of the dislocation detector in the table 2, the processor reconstruction of the double rotation processor can be completed, and the simplest symmetrical MSD coding is realized. The specific reconstruction instructions are as follows: the W-ROU arithmetic reconstruction instruction is 00010100, the H-ROU arithmetic reconstruction instruction is 00001011, and the V-ROU arithmetic reconstruction instruction is 00000111. The optical path structure of the simplest symmetric MSD encoded three-row operator is shown in fig. 3.
When the MSD number after the symmetrical MSD coding and the redundancy judgment result are coded in the dislocation detector, the interaction process of each component in the dislocation detector is as follows:
as shown in fig. 3, a and b are input optical states, where a is the number of MSDs after symmetric MSD encoding, b is the redundancy determination result, where input a is the main optical path, and input b is the control optical path. The operation of the W-ROU arithmetic unit is two vertical polarizers, and when a is in a non-light state, the two vertical polarizers are input into the W-ROU arithmetic unit for operation. In order to realize the conversion from the non-light state to the light state, a conversion device is usually added in front of the W-ROU arithmetic unit to convert the non-light state into vertically polarized light and input the vertically polarized light to the W-ROU arithmetic unit for operation. Normally, at most one of the three row operators is in a light state output, and the other is in a no light state output. If two or more than two uplink operators are all light outputs in the same input, the output is illegal, and errors may occur in the calculation process.
From the above, it is apparent that when the input a is in the no light state, the output c is also in the no light state. When the input a is in the vertical light state, a reaches the normally optically controlled liquid crystal cell two LCv through the vertical polarizer six V6. When the input b is in a vertical light state, b cannot pass through the horizontal polarizer five H5, so that the light control end of the normally optically controlled liquid crystal unit two LCv is in a non-light state, so that a deflects to a horizontal light state, cannot pass through the vertical polarizer seven V7, and the output c is in a non-light state. On the contrary, when the vertical light state of b is input, b reaches the light control end of the normally optically controlled liquid crystal unit II LCv through the horizontal polarizer five H5, so a is not deflected and still is in the vertical light state, and reaches c through the vertical polarizer seven V7 and the normally optically controlled liquid crystal unit four LC4, and is output as the vertical light state. Similarly, when input a is in the horizontal light state, a passes through the horizontal polarizer six H6 to reach the normally optically controlled liquid crystal cell three LCv. When the input b is in a horizontal light state, b cannot pass through V8, so the light control end of the normally optically controlled liquid crystal cell three LCv is in a non-light state, so a deflects to a vertical light state, cannot pass through the horizontal polarizer seven H7, and the output c is in a non-light state. On the contrary, when the input b is in a horizontal light state, b reaches the light control end of the normally optically controlled liquid crystal cell III LCv through the vertical polarizer eight V8, so a does not deflect, and reaches c through the horizontal polarizer seven H7 and the normally optically controlled liquid crystal cell four LCv, and the output is in a horizontal light state.
The rapid calculation method based on the large integer power modulus of the three-value optical processor provided by the embodiment utilizes the characteristics of the giant number and the reconfigurability of the three-value optical processor with a double-rotation structure, and combines a one-step adder and an MSD multiplier to design and realize the rapid calculation method of the large integer power modulus.
Further, the three-value optical computer mode extractor is topologically consistent with the MSD mode extractor.
Referring to fig. 8, an embodiment of the present invention provides a fast computing system based on big integer power modulo of a three-value optical processor, where the system applies the above fast computing method based on big integer power modulo of a three-value optical processor, and the system includes:
the parameter setting module is used for:
setting the modulus taking condition as a large integer modulus takingWherein->，，/>And n is>m；
The three-value optical computer module is used for:
will beTo zero padding and +.>Equal number of bits, i.e->Will be，/>Feeding into MSD mold extractor for mold extraction to obtain mold extraction result +.>；
Order theWill->And->Repeating the zero filling and the modulus taking operations to obtain a modulus taking result +.>Re-orderAnd record +.>Then let->And so on until ++>The cyclic period is s, and n bits are extended according to the number of bits and the period of b to obtain a result ∈>；
The three-value optical computer rapid power modulus module is used for:
according to the cycle number sAnd->Split into->Blocks, i.e.)>In the same way, the device can be used for the treatment of the heart failure,split +.>And->Andsubstitution of the corresponding +.>Parallel computation is carried out in a rapid power modular exponentiation device of a three-value optical computer, and the obtained modular exponentiation results are +.>；
And the three-value optical computer parallel multiplication modulus taking module is used for:
and then will beSubstituting into a three-value optical computer parallel multiplication modular extractor to obtain a final result +.>。
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (9)
1. A method for fast calculation of large integer power modulo based on a three-valued optical processor, the method comprising the steps of:
step 1, setting a mode taking condition large integer mode taking as mode takingWherein->，，/>And n is>m；
Step 2, willTo zero padding and +.>Equal number of bits, i.e->Will beAnd->Sending the obtained product into a three-value optical computer mold extractor for mold extraction to obtain a mold extraction result +.>；
Step 3, orderWill->And->Repeating step 2 to obtain the modulo result +.>Let->And record +.>Then let->And so on until ++>The cyclic period is s, and n bits are extended according to the number of bits and the period of b to obtain a result ∈>；
Step 4, according to the cycle period sAnd->Split into->Blocks, i.e.)>In the same way, the device can be used for the treatment of the heart failure,split the product/>And->Andsubstitution of the corresponding +.>Parallel computation is carried out in a rapid power modular exponentiation device of a three-value optical computer, and the obtained modular exponentiation results are +.>Then->Substituting into a three-value optical computer parallel multiplication modular extractor to obtain a final result +.>。
2. The method of fast calculation of large integer power modulo based on three value optical processor according to claim 1, wherein in step 2, the method of fast calculation of large integer power modulo based on three value optical processor is performed byAnd->Sending the obtained product into a three-value optical computer mold extractor for mold extraction to obtain a mold extraction result +.>The method of (1) comprises the following steps:
the three-value optical computer modulus taker comprises an n-bit G judgment device, two n-bit one-step MSD adders, two n-bit M transposition operators and a signal manager,
will beAnd->The data is sent to a G judging device to be compared according to the bit whether a is larger than c,
if a is greater than c, sending a signal to one of the M transpose operators through the signal manager to perform inverting operation so that the inverting operation of c becomes-c;
if a is smaller than c, the signal manager sends a signal to another M transpose operator, and the M transpose operator is used to perform zero padding operation in front of c, namelyThen performing the reversing operation;
will beAnd->Is input into one of the one-step MSD adders together to obtain an intermediate result +.>The method comprises the steps of carrying out a first treatment on the surface of the And then->Continuing the next round of calculation until the result +.>Obtaining the modulo result->。
3. The large integer power based on three-valued optical processor as defined in claim 2The fast calculation method of the modulus is characterized in that in the step 2, when zero padding operation is carried out, the method needs to firstly carry out、/>Respectively converted into MSD numbers.
4. A method of fast calculation of large integer power modulo based on three value optical processor according to claim 3, wherein in said step 2, inThe right-most operation of (c) is to make up 0 by adding 0 at the lowest bit of c, the 0 at the lowest bit is realized by adding no-light data bit at the lowest bit of data, the zero-filling operation is to make up 0 at the highest bit of c by using M transposition operator before c, and the 0 at the highest bit is realized by adding no-light data bit at the highest bit.
5. The method for fast computing a large integer power modulo based on a three-valued optical processor according to claim 4, wherein in step 4, the computing process of the three-valued optical computer fast power modulo comprises the following steps:
will beAnd->Respectively sending the encoded signals to a simplest MSD encoding module to obtain encoding results>And->；
Will encode the resultAnd->Carrying the two corresponding coding results into corresponding MSD multipliers to carry out multiplication operation to obtain n multiplication results;
performing cumulative multiplication operation on the n multiplication results to obtain a final multiplication resultWill->Sending the code to the simplest MSD coding module for coding, and adding the coding result and multiplication result ++>Feeding into MSD mould extractor for mould extraction to obtain result +.>。
6. The method according to claim 5, wherein in the step 4, each of the three-value optical computer fast power modulo units includes a number of MSD multipliers related to a minimum period s, and if s is an odd number, each of the three-value optical computer fast power modulo units requires 3s-2 MSD multipliers, and if s is an even number, each of the three-value optical computer fast power modulo units requires 3s-1 MSD multipliers.
7. The method of fast calculation of large integer power modulo based on three value optical processor according to claim 6, wherein in said step 4, the modulo result is takenSubstituting into a three-value optical computer parallel multiplication modular extractor to obtain a final result +.>The method of (1) comprises the following steps:
will take the modulus resultInputting to a three-value optical computer parallel multiplication modulus taker, and taking modulus resultDividing into two groups, respectively utilizing MSD multiplier to make multiplication operation so as to obtain two multiplication results, then respectively making said two multiplication results and +.>Coding result of->Performing modulo operation to obtain result multiplication and modulo again to obtain final result +.>。
8. The method of claim 7, wherein the three-value optical computer modulo device and the MSD modulo device are topologically identical.
9. A ternary optical processor-based large integer power modulo fast calculation system, wherein the system applies the ternary optical processor-based large integer power modulo fast calculation method of any one of claims 1 to 8, the system comprising:
the parameter setting module is used for:
setting the modulus taking condition as a large integer modulus takingWherein->，，/>And n is>m；
The three-value optical computer module is used for:
will beTo zero padding and +.>Equal number of bits, i.e->Will be，/>Sending the mixture into an MSD (multi-stage digital) mold taking device for mold taking to obtain a mold taking result；
Order theWill->And->Repeating the zero filling and the modulus taking operations to obtain a modulus taking result +.>Let->And record +.>Then let->And so on until ++>The cyclic period is s, and n bits are extended according to the number of bits and the period of b to obtain a result ∈>；
The three-value optical computer rapid power modulus module is used for:
according to the cycle number sAnd->Split into->Blocks, i.e.In the same way, the device can be used for the treatment of the heart failure,split +.>And->Andsubstitution of the corresponding +.>Parallel computation is carried out in a rapid power modular exponentiation device of a three-value optical computer, and the obtained modular exponentiation results are +.>；
And the three-value optical computer parallel multiplication modulus taking module is used for:
and then will beSubstituting into a three-value optical computer parallel multiplication modular extractor to obtain a final result +.>。
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