CN109388372A - A kind of three value optical processor MSD multiplication calculation methods based on minimum module - Google Patents
A kind of three value optical processor MSD multiplication calculation methods based on minimum module Download PDFInfo
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- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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Abstract
The three value optical processor MSD multiplication calculation methods based on minimum module that the present invention provides a kind of, the present invention realize using three value optical computer of photoelectric hybrid as research/development platform and carry out Fast Multiplication operation on three value optical computers.This method disassembles the multiplication of two long numbers at multiple minimum modules, that is, four figures four figures multiplication, then restores its corresponding position in initial data by mending 0 operation, and long-number multiplication is dexterously converted to four figures multiplication and a series of additions.Entire calculating process only needs to carry out according to set operating procedure, and the data bit increase of data only increases the number of the minimum module reconstructed and the number of addition, and calculating process is will not to become complicated with the increase of data bits.
Description
Technical field
The present invention relates to three value optical computer technical fields, more particularly to a kind of three value optics based on minimum module
Processor MSD multiplication calculation method.
Background technique
Multiplying in conditional electronic computer is faced with the problems such as computational accuracy is low, delay is long.Multiplying is most
One of common basic operations, are widely used in the every field of engineering technology and scientific algorithm, are to influence to realize using algorithm
The critical path of efficiency.
Avizienis has been put forward for the first time MSD representation in 1961, and later Draker et al. is introduced into optical oomputing.
MSD is a kind of redundancy counting method, and 0,1 and u (indicating -1), three counting symbols are used in MSD counting method.
In the prior art, in three value optical processor MSD multipliers, there are calculating process can be with data bits
Increase and become complicated problem.
Summary of the invention
Present invention place against the above deficiency, proposes based on a kind of three value optical processor MSD multiplication by minimum module
Calculation method, to solve the problems, such as that calculating process can become complicated with the increase of data bits.
A kind of three value optical processor MSD multiplication calculation methods based on minimum module, comprising the following steps:
Step 1, by each y of B3, y2, y1, y0Generate one four auxiliary data Bj=yjyjyjyj, obtain four
New data B0, B1, B2, B3；
Step 2, by multiplier A=x3x2x1x0Copy 4 parts of four M arithmetic units being respectively fed in four minimum module optical paths
In, while by the B of multiplicand0, B1, B2, B3Also it is respectively fed in four M arithmetic units in four minimum module optical paths carry out with A
M transformation, obtains partial product P0, P1, P2, P3；
Step 3, by partial product P1It is moved to the left 1, P22 are moved to the left, P33 are moved to the left, P0It does not move, it is mobile
Sum number item S is just obtained after the completion0, S1, S2, S3；
It step 4, will be with several S0, S1, S2, S3It is sent into seven single step adders in four minimum module optical paths, nine
Add up in single step adder, obtain this four minimum modules as a result, as Fmin。
The three value optical processor MSD multiplication calculation methods based on minimum module provided according to the present invention, will be more than two
The multiplication of digit is disassembled into multiple minimum modules, that is, four figures × four figures multiplication, then restores it original by mending 0 operation
Corresponding position in data, is dexterously converted to four figures multiplication and a series of additions for long-number multiplication.Entire calculating process
It only needs to carry out according to set operating procedure, the data bit increase of data only increases the minimum module reconstructed
The number of number and addition, and calculating process is will not to become complicated with the increase of data bits.
The present invention designs the minimum module of MSD multiplier, i.e. four MSD multipliers first, then in minimum module
On the basis of, it is extended according to specific needs to realize multidigit multiplying.According to the sum of several numbers of distributive law of multiplication
When being multiplied with a number, first they can be multiplied with this number respectively, then product is added.It is again any one known to several expressions
Number is to be multiplied Quan Qiuhe by the number that it contains and obtained.The multiplication of long number can be expressed as to multiple lower-order digit multiplication accordingly, so
Its weight in initial data is restored by mending 0 in low level afterwards.As theoretical basis, three based on minimum module are designed
It is worth optical computer multiplier.Two numbers in multiplying are pressed four respectively to split for a basic unit, in multiplier
Each basic unit and each basic unit of multiplicand carry out the multiplying of four figures × four figures, obtain result it
Afterwards according to weight of two basic units in its initial data carry out mend 0 operation, then by it is all mend 0 after results added,
It can be obtained by the result of the multiplication of two long numbers.Then according to above-mentioned principle, there is following formula:
In addition, above-mentioned three value optical processor MSD multiplication calculation methods based on minimum module according to the present invention, may be used also
To have following additional technical characteristic:
Further, in step 3, to partial product carry out mend 0 operation come calculate with it is several.
Further, described to mend 0 operation by partial product piA high position or low level increase unglazed state data bit and realize.
Further, in step 4, by with it is several feeding four minimum module index paths in 11 single step additions
Device is added up to obtain final calculated result, S3, S2, S1, S0Four and it is several be pass through parallel computation simultaneously generation but position
Number is different, is sent into the not single step MSD adder of isotopic number when cumulative.
Further, step 4 specifically includes:
First by S0With S1It is sent into seven single step adders in four minimum module optical paths, S2With S3It is sent into four most
Parallel computation is carried out in nine single step adders in little module optical path, is as a result denoted as F'0, F'1, then by F'0Mend 40 in front
As F0, F'1It is F that front, which mends 20,1, finally data prediction in four minimum module optical paths is sent to using result as input
The input terminal of module is calculated, and output result is Fmin。
Additional aspect and advantage of the invention will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Fig. 1 is the basic framework figure of single step MSD adder；
Fig. 2 is the light channel structure figure of M arithmetic unit
Fig. 3 is four minimum module index paths；
Fig. 4 is the flow chart of expansion scheme；
Fig. 5 is specific cumulative process schematic diagram；
Label declaration in figure is as follows:
1,3,5,7,8 vertical polarizer；2 uncertain components；4,6 Chang Xuanguang electrically-controlled liquid crystal unit；9 control optical paths；10,
12,14 vertical polarizer；11,13,16,18 normal chiral liquid crystals；15,17 horizontal polarizer；19,20,21,22M arithmetic unit；23 7
Position single step adder；24 9 single step adders；250 one single step adders；26 data preprocessing modules；27,
28,29 minimum module；30,31,32,33,34,35,36,37,38,39 single step adder.
Specific embodiment
To facilitate the understanding of the present invention, a more comprehensive description of the invention is given in the following sections with reference to the relevant attached drawings.In attached drawing
Give several embodiments of the invention.But the invention can be realized in many different forms, however it is not limited to this paper institute
The embodiment of description.On the contrary, purpose of providing these embodiments is make it is more thorough and comprehensive to the disclosure.
Unless otherwise defined, all technical and scientific terms used herein and belong to technical field of the invention
The normally understood meaning of technical staff is identical.Term as used herein in the specification of the present invention is intended merely to description tool
The purpose of the embodiment of body, it is not intended that in the limitation present invention.Term " and or " used herein includes one or more phases
Any and all combinations of the listed item of pass.
The three value optical processor MSD multiplication calculation methods based on minimum module that the embodiment provides a kind of,
Before this, the basis of this method implementation is introduced first.
Due to the presence of redundancy, a numerical value in MSD may have several representations.A decimal number X is given,
MSD expression formula are as follows:
X=∑ixi×2i (1)
Wherein, xiCodomain be { u, 0,1 }, u indicate -1；2iIllustrate that MSD is still binary scale.Due to xiHave 3 can
Value then can have multiple MSD to indicate a numerical value, for example, having following different expressions for numerical value 7:
(7)10=(100u)MSD=(1u00u)MSD
Negative MSD indicates very simple, it is only necessary to which each by corresponding positive number negates.1 to negate be u, and it is 1,0 to take that u, which is negated,
Counter is 0.As long as therefore first doing a step-by-step inversion operation to subtrahend when making MSD subtraction, then continue according to MSD addition
?.The redundancy of MSD number representation is limited in the generated carry when carrying out add operation on two adjacent positions
Without generating carry propagation, the cascaded carry latency issue of optical addition device thus can solve
The working principle of single step MSD adder is as follows:
In calculating, the maximum obstacle of parallel addition is uncertainty (one that the generation of carry and carry are transmitted
The carry that lowest order generates under special circumstances can be for delivery to highest order), the essence of carry transmitting is because in operand
It is possible that coded combination as continuous 1 or continuous -1, for example, 011111 with 101111 and similar two
Operand carries out the transmitting that carry will be generated when addition.Symmetrical MSD coding can be eliminated continuous 1 or continuous in data
- 1, so the addition of symmetrical MSD number will not generate carry transmitting, then their addition is just easily achieved parallelization.Based on pair
The rule for claiming MSD number and being added two-by-two, can establish the truth table of single step MSD addition, as shown in table 1.
1 one step MSD addition truth table of table
In attached drawing 1,1,3,5,7,8 indicate vertical polarizer, and 4 and 6 indicate Chang Xuanguang electrically-controlled liquid crystal unit, and 2 be uncertain
Component.Part in dotted line frame is main optical path, and input includes a1And a2, they are adjacent two of arithmetic operation number a；Control
The input of optical path includes b1And b2, they are adjacent two of arithmetic operation number b.The part of red strokes and dots wire frame is birotation
Structure, it is a special case of birotation architecture logic arithmetic unit.
The working principle of MSD multiplication is as follows:
Input data is indicated with X and Y, if X there are m, Y has n≤m, and Y=yn yn-1……yi…y1, product F are as follows:
F=X × Y=∑iX×yi×2i=∑ipi×2i=∑isi；(i=1,2 ... ..., r) (2)
Wherein pi=X × yiReferred to as partial product, si=pi×2iReferred to as with it is several.
Due to yiValue be u, 0 and 1, so to X and yiCarrying out a simple three-valued logic operation can be obtained pi,
For discussion purposes, which is known as M operation.(1) factor 2 in formulaiIt determines to obtained piI is added below
A 0 obtains and several si, then to siSummation, just obtains product F.
The working principle of M arithmetic unit is as follows:
In MSD multiplier, there are two crucial arithmetic units, and one is single step MSD adder, the other is M is transported
Calculate device.The truth table of M arithmetic unit is as shown in table 2.
The truth table of table 2.M arithmetic unit
According to truth table shown in depreciation design theory and table 2, the light channel structure of M arithmetic unit can be designed that, it is such as attached
Shown in Fig. 2.
The three value optical processor MSD multiplication calculation methods provided in this embodiment based on minimum module utilize birotation knot
The huge digit of three value optical processor of structure and restructural feature have devised and embodied MSD multiplier in conjunction with single step adder
Minimum module.
Assume initially that the multiplier A=x in minimum module3x2x1x0, multiplicand B=y3y2y1y0, this method includes following step
It is rapid:
Step 1, by each y of B3, y2, y1, y0Generate one four auxiliary data Bj=yjyjyjyj, obtain four
New data B0, B1, B2, B3；
Step 2, by multiplier A=x3x2x1x0Copy 4 parts of four M arithmetic units being respectively fed in four minimum module optical paths
In (i.e. 19 in Fig. 3,20,21,22 4 M arithmetic units), while by the B of multiplicand0, B1, B2, B3Also four minimums are respectively fed to
M transformation is carried out with A in four M arithmetic units (i.e. 19 in Fig. 3,20,21,22 4 M arithmetic units) in module optical path, obtains part
Product P0, P1, P2, P3；
Step 3, by partial product P1It is moved to the left 1, P22 are moved to the left, P33 are moved to the left, P0It does not move, it is mobile
Sum number item S is just obtained after the completion0, S1, S2, S3；
It step 4, will be with several S0, S1, S2, S3Seven single step adders being sent into four minimum module optical paths (are schemed
Position single step adder 23 in 3), add up in nine single step adders (i.e. nine single step adders 24 in Fig. 3), obtain
To this four minimum modules as a result, as Fmin。
Wherein, in step 3, to partial product carry out mend 0 operation come calculate with it is several.It is described to mend 0 operation by part
Product piA high position or low level increase unglazed state data bit and realize.
In step 4, it will be carried out with 11 single step adders in four minimum module index paths of several feedings tired
Add to obtain final calculated result, S3, S2, S1, S0Four with it is several be pass through parallel computation and meanwhile generate but digit it is different,
It is sent into the not single step MSD adder of isotopic number when cumulative.Because that two n MSD numbers are added the result is that a n+2
Position MSD number, so needing to reconstruct 1 seven single step MSD adder, 23,1 nine single steps in four minimum modules
24,1 11 single step MSD adders 25 of MSD adder.Detailed process is that S0 and S1 is first sent into seven single step MSD
In adder 23, S2With S3It is sent into nine single step MSD adders 24 and carries out parallel computation, be as a result denoted as F'0, F'1, then will
F'0It is F that front, which mends 40,0, F'1It is F that front, which mends 20,1, finally data preprocessing module 26 is sent to using result as input
Input terminal calculated, output result be exactly Fmin, i.e. the final result of this minimum module.
Step 4 specifically includes:
First by S0With S1It is sent into seven single step adders (i.e. 25 in Fig. 3) in four minimum module optical paths, S2With
S3Parallel computation is carried out in nine single step adders being sent into four minimum module optical paths, is as a result denoted as F'0, F'1, then will
F'0It is F that front, which mends 40,0, F'1It is F that front, which mends 20,1, finally four minimum module optical paths are sent to using result as input
The input terminal of middle data preprocessing module is calculated, and output result is Fmin。
Attached drawing 4,5 is please referred to, spread step of the invention is as follows:
Step S1, data prediction, pretreatment operation by TOC task management software complete, by can operation data it is direct
It is sent into operation in multiplier, first by incoming multiplier A=An...Ai...A1With multiplicand B=Bm...Bi...B1(MSD number)
It is divided by four one group, mends 0 polishing four, and calculating group number in a high position when less than four, remember that the group number of multiplier is p,
The group number of multiplicand is q.
Step S2, minimum module reconstruct, according to step S1's as a result, being constructed simultaneously on three value optical computer processors
P × q four minimum modules out, i.e. minimum module 27, minimum module 28, the minimum module 29 of Fig. 4.
Step S3, data calculate, and the multiplier after division is passed to the processing of three value optical computers as input with multiplicand
In the minimum module that device reconstructs, parallel computation is carried out.It can be obtained by the defeated of all minimum modules in an execution cycle
Out as a result, total p × q is a as a result, the result of k-th of minimum module of note is F at this timemin(k)。
Step S4 mends 0, mends 0 number by group sequence in initial data of multiplier and multiplicand to determine, it is assumed that multiplier with
Multiplicand is i-th group and jth group respectively, then mending 0 number is (i+j-2) × 4, and the result after k-th of minimum module mends 0 is denoted as
F′min(k)。
Step S5, add up, it is cumulative then by single step MSD adder completion.P × q the result obtained after 0 being mended, which is sent into, to be added
The result of two adjacent minimum modules is assigned to operation in a single step MSD adder by musical instruments used in a Buddhist or Taoist mass, and operation result is denoted as
fi.The quantity of the single step MSD adder needed are as follows: need p × q/2 adder when p × q is even number；When p × q is surprise
(p × q-1)/2 adder is needed when number.
Then previous step is generatedIt is a and, i.e., it is totalA fi, as next column single step adder
Input, regard asTo addition operand, obtained after completing single step MSD additionIt is a and.
It repeats the above stepsIt is secondary, until acquiring F, that is, last output knot with a MSD adder
Fruit.Expansion scheme process, as shown in Figure 5.
In step s 4, it needs to carry out data to mend 0 operation, i.e., is added in the low level of the calculated result of each minimum module
The identical unglazed state w with 0 number of benefit completes to mend 0 operation with this.
As shown in Fig. 5, the completion that each column single step MSD adder can be parallel calculates, altogetherColumn
Single step MSD adder.
According to the three value optical processor MSD multiplication calculation methods provided in this embodiment based on minimum module, by two
The multiplication of long number is disassembled into multiple minimum modules, that is, four figures × four figures multiplication, then restores it in original by mending 0 operation
Corresponding position in beginning data, is dexterously converted to four figures multiplication and a series of additions for long-number multiplication.Entirely calculated
Journey only needs to carry out according to set operating procedure, and the data bit increase of data only increases the minimum module reconstructed
Number and addition number, and calculating process is will not to become complicated with the increase of data bits.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (5)
1. a kind of three value optical processor MSD multiplication calculation methods based on minimum module, which is characterized in that assuming that minimum module
In multiplier A=x3x2x1x0, multiplicand B=y3y2y1y0, method includes the following steps:
Step 1, by each y of B3, y2, y1, y0Generate one four auxiliary data Bj=yjyjyjyj, obtain four new numbers
According to B0, B1, B2, B3；
Step 2, by multiplier A=x3x2x1x0It copies in 4 parts of four M arithmetic units being respectively fed in four minimum module optical paths, together
When by the B of multiplicand0, B1, B2, B3Also it is respectively fed in four M arithmetic units in four minimum module optical paths carry out M change with A
It changes, obtains partial product P0, P1, P2, P3；
Step 3, by partial product P1It is moved to the left 1, P22 are moved to the left, P33 are moved to the left, P0It does not move, after the completion of mobile
Just obtain sum number item S0, S1, S2, S3；
It step 4, will be with several S0, S1, S2, S3Seven single step adders, nine steps being sent into four minimum module optical paths
Add up in formula adder, obtain this four minimum modules as a result, as Fmin。
2. the three value optical processor MSD multiplication calculation methods according to claim 1 based on minimum module, feature exist
In, in step 3, to partial product carry out mend 0 operation come calculate with it is several.
3. the three value optical processor MSD multiplication calculation methods according to claim 2 based on minimum module, feature exist
In described to mend 0 operation by partial product piA high position or low level increase unglazed state data bit and realize.
4. the three value optical processor MSD multiplication calculation methods according to claim 1 based on minimum module, feature exist
In, in step 4, will with it is several feeding four minimum module index paths in 11 single step adders be added up to obtain
Final calculated result, S3, S2, S1, S0Four with it is several be pass through parallel computation and meanwhile generate but digit it is different, adding up
When be sent into not in the single step MSD adder of isotopic number.
5. the three value optical processor MSD multiplication calculation methods according to claim 4 based on minimum module, feature exist
In step 4 specifically includes:
First by S0With S1It is sent into seven single step adders in four minimum module optical paths, S2With S3It is sent into four minimum modules
Parallel computation is carried out in nine single step adders in optical path, is as a result denoted as F'0, F'1, then by F'0It mends 40 front
F0, F'1It is F that front, which mends 20,1, finally data preprocessing module in four minimum module optical paths is sent to using result as input
Input terminal calculated, output result be Fmin。
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| CN117632084A (en) * | 2024-01-26 | 2024-03-01 | 华东交通大学 | Large integer power modular rapid computing method and system based on three-value optical processor |
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