CN117614458A - Conversion method and conversion circuit between different codes of finite state machine in RTL circuit - Google Patents
Conversion method and conversion circuit between different codes of finite state machine in RTL circuit Download PDFInfo
- Publication number
- CN117614458A CN117614458A CN202311614762.6A CN202311614762A CN117614458A CN 117614458 A CN117614458 A CN 117614458A CN 202311614762 A CN202311614762 A CN 202311614762A CN 117614458 A CN117614458 A CN 117614458A
- Authority
- CN
- China
- Prior art keywords
- binary
- code
- decoder
- codes
- finite state
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 32
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000004364 calculation method Methods 0.000 abstract description 6
- 238000012545 processing Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 7
- 238000010801 machine learning Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007418 data mining Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000012549 training Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/04—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being two
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Error Detection And Correction (AREA)
Abstract
The invention discloses a conversion method and a conversion circuit between different codes of a finite state machine in an RTL circuit, wherein the method comprises the following steps: determining the number of input/output ends of the single-heat codes; determining the corresponding binary coded coding bit number; compiling the input single thermal code into binary code through a first decoder group; transmitting the binary code to a second decoder group through a D-type trigger group; the second decoder bank compiles the binary code into one-hot code. The first decoder group compiles the single thermal code into binary code, the binary code after logic calculation is compiled into single thermal code by the second decoder group, discrete characteristic state output is realized, the input and output terminals of the conversion circuit before and after code conversion are kept unchanged, the discrete characteristics of the single thermal code are reserved, and the convenience of calculation and logic processing of the binary code is realized.
Description
Technical Field
The invention relates to the field of digital logic circuit design research, in particular to a conversion method and a conversion circuit between different codes of a finite state machine in an RTL circuit.
Background
In the design process of Resistor-Transistor Logic (RTL), it is an essential link to convert the RTL description of the circuit into a gate-level netlist. In the process of comprehensive conversion of the circuit, a comprehensive tool can select and modify the coding format of the finite state machine in the comprehensive process according to actual requirements. In formal verification, it is necessary to convert the codes of the finite state machines in RTL into the coding style modified by the synthesis tool.
The coding style of the finite state machine generally comprises single hot coding, binary coding and Gray coding. One common method of Encoding discrete features is One in which N states are encoded using N-bit state registers, each state having its own register bit, and only One of the bits is active at any time. The purpose of this is to convert the classification variables into digital representations that can be used for machine learning algorithm model training. In the fields of data mining and machine learning, it is very important to convert a classification variable into a numerical variable, which is one of the reasons why the single-hot coding is widely used.
However, the single-hot encoding has the defects that a large number of dimensions are increased due to the fact that one bit of the single-hot encoding is effective, the feature dimensions are sparse, useful information is scattered in a large amount of data, so that a large number of illegal states exist in the single-hot encoding, and the discrete features are unfavorable for a machine learning algorithm to calculate the distance.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method and circuit for converting between different codes of a finite state machine in an RTL circuit that is easy to calculate and simple and practical.
A method for converting between different encodings of a finite state machine in an RTL circuit, for converting a coding style of the finite state machine in the RTL circuit from a single thermal encoding to a binary encoding, the method comprising the steps of:
determining the number of input/output ends of the single-heat codes;
determining the corresponding binary coded coding bit number;
compiling the input single thermal code into binary code through a first decoder group;
transmitting the binary code to a second decoder group through a D-type trigger group;
the second decoder bank compiles the binary code into one-hot code.
Preferably, the first decoder group includes a plurality of first decoders, the first decoders are used for compiling the single thermal codes into binary codes, the number of the first decoders is the same as the number of coding bits of the binary codes, and the number of the input ends of each first decoder is the same as the number of the input ends of the single thermal codes.
Preferably, the second decoder set includes a plurality of second decoders, the second decoders are used for compiling binary codes into one-hot codes, the number of the second decoders is the same as the number of the output ends of the one-hot codes, and the number of the input ends of each second decoder is the same as the number of coding bits of the binary codes.
Preferably, the D-type flip-flop group includes a plurality of D-type flip-flops, the D-type flip-flop group is used for transmitting the binary code outputted from the first decoder group to the second decoder group, and the number of the D-type flip-flops is the same as the number of encoding bits of the binary code.
Preferably, the D-type flip-flop includes an address selection multiplexer, and an input signal of a control terminal of the address selection multiplexer is a valid signal of one-hot encoding.
Preferably, the step of determining the number of encoding bits of the corresponding binary code specifically includes:
determining the coding bit number of binary coding according to the coding bit number of the single-hot coding;
and determining a logic expression corresponding to each binary bit according to the binary coding rule.
And a conversion circuit between different codes of the finite state machine in the RTL circuit, which is used for realizing the conversion method between different codes of the finite state machine in the RTL circuit, so as to convert the coding style of the finite state machine in the RTL circuit from single-hot coding to binary coding, wherein the conversion circuit comprises an input terminal module, a first decoder group module, a D-type trigger group module, a second decoder group module and an output terminal module which are sequentially arranged,
the input terminal module is used for inputting the single-heat code;
the first decoder group module is used for compiling the one-hot code into binary code according to a logic expression;
the D-type trigger group module is used for transmitting binary codes;
the second decoder group module is used for compiling the binary code into the single-hot code according to the logic expression;
and the output terminal module is used for outputting the single-heat codes.
Preferably, the number of terminals in the input terminal module is the same as the number of terminals in the output terminal module and is consistent with the number of encoding bits of the one-hot encoding.
Preferably, the first decoder group module includes a plurality of first decoder circuits, the number of which is the same as the number of binary-coded bits; the second decoder group module comprises a plurality of second decoder circuits, and the number of the second decoder circuits is the same as the number of the encoding bits of the one-hot encoding.
Preferably, the D-type flip-flop group module includes a plurality of D-type flip-flop circuits, the number of the D-type flip-flop circuits being the same as the number of encoding bits of the binary code, each of the D-type flip-flop circuits including an address selection multiplexer circuit for signal validity selection at the time of binary code transmission.
In the conversion method and the conversion circuit between different codes of the finite state machine in the RTL circuit, the first decoder group compiles the single-hot code into the binary code, the binary code after logic calculation is compiled into the single-hot code by the second decoder group, discrete characteristic state output is realized, the input and output terminals of the conversion circuit before and after code conversion are kept unchanged, the discrete characteristics of the single-hot code are reserved, and the convenience of calculation and logic processing of the binary code is realized. The method is simple, easy to realize and convenient to popularize.
Drawings
FIG. 1 is a flow chart of a method for converting between different codes of a finite state machine in an RTL circuit according to an embodiment of the present invention.
Fig. 2 is a diagram showing correspondence between single hot codes and binary codes of a five-state finite state machine according to a first embodiment of the present invention.
Fig. 3 is a diagram showing correspondence between binary coded bits and one-hot coded bits of a five-state finite state machine according to the first embodiment of the present invention.
Fig. 4 is a truth table for the conversion of one-hot code to binary code for a five-state finite state machine according to a first embodiment of the present invention.
Fig. 5 is a schematic diagram of a connection relationship between a D-type flip-flop and an address selection multiplexer according to a first embodiment of the present invention.
Fig. 6 is a truth table for binary code to one-hot code conversion for a five-state finite state machine according to a first embodiment of the present invention.
Fig. 7 is a diagram showing correspondence between three-bit single-hot encoding and binary encoding according to the second embodiment of the present invention.
Fig. 8 is a simplified truth table of a decoder in the first decoder group according to the second embodiment of the present invention.
Fig. 9 is a simplified truth table two of decoders in the first decoder group according to the second embodiment of the present invention.
Fig. 10 is a simplified truth table of a decoder in a second decoder group according to a second embodiment of the present invention.
Fig. 11 is a simplified truth table two of decoders in the second decoder set according to the second embodiment of the present invention.
Fig. 12 is a simplified truth table three of decoders in the second decoder set according to the second embodiment of the present invention.
Fig. 13 is a schematic diagram of a circuit structure for converting three-bit one-hot code into binary code (original registers are not deleted) according to the second embodiment of the present invention.
Fig. 14 is a schematic diagram of a circuit configuration diagram for converting three-bit one-hot code into binary code (deleting an original register) according to the second embodiment of the present invention.
Detailed Description
In this embodiment, a method and a circuit for converting between different codes of a finite state machine in an RTL circuit are taken as an example, and the present invention will be described in detail with reference to specific embodiments and drawings.
Referring to fig. 1, a method for converting different codes of a finite state machine in an RTL circuit according to an embodiment of the present invention is used to convert a coding style of the finite state machine in the RTL circuit from a single thermal code to a binary code. Firstly, determining the number of input/output ends of the single-heat codes; determining the corresponding binary coded coding bit number; then, compiling the input single thermal code into binary code through a first decoder group; transmitting the binary code to a second decoder group through a D-type trigger group; the second decoder bank compiles the binary code into one-hot code.
The method specifically comprises the following steps:
step S10, determining the coding bit number of the single thermal coding.
Step S20, determining the corresponding binary coding bit number according to the single thermal coding bit number.
Specifically, step S20 further includes the following specific steps:
step S21, corresponding relation of each encoding bit of the binary encoding is determined according to the discrete features of the single thermal encoding.
Step S22, determining a truth table of each binary bit according to the rule of binary coding.
Specifically, the logic expression corresponding to each binary bit can be represented by a truth table to verify the accuracy of the logic expression.
Specifically, the method of converting the single thermal code into the binary code may refer to a conversion method of converting the decimal integer into the binary integer, that is, a "divide-by-2 remainder, reverse order arrangement" method.
Step S30, determining the logic expression of each corresponding binary coding bit according to the state codes of each state register of the single thermal codes.
In step S40, the input single thermal code is compiled into binary code by the first decoder group.
Specifically, the first decoder group includes a plurality of first decoders, the first decoders are used for compiling the single thermal codes into binary codes, the number of the first decoders is the same as the number of coding bits of the binary codes, and the number of input ends of each first decoder is the same as the number of input ends of the single thermal codes.
Step S50, the binary code is transmitted to the second decoder via the D-type flip-flop group.
Specifically, the second decoder set includes a plurality of second decoders, where the second decoders are used to encode binary codes into one-hot codes, the number of the second decoders is the same as the number of output ends of the one-hot codes, and the number of input ends of each second decoder is the same as the number of coding bits of the binary codes.
Specifically, the D-type flip-flop group includes a plurality of D-type flip-flops, the D-type flip-flop group is configured to transmit the binary code output from the first decoder group to the second decoder group, and the number of the D-type flip-flops is the same as the number of encoding bits of the binary code.
In particular, the D-type flip-flop group may be replaced by other logic circuits to realize corresponding logic functions, including, but not limited to, operations, comparison, storage, counting, timing control, and the like.
Preferably, the D-type flip-flop includes an address selection multiplexer, and an input signal of a control terminal of the address selection multiplexer is a valid signal of one-hot encoding.
Specifically, the address selection multiplexer outputs a valid address signal when each encoded bit of the one-hot encoding is valid and the output signal is a valid address signal.
In step S60, the second decoder group compiles the binary code into one-hot code.
In step S70, the output terminal of the second decoder group is connected to the output terminal of the one-hot encoding.
In the first embodiment, the description will be given taking, as an example, conversion of one-hot codes used by a finite state machine of five states into binary codes.
As shown in fig. 2, when the five-state finite state machine uses the one-hot encoding, the number of encoding bits is five, and after the binary encoding is used, the number of encoding bits is three. In an RTL circuit, the number of bits of state encoding for each finite state machine corresponds to one register. If one-hot encoding is used in the circuit, there will be five registers in the circuit representing values of different digits. The same applies to binary coding.
The correspondence of binary coded bits to single thermal coded bits is shown in fig. 3. The registers represented by the single thermal codes are respectively represented as OR4, OR3, OR2, OR1 and OR0 from the upper order to the lower order, and the registers represented by the binary codes are respectively represented as BR2, BR1 and BR0 from the upper order to the lower order. The method is characterized in that the single thermal code is converted into binary code in an RTL circuit, namely, each register is changed, firstly, the registers are provided with input and output ports, five registers are provided with five D-end input ports and five Q-end output ports, all the registers of the original code are deleted in the RTL circuit in the code conversion, the input and output ports of the original registers are reserved, and then the registers with the same number are created according to the converted coding bits. The input/output of the newly created register can then be determined by the original code and the converted code.
In this embodiment, the single thermal code is used as the original code, and the single thermal code needs to be converted into the binary code in the circuit. The D-terminal input ports of the registers OR4 to OR0 are denoted A, B, C, D, E. To determine the D-side input signal of BR2 when creating this register of BR2, five D-side input ports are required, which are reserved for the original five registers, and this can be achieved by encoding each state of the finite state machine of fig. 3. In states S3, S4, the BR2 register value in binary encoding is 1, which can be determined by the value of each bit of the encoding of S3, S4 in one-hot encoding, and a truth table can be formed, as shown in fig. 4.
The D-side input signal of the BR2 register may be determined according to the truth table as shown in equation (1),
（1）；
according to the expression, the connection mode of the S1 input signal in the circuit can be determined, and since the finite state machine has five states, only five effective values are input into the BR2 in the circuit, judgment is needed when the S1 is connected to the BR2, as shown in fig. 5, the D-type trigger is connected with the address selection multiplexer, and the control terminal T control signal of the address selection multiplexer is shown in the formula (2). When the value of T is 0, the input value of the D-type flip-flop is X, and when the value of T is 1, the input value of the D-type flip-flop is valid, and the input value is S1, as shown in fig. 5 below.
（2）；
Similarly, the methods for creating S2, S3 are the same.
When binary encoding is converted to one-hot encoding, the corresponding truth table is shown in fig. 6. From the truth table of fig. 6, five Q output signals are O1, O2, O3, O4, O5, respectively, while the Q outputs of the newly created registers are A, B, C, respectively. At this time, the three Q outputs of the newly created register are required to represent the five Q outputs of the original register, which is the same as when the D input is converted. In this case, when the O1 output signal held in the OR4 register is valid and the S4 state value is 1, the connection can be performed according to the expression (3).
（3）；
Similarly, effective output signals of other output ends can be obtained.
And a conversion circuit between different codes of the finite state machine in the RTL circuit, which is used for realizing the conversion method between different codes of the finite state machine in the RTL circuit, so as to convert the coding style of the finite state machine in the RTL circuit from single-hot coding to binary coding, wherein the conversion circuit comprises an input terminal module, a first decoder group module, a D-type trigger group module, a second decoder group module and an output terminal module which are sequentially arranged,
the input terminal module is used for inputting the single-heat code;
the first decoder group module is used for compiling the one-hot code into binary code according to a logic expression;
the D-type trigger group module is used for transmitting binary codes;
the second decoder group module is used for compiling the binary code into the single-hot code according to the logic expression;
and the output terminal module is used for outputting the single-heat codes.
Preferably, the number of terminals in the input terminal module is the same as the number of terminals in the output terminal module and is consistent with the number of encoding bits of the one-hot encoding.
Preferably, the first decoder group module includes a plurality of first decoder circuits, the number of which is the same as the number of binary-coded bits; the second decoder group module comprises a plurality of second decoder circuits, and the number of the second decoder circuits is the same as the number of the encoding bits of the one-hot encoding.
Preferably, the D-type flip-flop group module includes a plurality of D-type flip-flop circuits, the number of the D-type flip-flop circuits being the same as the number of encoding bits of the binary code, each of the D-type flip-flop circuits including an address selection multiplexer circuit for signal validity selection at the time of binary code transmission.
In a second embodiment, taking a circuit for converting three-bit single-hot code into binary code as an example, please refer to fig. 13 and 14.
Referring to fig. 7, a correspondence between three-bit single-hot encoding and binary encoding is shown, so that a simple truth table of two decoders in the first decoder group can be obtained, as shown in fig. 8 and 9. Similarly, the simple truth tables for the three decoders in the second decoder set for the inverse transform are shown in fig. 10, 11 and 12.
In the conversion method and the conversion circuit between different codes of the finite state machine in the RTL circuit, the first decoder group compiles the single-hot code into the binary code, the binary code after logic calculation is compiled into the single-hot code by the second decoder group, discrete characteristic state output is realized, the input and output terminals of the conversion circuit before and after code conversion are kept unchanged, the discrete characteristics of the single-hot code are reserved, and the convenience of calculation and logic processing of the binary code is realized. The method is simple, easy to realize and convenient to popularize.
It should be noted that the above-mentioned embodiments are merely preferred embodiments of the present invention, and are not intended to limit the present invention, but various modifications and variations of the present invention will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A method for converting between different encodings of a finite state machine in an RTL circuit, for converting a coding style of the finite state machine in the RTL circuit from a single thermal encoding to a binary encoding, the method comprising the steps of:
determining the number of input/output ends of the single-heat codes;
determining the corresponding binary coded coding bit number;
compiling the input single thermal code into binary code through a first decoder group;
transmitting the binary code to a second decoder group through a D-type trigger group;
the second decoder bank compiles the binary code into one-hot code.
2. The method of claim 1, wherein the first decoder set includes a plurality of first decoders, the first decoders are used for compiling the single thermal code into binary code, the number of the first decoders is the same as the number of the binary code, and the number of the input ends of each first decoder is the same as the number of the input ends of the single thermal code.
3. The method of switching between different codes of finite state machines in an RTL circuit according to claim 1, wherein the second decoder set includes a plurality of second decoders, the second decoders are used for compiling binary codes into one-hot codes, the number of the second decoders is the same as the number of output ends of the one-hot codes, and the number of input ends of each of the second decoders is the same as the number of coding bits of the binary codes.
4. The method of switching between different codes of a finite state machine in an RTL circuit according to claim 1, wherein the D-type flip-flop group includes a plurality of D-type flip-flops, the D-type flip-flop group is used for transmitting binary codes outputted from the first decoder group to the second decoder group, and the number of the D-type flip-flops is the same as the number of coding bits of the binary codes.
5. The method of switching between different codes of a finite state machine in an RTL circuit of claim 4, wherein the D-flip-flop comprises an address selection multiplexer, and wherein the input signal at the control terminal of the address selection multiplexer is a valid signal for one-hot coding.
6. The method for converting between different codes of finite state machines in an RTL circuit according to claim 1, wherein the step of determining the number of coding bits of the corresponding binary code specifically comprises:
determining the coding bit number of binary coding according to the coding bit number of the single-hot coding;
and determining a logic expression corresponding to each binary bit according to the binary coding rule.
7. A conversion circuit between different codes of a finite state machine in an RTL circuit, which is used for realizing the conversion method between different codes of the finite state machine in the RTL circuit according to any one of claims 1-6 so as to convert the coding style of the finite state machine in the RTL circuit from single thermal coding into binary coding, and is characterized by comprising an input terminal module, a first decoder group module, a D-type trigger group module, a second decoder group module and an output terminal module which are sequentially arranged in sequence,
the input terminal module is used for inputting the single-heat code;
the first decoder group module is used for compiling the one-hot code into binary code according to a logic expression;
the D-type trigger group module is used for transmitting binary codes;
the second decoder group module is used for compiling the binary code into the single-hot code according to the logic expression;
and the output terminal module is used for outputting the single-heat codes.
8. The switching circuit between different codes of a finite state machine in an RTL circuit according to claim 7, wherein the number of terminals in the input terminal block is the same as the number of terminals in the output terminal block and is consistent with the number of codes of a single thermal code.
9. The switching circuit between different encodings of a finite state machine in an RTL circuit as defined in claim 7, wherein the first decoder set module includes a plurality of first decoder circuits, the number of first decoder circuits being the same as the number of encoding bits of a binary encoding; the second decoder group module comprises a plurality of second decoder circuits, and the number of the second decoder circuits is the same as the number of the encoding bits of the one-hot encoding.
10. The switching circuit between different encodings of a finite state machine in an RTL circuit as defined in claim 7, wherein the D-type flip-flop group module comprises a plurality of D-type flip-flop circuits, the number of D-type flip-flop circuits being the same as the number of encoded bits of the binary code, each of the D-type flip-flop circuits comprising an address selection multiplexer circuit for signal validity selection during transmission of the binary code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311614762.6A CN117614458A (en) | 2023-11-29 | 2023-11-29 | Conversion method and conversion circuit between different codes of finite state machine in RTL circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311614762.6A CN117614458A (en) | 2023-11-29 | 2023-11-29 | Conversion method and conversion circuit between different codes of finite state machine in RTL circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117614458A true CN117614458A (en) | 2024-02-27 |
Family
ID=89955929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311614762.6A Pending CN117614458A (en) | 2023-11-29 | 2023-11-29 | Conversion method and conversion circuit between different codes of finite state machine in RTL circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117614458A (en) |
-
2023
- 2023-11-29 CN CN202311614762.6A patent/CN117614458A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| LEWIN | Design of logic systems | |
| CN112214349B (en) | Data cyclic redundancy check device and method | |
| CN108391129A (en) | Data-encoding scheme and device | |
| JPS63123232A (en) | Method of detecting single bit error and arithmetic decoder employing the same | |
| KR100282516B1 (en) | Convolutional code generator and digital signal processor | |
| US20040001014A1 (en) | Method and apparatus for generating gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO'S | |
| Stonham | Digital logic techniques | |
| US6370667B1 (en) | CRC operating calculating method and CRC operational calculation circuit | |
| CN117614458A (en) | Conversion method and conversion circuit between different codes of finite state machine in RTL circuit | |
| WO2024040892A1 (en) | Apparatus for converting binary code into thermometer code, and electronic device | |
| CN103607207A (en) | Plug-and-play multi-interface data compression apparatus | |
| CN103475379B (en) | A kind of LDPC coding method | |
| CN112953878B (en) | Construction method of n-dimensional time amplitude modulation signal permutation array constellation diagram and modulator | |
| CN100426219C (en) | Data operating method and apparatus in integrated circuit | |
| Sarkar et al. | The set of reversible 90150 cellular automata is regular | |
| CN103152059A (en) | Device and method of generating of constant coefficient matrix of radio sonde (RS) of consultative committee for space data system (CCSDS) | |
| CN106953643B (en) | Integrated circuit data decompression circuit and method of binary interval method | |
| CN107659315B (en) | Sparse binary coding circuit for compressed sensing | |
| CN105703783A (en) | LDPC coder with quasi-parallel structure | |
| CN110324045B (en) | Gray code construction method | |
| CN1752923B (en) | Mix Q disables, carry rows digital method, mix Q disables and Carry rows computer | |
| CN110515419B (en) | Device for realizing clock domain crossing by optimizing Gray code encoding mode | |
| CN208522727U (en) | Full parellel forward-backward recutrnce assembly line LDPC encoder | |
| CN218299677U (en) | Simple and easy intelligent dial switch of interface that can expand wantonly | |
| CN108683424B (en) | Full-parallel bidirectional recursion pipeline LDPC encoder and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |