CN117610494A - SOC chip performance verification method, system, equipment and storage medium - Google Patents
SOC chip performance verification method, system, equipment and storage medium Download PDFInfo
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Abstract
The invention discloses a method, a system, equipment and a storage medium for verifying performance of an SOC chip, and relates to the technical field of integrated circuit design. The method comprises the steps of: obtaining EDA simulation test case information of the DUT; based on the simulated stimulus test file of the test case, the test stimulus module applies test stimulus to the DUT; the test excitation module comprises a delay and bandwidth collector which is used for collecting delay values and bandwidth values of each module in the EDA simulation process and then adding the delay and bandwidth values into a preset module data transmission characteristic table; when the performance verification of the SOC chip is performed, the data path delay and the data path bandwidth of the IP module serving as the master are calculated based on the delay value and the bandwidth value of each IP module recorded in the module data transmission characteristic table. According to the invention, the delay and bandwidth information of the data path can be obtained without performing new EDA simulation, and the performance verification efficiency of the SOC chip is improved.
Description
Technical Field
The present invention relates to the field of integrated circuit design technologies, and in particular, to a method, a system, an apparatus, and a storage medium for verifying performance of an SOC chip.
Background
In the field of IC design, mainstream Chip designs are increasingly tending toward System On Chip (SOC) designs that use reusable IP blocks (i.e., intellectual Property core, also called IP cores). Common IP modules in SOC chip systems, such as CPU modules, DDR modules, USB modules, PCIE modules, etc. The SOC chip integrates the functional modules of the system into a chip and at least comprises a processor IP (or processor core), and a port IP module, a memory IP module, other IP modules and the like can be arranged according to the requirement. The system is internally communicated and controlled through an on-chip bus, and the on-chip bus is responsible for connecting each functional module in the system so that the functional modules can exchange data and share resources with each other.
In the design development process of the SOC chip, verification is needed before the SOC chip is put into use so as to ensure that the performance of the SOC can meet the design specification requirements in all aspects, and good performance and reliability are maintained under different working conditions. After the development of each IP module is completed, each module is integrated into the system for simulation, then performance verification is carried out, and if the performance characteristics do not meet the requirements, the system is modified. With the development of SOC chips toward higher integration level, larger regulation and more complex structure, more and more IP modules are integrated in the chip, and the chip performance verification work is particularly important, which is one of the determining factors for determining whether the chip can meet the actual requirements. The system performance of the SOC chip mainly includes the data path bandwidth and data path delay of each IP block, and the data path refers to a data transmission channel of data (or signal) in the SOC chip. Two important indicators are involved: path Bandwidth (Bandwidth) and path delay (Latency). The path bandwidth is the maximum rate at which data is transferred over the data path and represents the capacity of the data transfer within the SOC chip, typically measured in bits per second (i.e., bps). Higher channel bandwidth means that the chip can transfer data faster, thereby improving overall performance. The path delay is the time required for data transmission from one end to the other end on the data path, and reflects the speed of data transmission inside the chip, and the lower the path delay, the faster the data transmission inside the chip and the faster the system response speed.
Currently, the prior art also provides some data path calculation methods of SOC chip systems. For example, chinese patent application No. cn 2022106768222. X proposes a method for obtaining a delay value of a data path, which includes the steps of: determining a master device and a slave device corresponding to the master device in the SOC system; calling a delay test case, performing multiple access operations on the master device and each slave device based on a read/write data path between the master device and each slave device to perform a delay test so as to acquire a delay value of each access operation, wherein the access operation comprises a read operation/write operation; determining a first target delay value on each read data path based on the first delay value of the read operation on that read data path; a second target latency value on each write data path is determined based on the second latency value of the write operation on that write data path. According to the scheme, the target delay values corresponding to the accurate read operation and the accurate write operation are obtained by performing multiple access operations on the master device and the slave device to perform delay test, and particularly, the delay test is performed through single transmission. As for the calculation of the path bandwidth, it is also generally necessary to write a specific bandwidth test case and to perform EDA simulation based on the bandwidth test case, in which a large amount of data is transmitted and the transmission rate is measured. For example, a verifier may specify that an IP module sends 1000 transmissions as a master device in a bandwidth test case, and each transmission sends 1MByte of data, the total data to be transmitted is 1000 mbytes, and then analyzes the time taken for the IP module to send the 1000 mbytes by using waveforms shown in the EDA simulation result, for example, 5us (5 microseconds), and then the corresponding channel bandwidth is 1000M/5us, that is, the total data divided by the time taken for the data to be transmitted, so as to obtain the channel bandwidth of the IP module as the master device.
It can be seen that the above-mentioned existing verification scheme requires writing a special test case and running an EDA simulation based on the special test case, which occupies more human resources and computing resources, and affects the performance verification efficiency of the SOC chip. How to quickly and accurately acquire the data path bandwidth and the data path delay of the SOC chip is a technical problem to be solved currently.
Disclosure of Invention
The invention aims at: overcomes the defects of the prior art and provides a method, a system, equipment and a storage medium for verifying the performance of an SOC chip. According to the SOC chip performance verification scheme provided by the invention, the delay and bandwidth collector is arranged on the test excitation module of EDA simulation to collect the delay value and the bandwidth value of each IP module in the chip system in the EDA simulation process, the collected delay value and bandwidth value are added into the preset module data transmission characteristic table for recording, and then the channel bandwidth and the channel delay of the current main equipment end are calculated by reading the data in the module data transmission characteristic table when the SOC chip performance is verified, so that the delay and bandwidth information of a data channel can be obtained without performing new EDA simulation, and the writing of specific test cases for the IP module is not required, thereby improving the performance verification efficiency of the SOC chip.
In order to achieve the above object, the present invention provides the following technical solutions:
a SOC chip performance verification method comprises the following steps:
EDA simulation test case information for the DUT to be designed is obtained, and a corresponding simulation excitation test file is arranged corresponding to each test case; the DUT to be tested is correspondingly integrated with the SOC chip with a plurality of IP modules, and each IP module is connected through an on-chip bus;
based on the simulation excitation test file of the test case, the test excitation module applies test excitation to the DUT to be tested to perform EDA simulation; the test excitation module comprises a delay and bandwidth collector, wherein the delay and bandwidth collector is used for monitoring operation delay information and bandwidth information of each IP module in the chip system in an EDA simulation process, and adding the delay value and the bandwidth value of each IP module into a preset module data transmission characteristic table after obtaining the delay value and the bandwidth value of each IP module according to the monitored information;
and when the performance verification of the SOC chip is carried out, calculating the data path delay and the data path bandwidth of the IP module serving as the master equipment end master based on the delay value and the bandwidth value of each IP module recorded in the data transmission characteristic table of the module, wherein the data path delay value of the master equipment end master is accumulated as the delay value of the relevant module on the path of the current data path, and the data path bandwidth value of the master equipment end master is the bandwidth value of the bandwidth minimum module in the relevant module on the path of the current data path.
Further, the module data transmission characteristic table at least comprises a module ID field, a delay field and a bandwidth field;
the module ID field is used for recording unique module name and/or module number information of the IP module;
the delay field is used for recording the delay value of the corresponding IP module in EDA simulation;
and the bandwidth field is used for recording the bandwidth value of the corresponding IP module in EDA simulation.
Further, the main equipment end is an IP module capable of controlling a bus, and the bus type is an AXI type;
when performance verification is carried out, an operation instruction is sent to a slave device side slave in a system through a master device side master, wherein the slave device side slave is a DDR module or is provided with a chip memory module DDR module, and data is read and written to the DDR module according to the operation instruction;
the data path is formed between the master equipment end and the slave equipment end.
Further, judging whether the data path has the change of the clock domain, and introducing a register Slice module into the data path to improve the working frequency of the bus when judging that the data path has the change of the clock domain;
and taking time delay and bandwidth change brought by introducing the Slice module into consideration when calculating the delay value and the bandwidth value of the data path.
Further, the delay value and the bandwidth value of the Slice module of the register are obtained, the delay values of the Slice module are accumulated together when the delay of the data path is calculated, and the bandwidth values of the Slice module are compared together when the bandwidth of the data path is calculated.
Further, for read and write operation instructions, the delay and bandwidth collector is capable of calculating a read operation delay value and a write operation delay value for each IP block, respectively; correspondingly, the delay values recorded in the module data transmission characteristic table comprise a read operation delay value and a write operation delay value;
when performance test is carried out, judging whether an operation instruction sent by a main equipment end is of a read operation type or a write operation type; when the read operation type is judged, the delay value of the data path of the main equipment end is accumulated with the delay value of the read operation of the related module on the path of the data path; and when the write operation type is determined, accumulating the write operation delay value of the relevant module on the path of the data path by the data path delay value of the main equipment end.
Further, for each DUT to be designed, when the DUT to be designed is updated, EDA simulation of the updated DUT to be designed is started, and the module data transmission characteristic table is updated according to a new EDA simulation process, so that the delay value and the bandwidth value of the module recorded in the module data transmission characteristic table are matched with the updated SOC chip design.
The invention also provides a system for verifying the performance of the SOC chip, which comprises:
the EDA simulation subsystem is used for performing EDA simulation on a design DUT to be tested, the design DUT to be tested corresponds to an SOC chip integrated with a plurality of IP modules, and each IP module is connected through an on-chip bus; wherein the EDA simulation subsystem is configured to: EDA simulation test case information for the DUT to be designed is obtained, and a corresponding simulation excitation test file is arranged corresponding to each test case; based on the simulation excitation test file of the test case, the test excitation module applies test excitation to the DUT to be tested to perform EDA simulation; the test excitation module comprises a delay and bandwidth collector, wherein the delay and bandwidth collector is used for monitoring operation delay information and bandwidth information of each IP module in the chip system in the EDA simulation process, and adding the delay value and bandwidth value of each IP module into a preset module data transmission characteristic table after obtaining the delay value and bandwidth value of each IP module according to the monitored information;
the SOC chip performance verification subsystem is used for verifying the system performance of the SOC chip; the SOC chip performance verification subsystem is configured to: acquiring a path performance calculation instruction triggered by a user aiming at a data path of a current main equipment end, and acquiring module information on a path of the data path according to the path performance calculation instruction; reading delay values and bandwidth values of corresponding modules from a module data transmission characteristic table of the EDA simulation subsystem according to the module information; and calculating the data path delay and the data path bandwidth of the data path based on the delay value and the bandwidth value, wherein the delay value of the data path at the master device side is accumulated with the delay value of the relevant module on the path of the data path, and the bandwidth value of the data path at the master device side is the bandwidth value of the minimum module in the relevant module on the path of the data path.
The invention also provides an electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of the preceding claims.
The invention also provides a computer storage medium storing computer instructions for causing the computer to perform a method according to any one of the preceding claims.
Compared with the prior art, the invention has the following advantages and positive effects by taking the technical scheme as an example: according to the SOC chip performance verification scheme provided by the invention, the delay and bandwidth collector is arranged on the test excitation module of EDA simulation to collect the delay value and the bandwidth value of each IP module in the chip system in the EDA simulation process, the collected delay value and bandwidth value are added into the preset module data transmission characteristic table for recording, and then the channel bandwidth and the channel delay of the current main equipment end are calculated by reading the data in the module data transmission characteristic table when the SOC chip performance is verified, so that the delay and bandwidth information of a data channel can be obtained without performing new EDA simulation, and the writing of specific test cases for the IP module is not required, thereby improving the performance verification efficiency of the SOC chip.
Drawings
Fig. 1 is a diagram illustrating information when running EDA simulation in the SOC chip performance verification method according to an embodiment of the present invention.
Fig. 2 is a pipeline structure diagram of a data path provided in an embodiment of the present invention.
Fig. 3 is a pipeline structure diagram after adding a Slice module to a data path with a changed clock domain according to an embodiment of the present invention.
Fig. 4 is a diagram illustrating an exemplary data structure of a module data transmission characteristic table according to an embodiment of the present invention.
Fig. 5 is an information example diagram of a data transmission characteristic table of a dynamic update module according to an embodiment of the present invention.
Detailed Description
The SOC chip performance verification method, system, device and storage medium disclosed in the present invention are described in further detail below with reference to the accompanying drawings and specific embodiments. It is noted that techniques (including methods and apparatus) known to those of ordinary skill in the relevant art may not be discussed in detail, but are considered to be part of the specification where appropriate. Meanwhile, other examples of the exemplary embodiment may have different values. The structures, proportions, sizes, etc. shown in the drawings are shown only in connection with the present disclosure for purposes of understanding and reading by those skilled in the art and are not intended to limit the scope of the invention.
In the description of the embodiment of the present application, "/" means "and/or" is used to describe the association relationship of the association object, which means that three relationships may exist, for example, "a and/or b" means: there are three cases of A and B separately. In the description of the embodiments of the present application, "plurality" means two or more.
Examples
The invention provides a performance verification method of an SOC chip, which comprises the following steps of.
S100, EDA simulation test case information for a DUT to be designed is obtained, and a corresponding simulation excitation test file is arranged corresponding to each test case; the DUT to be designed corresponds to an SOC chip integrated with a plurality of IP modules (i.e. modules), and each IP module is connected through an on-chip bus.
S200, based on a simulation excitation test file of the test case, a test excitation module applies test excitation to a design DUT to be tested to perform EDA simulation; the test excitation module comprises a delay and bandwidth collector, wherein the delay and bandwidth collector is used for monitoring operation delay information and bandwidth information of each IP module in the chip system in an EDA simulation process, and adding the delay value and the bandwidth value of each IP module into a preset module data transmission characteristic table after obtaining the delay value and the bandwidth value of each IP module according to the monitored information.
And S300, calculating the data path delay and the data path bandwidth of the IP module serving as the master equipment end master based on the delay value and the bandwidth value of each IP module recorded in the data transmission characteristic table of the module when the performance verification of the SOC chip is carried out, wherein the data path delay value of the master equipment end master is accumulated as the delay value of the relevant module on the path of the current data path, and the data path bandwidth value of the master equipment end master is the bandwidth value of the minimum module in the relevant module on the path of the current data path.
The design under test DUT (Design under Test), i.e. the design of the SOC chip under test, is usually referred to as the register transfer level RTL code of the SOC chip during the functional emulation phase.
The test case (case test) is to write a series of codes in order to verify the function or performance of the SOC chip. Taking UVM (Universal Verification Methodology ) verification as an example, which is commonly used in chip design, test cases are written based on the system verilog language, and stimulus is generated by using a UVM sequence (UVM sequence) manner, and different test cases correspond to different test stimulus, namely, correspond to different simulation stimulus test files (also called simulation files).
When EDA simulation is performed, after the hardware circuit function of the SOC chip is described by using a hardware description language, such as verilog, RTL codes are formed, and excitation is applied to the RTL codes through a simulation excitation test file, namely, external signal input is simulated, so that whether the SOC chip design can run correctly is judged.
The IP module is a specific functional module in the chip. Examples of the modules include a CPU module, a DDR module, a USB module, and a PCIE module. The SOC chip integrates the IP modules of the system, and an on-chip bus is responsible for connecting all the IP modules in the system so that the IP modules can exchange data and share resources.
For any SOC chip to be verified, when EDA simulation is carried out, a design DUT to be tested of the SOC chip can be obtained first, EDA simulation test case information written for the design DUT to be tested is then obtained, and a corresponding simulation excitation test file testbench is arranged corresponding to each test case. After the EDA simulation is started, a test excitation module of the EDA simulation system applies test excitation to the DUT to be tested based on a simulation excitation test file testbench of the test case so as to perform EDA simulation.
Referring to fig. 1, in this embodiment, the test excitation module includes a delay and bandwidth collector, where the delay and bandwidth collector is configured to monitor operation delay information and bandwidth information of each IP module in the chip system in the EDA simulation process, and obtain a delay value and a bandwidth value of each IP module according to the monitored information, and then add the delay value and the bandwidth value of each IP module to a preset module data transmission characteristic table. I.e. the delay and bandwidth data of each module is obtained by a delay and bandwidth collector and stored.
When the performance of the SOC chip is verified later, the data path delay and the data path bandwidth of the IP module serving as the master device side master can be calculated based on the delay value and the bandwidth value of each IP module recorded in the module data transmission characteristic table. Specifically, the delay value of the data path of the master device end master is accumulated for the delay value of the relevant module on the path of the current data path, and the bandwidth value of the data path of the master device end master is the bandwidth value of the bandwidth minimum module in the relevant module on the path of the current data path.
In this embodiment, the master device side is a device that initiates a transaction, and a slave device side is disposed corresponding to the master device side, where the slave device side is a device that accepts a transaction, and a pipeline from the master device side to the slave device side forms a data path. Specifically, one or more intermediate modules may be disposed between the master device side and the slave device side, where the data path is formed between the master device side and the slave device side.
In this embodiment, the data structure of the module data transmission characteristic table may be preset by a user or a system. Preferably, the table of the module data transmission characteristics table includes at least a module ID field, a delay field, and a bandwidth field.
The module ID field is used for recording unique module name and/or module number information of the IP module;
the delay field is used for recording the delay value of the corresponding IP module in EDA simulation;
and the bandwidth field is used for recording the bandwidth value of the corresponding IP module in EDA simulation.
In this embodiment, the master device side is an IP module capable of controlling a bus, and the bus type is AXI (Advanced eXtensible Interface) type. The AXI bus is an on-chip bus protocol used in high performance embedded systems. It is widely used in ARM architecture processors and other system chips. In AXI bus based chip systems, there are two types of devices: master device master and slave device slave. The master device side is the device that initiates the transaction, and the slave device side is the device that accepts the transaction, communicating between them over the AXI bus.
In this embodiment, the master device side master may send a read-write request to the slave device side slave, to access the register or memory of the slave device slave and to receive the response returned from the slave device slave.
The slave device slave may be a peripheral device, a memory unit, or other device that needs to be accessed by the master device. After receiving the read-write request from the slave device, the slave device executes corresponding operation and returns a response to the master device so as to complete data transmission or operation.
In this embodiment, when performing performance verification, the master device sends an operation instruction to the slave device slave in the system. The slave device side slave is a DDR module or is provided with a chip memory module DDR module, and reads and writes data of the DDR module according to the operation instruction, namely the slave device side slave operates according to the operation instruction of the master device side, so that the actual working scene of the SOC chip is simulated.
By way of example and not limitation, referring to FIG. 2, for example, the master device side is a USB module, the slave device side is a DDR module, and the DDR module is provided with a DDR model (DDR model). MTX1, MTX2, MTX3 and MTX4 respectively represent an intermediate IP module which needs to be passed through when data passes from the USB module to the DDR model, and the data passes from the USB module to the DDR module form a data path of the pipeline structure shown in FIG. 2, wherein: USB module MTX1 MTX2 MTX3 MTX4 DDR model.
In the EDA simulation process, the delay values of the modules such as MTX1, MTX2, MTX3, MTX4 and the like monitored by the delay and bandwidth collector are respectively latency1, latency 2, latency 3 and latency 4. When performing performance verification, the delay_c of the data path of the USB module is to add the delay values of the MTX1, MTX2, MTX3, MTX4 modules on the path, namely, delay 1, delay 2, delay 3, and delay 4.
And the bandwidth bandwidth_c of the data path of the USB module is that the bandwidths of the MTX1, MTX2, MTX3 and MTX4 modules on the paths are compared, and the bandwidth value of the module with the minimum bandwidth is selected as the bandwidth of the data path. Since the bandwidth of the data path is determined by the bandwidth of the IP block with the smallest bandwidth on the path.
According to the scheme provided by the invention, the delay and bandwidth collectors are arranged in the test excitation module, and when EDA simulation is carried out, delay data and bandwidth data of various IP modules in all EDA simulation are collected through the delay and bandwidth collectors, namely, the delay value and the bandwidth value of each IP module are values obtained by each EDA simulation based on history, and no specific delay test case and bandwidth test case are required to be written, so that EDA simulation is not required to be run based on the specific test case.
In another implementation of this embodiment, the pipeline structure of the data path may also be optimized in the presence of clock domain variations in the data path, taking into account data transfers across the clock domain. Specifically, whether the data path has a change of the clock domain is determined, and when the data path has a change of the clock domain, a register Slice module is introduced into the data path to improve the working frequency of the bus.
The register Slice module is used for cutting off a data transmission pipeline, and shooting a transmission signal at the cut-off position by using a register (register) (the signal is delayed by one clock period), namely, inserting the register Slice between module nodes of a data path. Referring to fig. 3, by way of example and not limitation, if there is a change in clock domain between the MTX1 module and the MTX2 module, a Slice module is configured between the MTX1 module and the MTX2 module to improve the operating frequency of the bus.
In this case, the delay value and the bandwidth value of the data path are calculated by taking into consideration the time delay and the bandwidth variation caused by the introduction of the Slice module. In specific implementation, the delay value and the bandwidth value of the Slice module of the register can be obtained, the delay values of the Slice module are accumulated together when the delay of the data path is calculated, and the bandwidth values of the Slice module are compared together when the bandwidth of the data path is calculated.
In this embodiment, the delay value and the bandwidth value of the Slice module may also be obtained through EDA simulation. Alternatively, the delay value and bandwidth value of the Slice module are provided by the provider/designer of the IP module. In either way, the delay value and the bandwidth value of the Slice module may be stored in the module data transmission characteristic table before performance verification.
Referring to FIG. 4, as an example, delay values of MTX1, MTX2, MTX3, MTX4 and Slice modules obtained by EDA simulation of history are 20ns, 30ns, 40ns, 50ns, 60ns respectively, and bandwidth values of IP modules are 10Mbyte/s, 20Mbyte/s, 30Mbyte/s, 40Mbyte/s and 50Mbyte/s, respectively, and the system can directly read the delay values and bandwidth values in the foregoing table to obtain delay and bandwidth information of the corresponding data path when calculating the bandwidth.
Specifically, the path delay value latency_c=20ns+30ns+40ns+50ns+60ns=200ns, and the path bandwidth value bandwidth_c=10 Mbyte/s, i.e. the bandwidth value of the MTX1 module.
In another implementation of this embodiment, the delay and bandwidth collector is capable of calculating a read operation delay value and a write operation delay value for each IP block, respectively, for read and write operation instructions. Correspondingly, the delay values recorded in the module data transmission characteristic table comprise a read operation delay value and a write operation delay value.
When performance test is carried out, judging whether an operation instruction sent by a main equipment end is of a read operation type or a write operation type; when the read operation type is judged, the delay value of the data path of the main equipment end is accumulated with the delay value of the read operation of the related module on the path of the data path; and when the write operation type is determined, accumulating the write operation delay value of the relevant module on the path of the data path by the data path delay value of the main equipment end.
In another implementation of this embodiment, the module data transmission characteristic table may be dynamically updated according to dynamic changes of the EDA simulation.
Specifically, for each DUT to be designed, when the DUT to be designed is updated, an EDA simulation of the DUT to be designed after updating is started, that is, a new original simulation (EDA simulation) appears, and the module data transmission characteristic table mobile list is updated according to the new EDA simulation process, as shown in fig. 5, so that the delay value and the bandwidth value of the module recorded in the module data transmission characteristic table are matched with the updated SOC chip design.
In this way, each real EDA simulation (i.e., the original simulation in fig. 5) corresponds to a table data update of the module data transmission characteristic table module list, so that real-time and accurate data in the module data transmission characteristic table module list can be ensured.
The invention also provides a system for verifying the performance of the SOC chip.
The system comprises an EDA simulation subsystem and an SOC chip performance verification subsystem.
The EDA simulation subsystem is used for performing EDA simulation on a design DUT to be tested, the design DUT to be tested corresponds to an SOC chip integrated with a plurality of IP modules, and all the IP modules are connected through an on-chip bus.
In this embodiment, the EDA simulation subsystem is configured to: EDA simulation test case information for the DUT to be designed is obtained, and a corresponding simulation excitation test file is arranged corresponding to each test case; based on the simulation excitation test file of the test case, the test excitation module applies test excitation to the DUT to be tested to perform EDA simulation; the test excitation module comprises a delay and bandwidth collector, wherein the delay and bandwidth collector is used for monitoring operation delay information and bandwidth information of each IP module in the chip system in the EDA simulation process, and adding the delay value and bandwidth value of each IP module into a preset module data transmission characteristic table after obtaining the delay value and bandwidth value of each IP module according to the monitored information.
And the SOC chip performance verification subsystem is used for verifying the system performance of the SOC chip.
In this embodiment, the SOC chip performance verification subsystem is configured to: acquiring a path performance calculation instruction triggered by a user aiming at a data path of a current main equipment end, and acquiring module information on a path of the data path according to the path performance calculation instruction; reading delay values and bandwidth values of corresponding modules from a module data transmission characteristic table of the EDA simulation subsystem according to the module information; and calculating a data path delay and a data path bandwidth of the data path based on the delay value and the bandwidth value.
And accumulating the delay value of the related module on the path of the data path by the data path delay value of the main equipment end, and accumulating the bandwidth value of the bandwidth of the minimum module in the related module on the path of the data path by the data path bandwidth value of the main equipment end.
Other technical features are described in the previous embodiments and are not described in detail here.
Another embodiment of the present invention also provides an electronic device, including:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of the preceding claims.
Other technical features are described in the previous embodiments and are not described in detail here.
The invention also provides a computer storage medium storing computer instructions for causing the computer to perform a method according to any one of the preceding claims.
The storage medium may include a U-disk, a removable hard disk, a Read Only Memory (ROM), a random access memory (random access memory, RAM), a magnetic disk, or an optical disk, etc. various media capable of storing program codes.
Other technical features are described in the previous embodiments and are not described in detail here.
In the above description, the disclosure of the present invention is not intended to limit itself to these aspects. Rather, the components may be selectively and operatively combined in any number within the scope of the present disclosure. In addition, terms like "comprising," "including," and "having" should be construed by default as inclusive or open-ended, rather than exclusive or closed-ended, unless expressly defined to the contrary. All technical, scientific, or other terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Common terms found in dictionaries should not be too idealized or too unrealistically interpreted in the context of the relevant technical document unless the present disclosure explicitly defines them as such. Any alterations and modifications of the present invention, which are made by those of ordinary skill in the art based on the above disclosure, are intended to be within the scope of the appended claims.
Claims (10)
1. The SOC chip performance verification method is characterized by comprising the following steps:
EDA simulation test case information for the DUT to be designed is obtained, and a corresponding simulation excitation test file is arranged corresponding to each test case; the DUT to be tested is correspondingly integrated with the SOC chip with a plurality of IP modules, and each IP module is connected through an on-chip bus;
based on the simulation excitation test file of the test case, the test excitation module applies test excitation to the DUT to be tested to perform EDA simulation; the test excitation module comprises a delay and bandwidth collector, wherein the delay and bandwidth collector is used for monitoring operation delay information and bandwidth information of each IP module in the chip system in an EDA simulation process, and adding the delay value and the bandwidth value of each IP module into a preset module data transmission characteristic table after obtaining the delay value and the bandwidth value of each IP module according to the monitored information;
and when the performance verification of the SOC chip is carried out, calculating the data path delay and the data path bandwidth of the IP module serving as the master equipment end master based on the delay value and the bandwidth value of each IP module recorded in the data transmission characteristic table of the module, wherein the data path delay value of the master equipment end master is accumulated as the delay value of the relevant module on the path of the current data path, and the data path bandwidth value of the master equipment end master is the bandwidth value of the bandwidth minimum module in the relevant module on the path of the current data path.
2. The method according to claim 1, characterized in that: the module data transmission characteristic table at least comprises a module ID field, a delay field and a bandwidth field;
the module ID field is used for recording unique module name and/or module number information of the IP module;
the delay field is used for recording the delay value of the corresponding IP module in EDA simulation;
and the bandwidth field is used for recording the bandwidth value of the corresponding IP module in EDA simulation.
3. The method according to claim 1, characterized in that: the main equipment end is an IP module capable of controlling a bus, and the bus type is an AXI type;
when performance verification is carried out, an operation instruction is sent to a slave device side slave in the system through a master device side master, wherein the slave device side slave is a DDR module of a chip memory module or is provided with the DDR module, and data is read and written to the DDR module according to the operation instruction; the data path is formed between the master equipment end and the slave equipment end.
4. A method according to claim 3, characterized in that: judging whether the data path has the change of the clock domain, and introducing a register Slice module into the data path to improve the working frequency of a bus when judging that the data path has the change of the clock domain;
and taking time delay and bandwidth change brought by introducing the Slice module into consideration when calculating the delay value and the bandwidth value of the data path.
5. The method according to claim 4, wherein: and acquiring the delay value and the bandwidth value of the Slice module, accumulating the delay values of the Slice module together when calculating the delay of the data path, and comparing the bandwidth values of the Slice module together when calculating the bandwidth of the data path.
6. A method according to claim 3, characterized in that: the delay and bandwidth collector is capable of calculating a read operation delay value and a write operation delay value of each IP module respectively for read and write operation instructions; correspondingly, the delay values recorded in the module data transmission characteristic table comprise a read operation delay value and a write operation delay value;
when performance test is carried out, judging whether an operation instruction sent by a main equipment end is of a read operation type or a write operation type; when the read operation type is judged, the delay value of the data path of the main equipment end is accumulated with the delay value of the read operation of the related module on the path of the data path; and when the write operation type is determined, accumulating the write operation delay value of the relevant module on the path of the data path by the data path delay value of the main equipment end.
7. The method according to claim 1, characterized in that: for each DUT to be designed, when the DUT to be designed is updated, EDA simulation of the updated DUT to be designed is started, and the module data transmission characteristic table is updated according to a new EDA simulation process, so that the delay value and the bandwidth value of the module recorded in the module data transmission characteristic table are matched with the updated SOC chip design.
8. An SOC chip performance verification system, comprising:
the EDA simulation subsystem is used for performing EDA simulation on a design DUT to be tested, the design DUT to be tested corresponds to an SOC chip integrated with a plurality of IP modules, and each IP module is connected through an on-chip bus; wherein the EDA simulation subsystem is configured to: EDA simulation test case information for the DUT to be designed is obtained, and a corresponding simulation excitation test file is arranged corresponding to each test case; based on the simulation excitation test file of the test case, the test excitation module applies test excitation to the DUT to be tested to perform EDA simulation; the test excitation module comprises a delay and bandwidth collector, wherein the delay and bandwidth collector is used for monitoring operation delay information and bandwidth information of each IP module in the chip system in the EDA simulation process, and adding the delay value and bandwidth value of each IP module into a preset module data transmission characteristic table after obtaining the delay value and bandwidth value of each IP module according to the monitored information;
the SOC chip performance verification subsystem is used for verifying the system performance of the SOC chip; the SOC chip performance verification subsystem is configured to: acquiring a path performance calculation instruction triggered by a user aiming at a data path of a current main equipment end, and acquiring module information on a path of the data path according to the path performance calculation instruction; reading delay values and bandwidth values of corresponding modules from a module data transmission characteristic table of the EDA simulation subsystem according to the module information; and calculating the data path delay and the data path bandwidth of the data path based on the delay value and the bandwidth value, wherein the delay value of the data path at the master device side is accumulated with the delay value of the relevant module on the path of the data path, and the bandwidth value of the data path at the master device side is the bandwidth value of the minimum module in the relevant module on the path of the data path.
9. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.
10. A computer storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-7.
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