CN113076709B - Multi-core processor function verification platform and method based on mixed reference model - Google Patents
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Abstract
The invention discloses a multi-core processor function verification platform and method based on a hybrid reference model, and belongs to the technical field of integrated circuits. The hybrid reference model in the platform consists of an instruction set simulator and a SystemVerilog model. The instruction set simulator is a functional precision level model and is used for verifying whether each instruction in the multi-core processor is executed correctly; the SystemVerilog model is a mixed model of functions and time sequence precision, and is used for verifying whether a memory access instruction executed by the multi-core processor and a Cache consistency operation process are correct. For different instruction set architectures, the verifier can directly adopt the existing instruction set simulators, such as Spike, ARMulator, and the like, so that the design time cost of the reference model can be effectively shortened. In the invention, the instruction set simulator and the SystemVerilog model can run simultaneously, thereby effectively improving the simulation speed of the verification platform.
Description
Technical Field
The invention relates to a multi-core processor function verification platform and method based on a hybrid reference model, and belongs to the technical field of integrated circuits.
Background
With the rapid development of integrated circuit technology, more and more cores are integrated on the same chip, and multi-core processors have become a mainstream architecture of processor design. However, to meet the ever-increasing high performance demands, processors are increasingly scaled up and their functional complexity is also increasing, which presents a significant challenge for the verification effort of multi-core processors.
Currently, the mainstream function verification method includes: form verification, hardware acceleration verification, and simulation-based functional verification. The simulation-based function verification method is most widely applied to verification work of the multi-core processor. Simulation-based functional verification typically employs a self-test method or a reference model. The self-checking method is generally suitable for a small-scale and simple-structure system, and therefore, a simulation-based multi-core processor verification platform generally adopts a reference model for functional verification.
The simulation verification platform based on the reference model verifies the functional correctness of the multi-core processor by comparing the simulation result of the multi-core processor with the execution result of the reference model. However, the complexity of the multi-core processor results in a sudden increase in the difficulty of designing the reference model, which typically requires significant time for the verifier to build the reference model. Therefore, how to quickly design a reference model with high accuracy and high simulation speed is important for verifying the platform design of the multi-core processor function.
Disclosure of Invention
The invention provides a multi-core processor function verification platform and method based on a mixed reference model, which aims to solve the problems that the design difficulty of the reference model is suddenly increased and verification personnel usually need to spend a great deal of time to construct the reference model due to the complexity of the multi-core processor at present.
A first object of the present invention is to provide a hybrid reference model for use in a multi-core processor functional verification platform, the hybrid reference model being composed of an instruction set simulator and a SystemVerilog model; the instruction set simulator is a functional precision level model and is used for verifying whether each instruction in the multi-core processor is executed correctly; the SystemVerilog model is a mixed model of functions and time sequence precision, and is used for verifying whether a memory access instruction executed by the multi-core processor and a Cache consistency operation process are correct.
Optionally, the SystemVerilog model includes control logic of a Cache coherence protocol, a Cache state history table, and a memory access request queue.
The second object of the invention is to provide a multi-core processor function verification platform based on a mixed reference model, which comprises a multi-core processor system DUT to be tested, a test stimulus generator, a mixed reference model, and a monitoring module and a scoreboard based on SystemVerilog language; the mixed reference model is the mixed reference model.
Optionally, the monitoring module is configured to monitor a value of the register set after each instruction is executed by the instruction set simulator in the DUT and the mixed reference model, monitor state transitions and timing relationships generated in a Cache coherence protocol operation flow of the DUT and the SystemVerilog model, and control cooperative work of the instruction set simulator and the SystemVerilog model.
Optionally, the multi-core processor system DUT to be tested comprises a multi-core processor system based on RISC-V, ARM, ALPHA and MIPS instruction set architecture.
A third object of the present invention is to provide a method for verifying a multi-core processor function based on a hybrid reference model, where the method is applied to the above-mentioned multi-core processor function verification platform based on a hybrid reference model, and the method includes:
step 1, loading test excitation to a DUT and a mixed reference model respectively;
step 2, a monitoring module starts to monitor and record program execution conditions of the DUT and the mixed reference model;
Step 3, after the excitation to be tested is executed, outputting a simulation log file;
Step 4, the scoreboard compares simulation log files of the DUT and the mixed reference model, judges whether the multi-core processor or the mixed reference model is correct in function or not, and outputs a coverage rate report;
And 5, if the simulation log files of the DUT and the mixed reference model are inconsistent, checking the multi-core processor and the mixed reference model, and improving the multi-core processor or the mixed reference model.
Optionally, the system verilog model of the hybrid reference model in the multi-core processor function verification platform based on the hybrid reference model includes control logic of a Cache consistency protocol, a Cache state history table and a memory access request queue.
Optionally, the step 2 monitoring module starts to monitor and record program execution conditions of the DUT and the hybrid reference model, including:
Step 2.1, the monitoring module starts to monitor the instruction execution conditions of the DUT and the instruction set simulator, when a private Cache of a certain core in the instruction set simulator is in memory request missing or active eviction, the monitoring module transmits the memory request to the SystemVerilog model for processing, and the instruction set simulator records the current memory address and continues to run a test program until encountering an instruction related to the current memory address, and stops waiting for the response of the SystemVerilog model; meanwhile, the SystemVerilog model feeds back a Cache state conversion result and corresponding data to the instruction set simulator and the monitoring module through control logic of an internal Cache consistency protocol according to the request type and a Cache state history table.
Optionally, the step 2 further includes:
And 2.2, when a plurality of cores in the instruction set simulator initiate access requests to the same memory address at the same time, the monitoring module and the operation of the instruction set simulator are the same as in step 2.1, the SystemVerilog model inputs the access requests into the access request queue according to the arbitration mechanism of the DUT in sequence, the control logic of the SystemVerilog model processes the access requests in the access request queue in a pipeline mode, and in turn, the Cache state conversion result and corresponding data are fed back to the instruction set simulator and the monitoring module, and in addition, the monitoring module records the cores initiating the access requests in the DUT and the mixed reference model and the access request execution completion time of each core.
Optionally, the step 4 includes:
The scoreboard judges whether the pipeline function of the DUT is correct by comparing whether the numerical values of the register group are consistent after each instruction is executed by the DUT and the instruction set simulator; the scoreboard judges whether the protocol conversion function of the Cache consistency protocol management module in the DUT is correct or not by comparing the Cache state conversion result after the completion of the access request of the DUT and the SystemVerilog model with the corresponding data; and the scoreboard compares whether the execution completion sequence of the access request of each core is consistent when the DUT and the SystemVerilog model simultaneously request access to the same memory address for the cores, and further judges whether the time sequence of the Cache consistency protocol management module in the DUT is correct.
The invention has the beneficial effects that:
(1) The mixed reference model provided by the invention consists of an instruction set simulator and a SystemVerilog model. The instruction set simulator can be slightly adjusted by adopting the existing instruction set simulator or based on the existing instruction set simulator aiming at the instruction set architecture to be tested; the SystemVerilog model only focuses on the result output of memory access operation and the execution sequence of Cache consistency operation, and is simpler in design. Therefore, the design method of the mixed reference model can effectively reduce the design time cost of the reference model.
(2) In the multi-core processor function verification platform based on the mixed reference model, when the current multi-executed instruction of the instruction set simulator is irrelevant to the memory address being accessed and stored in the SystemVerilog model, the instruction set simulator and the SystemVerilog model can run simultaneously, so that the simulation speed of the multi-core processor function verification platform is effectively improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a hybrid reference model in a multi-core processor functional verification platform based on the hybrid reference model provided in one embodiment of the invention;
FIG. 2 is a block diagram of a multi-core processor functional verification platform based on a hybrid reference model provided in one embodiment of the invention;
FIG. 3 is a flowchart of step 2 in a method for validating functionality of a multi-core processor based on a hybrid reference model according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a SystemVerilog model in a multi-core processor function verification platform based on a hybrid reference model according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
Embodiment one:
The embodiment provides a mixed reference model of a multi-core processor function verification platform based on the mixed reference model, referring to fig. 1, wherein the mixed reference model is composed of an instruction set simulator and a SystemVerilog model; the instruction set simulator is a functional precision level model and is used for verifying whether each instruction in the multi-core processor is executed correctly; the SystemVerilog model is a mixed model of functions and time sequence precision, and is used for verifying whether a memory access instruction executed by the multi-core processor and a Cache consistency operation process are correct. The SystemVerilog model comprises control logic of a Cache consistency protocol, a Cache state history table and a memory access request queue.
It should be noted that, for different instruction set architectures, the verifier may directly use the existing instruction set simulator, such as Spike, ARMulator, so as to effectively shorten the design time overhead of the reference model. In the invention, the instruction set simulator and the SystemVerilog model can run simultaneously, thereby effectively improving the simulation speed of the verification platform.
Example two
The embodiment provides a multi-core processor function verification method based on a mixed reference model, which is described by taking a multi-core processor system to be tested as a RISC-V multi-core processor system as an example, wherein the multi-core processor function verification platform based on the mixed reference model comprises a multi-core processor system to be tested (DUT), a test excitation generator, a mixed reference model, and a monitoring module and a scoreboard based on a SystemVerilog language; the multi-core processor system to be tested is a RISC-V multi-core processor system.
As shown in fig. 2, the monitoring module monitors the values of the register set after each instruction is executed by the DUT and the instruction set simulator, monitors state transitions and timing relationships generated in the Cache coherence protocol operation flow of the DUT and the SystemVerilog model, and controls the cooperative work of the instruction set simulator and the SystemVerilog model.
The verification method comprises the following steps:
step 1, loading test excitation to a DUT and a mixed reference model respectively;
step 2, a monitoring module starts to monitor and record program execution conditions of the DUT and the mixed reference model;
specifically, referring to fig. 3, step 2 includes:
Step 2.1, the monitoring module starts to monitor the instruction execution conditions of the DUT and the instruction set simulator and the change of the register group values of the DUT and the instruction set simulator, when the private Cache of a certain core in the instruction set simulator is in memory access request missing or active eviction, the monitoring module transmits the memory access request to the SystemVerilog model for processing, the instruction set simulator records the current memory access and continues to run a test program until the instruction related to the current memory access is encountered and stops, and simultaneously sends a request to the SystemVerilog model and waits for the response of the SystemVerilog model; after the SystemVerilog model receives the request sent by the instruction set simulator, according to the request type and the Cache state history table of the request, the Cache state conversion result and corresponding data are fed back to the instruction set simulator and the monitoring module through the control logic of the internal Cache consistency protocol.
And 2.2, when a plurality of cores in the instruction set simulator initiate access requests to the same memory address at the same time, the monitoring module and the operation of the instruction set simulator are the same as in step 2.1, the SystemVerilog model inputs the access requests into the access request queue according to the arbitration mechanism of the DUT in sequence, the control logic of the SystemVerilog model processes the access requests in the access request queue in a pipeline mode, and in turn, the Cache state conversion result and corresponding data are fed back to the instruction set simulator and the monitoring module, and in addition, the monitoring module records the cores initiating the access requests in the DUT and the mixed reference model and the access request execution completion time of each core.
Step 3, after the excitation to be tested is executed, outputting a simulation log file;
Step 4, the scoreboard compares simulation log files of the DUT and the mixed reference model, judges whether the multi-core processor or the mixed reference model is correct in function or not, and outputs a coverage rate report;
specifically, the scoreboard judges whether the pipeline function of the DUT is correct by comparing whether the numerical values of the register group are consistent after each instruction is executed by the DUT and the instruction set simulator; the scoreboard judges whether the protocol conversion function of the Cache consistency protocol management module in the DUT is correct or not by comparing the Cache state conversion result after the completion of the access request of the DUT and the SystemVerilog model with the corresponding data; and the scoreboard compares whether the execution completion sequence of the access request of each core is consistent when the DUT and the SystemVerilog model simultaneously request access to the same memory address for the cores, and further judges whether the time sequence of the Cache consistency protocol management module in the DUT is correct.
And 5, if the simulation log files of the DUT and the mixed reference model are inconsistent, checking the multi-core processor and the mixed reference model, and improving the multi-core processor or the mixed reference model.
For ease of understanding, a specific multi-core processor system to be tested is described below as an example, where the specific multi-core processor system to be tested is a RISC-V based multi-core processor system (DUT), the DUT employs a directory-based Cache coherency protocol, and the instruction set simulator in the hybrid reference model employs a Spike simulator.
After the test stimulus is loaded into the DUT, the monitoring module records the corresponding PC value when each core in the DUT and the Spike simulator executes a valid instruction and the change of the register value after the instruction is executed. Meanwhile, the monitoring module also monitors a read-write unit, a Cache and a Cache consistency protocol manager of the DUT, and when the DUT executes instructions related to the memory access, the monitoring module records the starting and finishing time of executing the memory access instructions, the memory access request type, the Cache state conversion condition and related data of read and write of each core.
When the memory access request is missing or actively evicted in the Spike, the monitoring module transmits the memory access request to the SystemVerilog model for processing, the Spike records the current memory access address and continues to run test excitation, and the Spike pauses until encountering an instruction related to the current memory access address and waits for the response of the SystemVerilog model.
Meanwhile, the SystemVerilog model feeds back Cache state conversion results and corresponding data to the Spike and the monitoring module through control logic of an internal Cache consistency protocol according to the access request type and the Cache state history table, and updates the Cache state history table. If other cores in the Spike also initiate access requests to the memory address at this time, the arbitration mechanism of the system verilog model simulates the DUT to sequentially input a plurality of access requests into the access request queue, the control logic processes the access requests in the access request queue in a pipeline form, and the Cache state conversion result and corresponding data are fed back to the Spike and the monitoring module in sequence. The Spike simulator continues to run the current test stimulus based on the access execution result.
Fig. 4 schematically shows a workflow diagram of the SystemVerilog model in an embodiment according to the invention.
And when the test excitation is executed, the monitoring module outputs simulation log files of the DUT and the mixed reference model, and the scoreboard extracts and compares information in the simulation log files. If the comparison results are consistent, collecting coverage rate and outputting a coverage rate report; if the comparison is inconsistent, the DUT and the hybrid reference model are checked, errors are located using simulated log files and DUT or hybrid reference models are improved.
As can be seen from the above-described process of functional verification for RISC-V based multi-core processor Systems (DUTs), the hybrid reference model designed by the present application can employ existing instruction set simulators, while it takes at least several weeks to typically manually construct a functional precision level model of a processor; in addition, the SystemVerilog model in the mixed reference model only focuses on the result output of the memory access operation and the execution sequence of the Cache consistency operation, and the design is simpler. Therefore, the method can greatly reduce the time required for constructing the reference model during design.
The instruction set simulator executes one instruction per clock cycle, while the SystemVerilog model takes several clock cycles to process a memory access request. In the verification process of the multi-core processor function verification platform based on the mixed reference model, when the currently executed instruction of the instruction set simulator is irrelevant to the memory address being accessed and stored in the SystemVerilog model, the instruction set simulator and the SystemVerilog model can run simultaneously, so that the simulation speed of the multi-core processor function verification platform is effectively improved.
Some steps in the embodiments of the present invention may be implemented by using software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (4)
1. The multi-core processor function verification platform based on the mixed reference model is characterized by comprising a multi-core processor system DUT to be tested, a test stimulus generator, a mixed reference model, a monitoring module based on SystemVerilog language and a scoreboard;
the mixed reference model consists of an instruction set simulator and a SystemVerilog model; the instruction set simulator is a functional precision level model and is used for verifying whether each instruction in the multi-core processor is executed correctly; the SystemVerilog model is a mixed model of functions and time sequence precision, and is used for verifying whether a memory access instruction executed by the multi-core processor and a Cache consistency operation process are correct or not;
The SystemVerilog model comprises control logic of a Cache consistency protocol, a Cache state history table and a memory access request queue;
The monitoring module is used for monitoring the numerical value of the register set after each instruction is executed by the instruction set simulator in the DUT and the mixed reference model, monitoring state conversion and time sequence relation generated in the Cache consistency protocol operation flow of the DUT and the SystemVerilog model, and controlling the cooperative work of the instruction set simulator and the SystemVerilog model;
the scoreboard is used for comparing simulation log files of the DUT and the mixed reference model, judging whether the multi-core processor or the mixed reference model is correct in function or not, and outputting a coverage rate report;
The process of the monitoring module for monitoring and recording program execution conditions of the DUT and the mixed reference model comprises the following steps:
Step 2.1, the monitoring module starts to monitor the instruction execution conditions of the DUT and the instruction set simulator, when a private Cache of a certain core in the instruction set simulator is in memory request missing or active eviction, the monitoring module transmits the memory request to the SystemVerilog model for processing, and the instruction set simulator records the current memory address and continues to run a test program until encountering an instruction related to the current memory address, and stops waiting for the response of the SystemVerilog model; meanwhile, the SystemVerilog model feeds back a Cache state conversion result and corresponding data to the instruction set simulator and the monitoring module through control logic of an internal Cache consistency protocol according to the request type and a Cache state history table;
And 2.2, when a plurality of cores in the instruction set simulator initiate access requests to the same memory address at the same time, the monitoring module and the operation of the instruction set simulator are the same as in step 2.1, the SystemVerilog model inputs the access requests into the access request queue according to the arbitration mechanism of the DUT in sequence, the control logic of the SystemVerilog model processes the access requests in the access request queue in a pipeline mode, and in turn, the Cache state conversion result and corresponding data are fed back to the instruction set simulator and the monitoring module, and in addition, the monitoring module records the cores initiating the access requests in the DUT and the mixed reference model and the access request execution completion time of each core.
2. The verification platform of claim 1, wherein the multi-core processor system under test DUT comprises a multi-core processor system based on RISC-V, ARM, ALPHA, power and MIPS instruction set architecture.
3. A method for verifying functions of a multi-core processor based on a hybrid reference model, wherein the method is applied to the implementation of a multi-core processor function verification platform based on a hybrid reference model as set forth in any one of claims 1-2, and the method comprises:
step 1, loading test excitation to a DUT and a mixed reference model respectively;
step 2, a monitoring module starts to monitor and record program execution conditions of the DUT and the mixed reference model;
Step 3, after the excitation to be tested is executed, outputting a simulation log file;
Step 4, the scoreboard compares simulation log files of the DUT and the mixed reference model, judges whether the multi-core processor or the mixed reference model is correct in function or not, and outputs a coverage rate report;
step 5, if the simulation log files of the DUT and the mixed reference model are inconsistent, checking the multi-core processor and the mixed reference model, and improving the multi-core processor or the mixed reference model;
the step 2 monitoring module starts to monitor and record program execution conditions of the DUT and the mixed reference model, and comprises the following steps:
Step 2.1, the monitoring module starts to monitor the instruction execution conditions of the DUT and the instruction set simulator, when a private Cache of a certain core in the instruction set simulator is in memory request missing or active eviction, the monitoring module transmits the memory request to the SystemVerilog model for processing, and the instruction set simulator records the current memory address and continues to run a test program until encountering an instruction related to the current memory address, and stops waiting for the response of the SystemVerilog model; meanwhile, the SystemVerilog model feeds back a Cache state conversion result and corresponding data to the instruction set simulator and the monitoring module through control logic of an internal Cache consistency protocol according to the request type and a Cache state history table;
And 2.2, when a plurality of cores in the instruction set simulator initiate access requests to the same memory address at the same time, the monitoring module and the operation of the instruction set simulator are the same as in step 2.1, the SystemVerilog model inputs the access requests into the access request queue according to the arbitration mechanism of the DUT in sequence, the control logic of the SystemVerilog model processes the access requests in the access request queue in a pipeline mode, and in turn, the Cache state conversion result and corresponding data are fed back to the instruction set simulator and the monitoring module, and in addition, the monitoring module records the cores initiating the access requests in the DUT and the mixed reference model and the access request execution completion time of each core.
4. A method according to claim 3, wherein said step 4 comprises:
The scoreboard judges whether the pipeline function of the DUT is correct by comparing whether the numerical values of the register group are consistent after each instruction is executed by the DUT and the instruction set simulator; the scoreboard judges whether the protocol conversion function of the Cache consistency protocol management module in the DUT is correct or not by comparing the Cache state conversion result after the completion of the access request of the DUT and the SystemVerilog model with the corresponding data; and the scoreboard compares whether the execution completion sequence of the access request of each core is consistent when the DUT and the SystemVerilog model simultaneously request access to the same memory address for the cores, and further judges whether the time sequence of the Cache consistency protocol management module in the DUT is correct.
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