CN117610472A - Ultra-large scale cluster FPGA prototype verification system - Google Patents

Ultra-large scale cluster FPGA prototype verification system Download PDF

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CN117610472A
CN117610472A CN202410099560.0A CN202410099560A CN117610472A CN 117610472 A CN117610472 A CN 117610472A CN 202410099560 A CN202410099560 A CN 202410099560A CN 117610472 A CN117610472 A CN 117610472A
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fpga
port
target
register
fpgas
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CN117610472B (en
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韩冰
夏人康
李旭
陆嘉鋆
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Shanghai Hejian Industrial Software Group Co Ltd
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Shanghai Hejian Industrial Software Group Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention relates to the technical field of chips, in particular to a prototype verification system of a super-large-scale cluster FPGA, which comprises P first FPGAs and Q second FPGAs which are mutually connected; the first FPGA comprises a switching module, M first ports and N second ports, any two ports in the first FPGA can communicate through the switching module, and each first port can be cascaded with one first FPGA; the second FPGA comprises a third port, the third port is used for being interconnected with the second port, and the second FPGA is used for loading a chip to-be-tested design code. The invention can flexibly and infinitely expand the number of the FPGA used for chip prototype verification and realize interconnection of ultra-large-scale cluster FPGA.

Description

Ultra-large scale cluster FPGA prototype verification system
Technical Field
The invention relates to the technical field of chips, in particular to a super-large-scale cluster FPGA prototype verification system.
Background
In the process of chip development, FPGA prototype verification is required to be carried out on the chip before the chip is streamed, and the FPGA prototype verification is used for verifying the chip function. For large and ultra-large chip designs, a large-scale clustered FPGA prototype verification system is required for FPGA prototype verification. The large-scale clustered FPGA prototype verification system has huge FPGA number requirements on the clustered FPGA prototype verification system, and how to implement interconnection of large-scale clustered FPGAs for chip prototype verification and communication between ultra-large clustered FPGAs becomes a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a super-large-scale cluster FPGA prototype verification system which can flexibly and infinitely expand the number of FPGAs for chip prototype verification and realize interconnection of the super-large-scale cluster FPGAs.
According to a first aspect of the present invention, there is provided a very large scale clustered FPGA prototype verification system comprising P interconnected first FPGAs { F 1 ,F 2 ,…,F p ,…,F P And Q second FPGAs, wherein F p For the P-th first FPGA, the value range of P is 1 to P;
the first FPGA comprises a switching module, M first ports and N second ports, any two ports in the first FPGA can communicate through the switching module, each first port can be cascaded with one first FPGA, each second port can be connected with one second FPGA, and Q is less than or equal to P multiplied by N;
the second FPGA comprises a third port, the third port is used for being interconnected with the second port, and the second FPGA is used for loading a chip to-be-tested design code;
any two second FPGAs connected to the same first FPGA can communicate through corresponding second ports and switching modules;
each F p Can pass through the first port and the switching module and { F 1 ,F 2 ,…,F p ,…,F P Divide F in } p Any one of the other first FPGAs is communicated;
each connected at F p Any one of the second FPGAs can pass through the corresponding second port, the switching module and { F } 1 ,F 2 ,…,F p ,…,F P Divide F in } p And any other second FPGA connected with any other first FPGA communicates.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the ultra-large scale cluster FPGA prototype verification system provided by the invention can achieve quite technical progress and practicality, has wide industrial utilization value, and has at least the following beneficial effects:
according to the system, the first FPGA which can be cascaded is arranged, the first FPGA is cascaded through the first port, the second FPGA is connected through the second port, and the design code to be tested of the chip is loaded through the second FPGA, so that the FPGA can be flexibly and infinitely expanded, and the interconnection of the ultra-large-scale cluster FPGA is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first FPGA connected to a second FPGA in a prototype verification system of a very large scale clustered FPGA according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a first FPGA connected to a first FPGA in a prototype verification system of a very large scale clustered FPGA according to an embodiment of the present invention;
FIG. 3 is a flowchart of a method for interconnection coding of a very large scale cluster FPGA according to an embodiment of the present invention;
fig. 4 is a flowchart of a communication method of a very large scale cluster FPGA according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
Example 1
Embodiment one provides a very large scale clustered FPGA prototype experimentThe certification system comprises P interconnected first FPGAs { F 1 ,F 2 ,…,F p ,…,F P And Q second FPGAs, wherein F p And P is the P-th first FPGA, and the value range of P is 1 to P. The first FPGA comprises a switching module, M first ports and N second ports, any two ports in the first FPGA can communicate through the switching module, wherein any two ports can be any two first ports, any two second ports, or any one first port and any one second port. Each first port can be cascaded with a first FPGA, and each second port can be connected with a second FPGA, wherein Q is less than or equal to P multiplied by N.
The second FPGA comprises a third port, the third port is used for being interconnected with the second port, the second FPGA is used for loading chip design codes to be tested, the same chip design codes to be tested can be divided into Q parts, the Q parts are respectively stored in the Q second FPGAs, and prototype verification of the chip in the ultra-large-scale cluster FPGA is realized.
Any two second FPGAs connected to the same first FPGA can communicate through the corresponding second ports and the switching module. Each F p Can pass through the first port and the switching module and { F 1 ,F 2 ,…,F p ,…,F P Divide F in } p Any other first FPGA communicates. Each connected at F p Any one of the second FPGAs can pass through the corresponding second port, the switching module and { F } 1 ,F 2 ,…,F p ,…,F P Divide F in } p And any other second FPGA connected with any other first FPGA communicates.
As shown in the example of fig. 1, the first FPGA includes 4 first ports and 4 second ports, and each second port is connected to a second FPGA. As illustrated in the example of fig. 2, each first port of the first FPGA may be cascaded with one first FPGA. However, it can be understood that fig. 1 and fig. 2 are only examples, and in an actual ultra-large-scale cluster FPGA, the number of second FPGAs connected to each first FPGA may be adjusted according to application requirements, and the number and structure of first FPGAs cascaded by the first FPGA using the first port may also be adjusted according to specific application requirements.
As a preferred embodiment, the hardware structures of the first port, the second port, and the third port are the same. In the first FPGA, which ports are the first ports and which ports are the second ports may be specified by means of software configuration. The first port, the second port and the third port adopt the same hardware structure, so that the hardware design cost can be increased, and the interconnection efficiency and the communication efficiency among the ports are improved.
As one embodiment, the system further comprises a host connected with the main first FPGA, wherein the main first FPGA is { F } 1 ,F 2 ,…,F p ,…,F P One of the FPGAs, the host communicates with either one of the first FPGAs or the second FPGAs through the master first FPGA.
As an embodiment, the number of each first FPGA is set in sequence by taking the main first FPGA as a root node and adopting a depth-first algorithm, a Guangdong algorithm or a fixed coding mode. Preferably, the serial numbers of each first FPGA are set in sequence using a depth-first algorithm.
As an embodiment, the first port includes a first register, a second register and a third register, where the first register is used to store a first FPGA number where the first port is located, the second register is used to store a first FPGA number directly connected to the first port, and the third register is used to store a number of a farthest first FPGA connected to the first port, where a PCL code corresponding to the first port is formed by combining a value of the first register, a value of the second register and a value of the third register, and the PCL code corresponding to each first port can uniquely determine an address of the first port. It should be noted that, if the second port and the third port have the same structure as the first port, the first register, the second register, and the third register in the second port and the third port may be set to be empty or set to be an initial value of 0.
As an embodiment, the first FPGA further includes at least one first IP (Intellectual Property), the second FPGA further includes at least one second IP, the host sends a target communication instruction to the main first FPGA, the target communication instruction includes target address information and target communication information, the target address information includes a primary target address and a secondary target address, the primary target address is a number of the target first FPGA, and the number of the target first FPGA is a number of one of the first FPGAs. The second-level target address is a target second port number, a first IP identifier or a combination of the target second port number and the second IP identifier. The first target FPGA can be determined based on the first target FPGA number, the corresponding second target FPGA can be determined based on the second target port number, the first target IP corresponding to the first target FPGA can be determined based on the first IP identifier, and the second IP corresponding to the second target FPGA can be determined based on the second target port number and the second IP identifier.
As one embodiment, the system communicates the target communication to the target first FPGA based on the primary target address and PCL encoding of the first port, and communicates the target communication to the secondary target address based on the secondary target address.
The first FPGA is arranged in the system, the first FPGA can be cascaded, the first FPGA is cascaded through the first port, the second FPGA is connected through the second port, the chip to be tested design codes are loaded through the second FPGA, the system is high in expansibility, the number of the first FPGA can be expanded wirelessly, the number of the second FPGA is also increased infinitely, interconnection of ultra-large-scale cluster FPGAs is achieved, and the system is suitable for verification of current ultra-large-scale chip design.
The first embodiment may implement the configuration of the corresponding values in the first register, the second register, and the third register in the first port in any existing manner. However, due to the huge size of the FPGA, how to quickly and accurately configure the corresponding values in the first register, the second register and the third register in the first port is also challenging, and based on this, the embodiment of the present invention further provides the second embodiment.
Example two
The second embodiment provides a method for interconnection encoding of a very large scale cluster FPGA, and it should be noted that the method for interconnection encoding of a very large scale cluster FPGA provided in the second embodiment may be applied to the configuration of corresponding values in the first register, the second register, and the third register in the first port in the first embodiment, and may also be applied to other scenes of interconnection encoding of a large scale FPGA. It will be appreciated that, when applied to the configuration of the corresponding values in the first register, the second register and the third register in the first port in the first embodiment, the port in the second embodiment specifically refers to the first port in the first embodiment, and the FPGA in the second embodiment specifically refers to the first FPGA in the first embodiment.
The ultra-large cluster FPGA comprises P interconnected FPGAs { F } 1 ,F 2 ,…,F p ,…,F P }, wherein F p For the P-th FPGA, the value range of P is 1 to P, the FPGA comprises a switching module and M ports, two ports can communicate through the switching module, each port can be cascaded with one FPGA, and each F p Can at least communicate with { F through one port 1 ,F 2 ,…,F p ,…,F P Divide F in } p Any other FPGA except the first port is communicated, each port comprises a first register, a second register and a third register, the first register is used for storing an FPGA number P where the port is located, the second register is used for storing an FPGA number C where the port is directly connected, the third register is used for storing a number L of the furthest FPGA where the port is connected, and each first register, each second register and each third register are initially set to 0;
as shown in fig. 3, the method includes:
step C1, selecting F p As a main FPGA, the current number value r=1 is initially set with the main FPGA as a target FPGA.
The main FPGA can directly communicate with the host.
Step C2, obtaining a target FPGA port connection state sequence { A } 1 ,A 2 ,…,A m ,…,A M }，A m The connection state information of the mth port of the target FPGA is that the value range of M is 1 to M, M is the total number of ports of the FPGA, A m =（A1 m ,A2 m ），A1 m Is A m Connected state of A2 m Is A m Processing state of A) m =0 means a m Without connection with FPGA, A m =1 represents a m Is connected with FPGA, A2 m =0 means a m Untreated, A2 m =1 represents a m Treated, A2 m Initially set to 0.
Step C3, judging whether A1 exists in the current target FPGA port state sequence m =1 and A2 m Port=0, if present, from which one A1 is selected m =1 and A2 m And taking the port with the value of=0 as a target port, updating the FPGA connected with the target port into a target FPGA, executing the step C4, and otherwise, executing the step C5.
It should be noted that, A1 exists in the current target FPGA port state sequence m =1 and A2 m When port=0, it indicates that there is a port which is connected to the FPGA and is not processed in the current target FPGA.
Step C4, updating the values in all the first registers in the target FPGA to r, updating the values in the second registers in the target port to r, updating the values in the third registers in the target port and all the ports of the parent FPGA directly connected with the target port to r, and updating A2 corresponding to the target port m Set to a value of 1, then r=r+1 is updated, and the process returns to step C2.
It should be noted that, the ports of all parent FPGAs directly connected to the target port refer to all ports through which the shortest path from the target port to the master FPGA passes. Each first register and each second register need only be configured once, the value does not change after the configuration, and each third register can be configured for a plurality of times until all FPGAs are processed, and the final configuration value can not be obtained.
And C5, judging whether the target FPGA has a parent FPGA, if so, updating the parent FPGA into the target FPGA, and returning to execute the step C3, otherwise, ending the flow.
As an embodiment, the main FPGA is connected to a host, where the host is configured to generate a corresponding operation instruction based on a preset protocol structure, where the preset protocol structure includes { B1, B2, B3, B4, B5}, where B1 is an operation type identifier, b1=1 represents a read instruction, b1=2 represents a read reply instruction, b1=3 represents a write instruction, B2 is a target FPGA number, B3 is a target port number, B4 is a target IP number, and B5 is a target address and target data. It should be noted that, B1 may also be set to other values, which represent other types of instructions, such as a write reply instruction, may be specifically set according to the specific application requirements, and are not listed here. The target data in B5 may be null, for example, when b1=1, i.e., the corresponding read instruction type.
As an embodiment, the step C2 includes:
and C21, the host sets B1 and B2 in a preset protocol structure as a target FPGA number, sets B3 as a port number corresponding to the target FPGA in a parent FPGA, sets B4 as 0 and sets B5 as a port state register address in the target FPGA, and generates a target reading instruction.
When the target FPGA is the main FPGA, the target FPGA is the root node, and the port number corresponding to the target FPGA in the parent FPGA is set to 0. When the target address is not an address in IP, B4 is set to 0.
And step C22, determining a target reading FPGA based on the target reading instruction.
Step C23, reading an address corresponding to B5 in a target reading instruction in the target reading FPGA, and obtaining a target reading FPGA connection state sequence { A } 1 ,A 2 ,…,A m ,…,A M }。
Step C24, the target reading FPGA sets B1 in a preset protocol structure as 2, B2 as a main FPGA number, B3 as 0, B4 as a preset IP number and B5 as { A } 1 ,A 2 ,…,A m ,…,A M And generating a target read return instruction.
It should be noted that, all the read return instructions need to be sent to the preset IP corresponding to the main FPGA, the preset IP is a pre-designated IP for receiving the read return instruction, the host accesses the preset IP to obtain the target data carried by the read return instruction, and when accessing the main FPGA board, B2 is set to the number of the main FPGA, and B3 needs to be set to 0.
And step C25, determining the target read return FPGA based on the target read return instruction.
Step C26, will { A } 1 ,A 2 ,…,A m ,…,A M And storing the data in a preset IP corresponding to the target read return FPGA.
As an embodiment, the step C4 includes:
and C41, the host sets B1 in a preset protocol structure as 3, B2 as a target writing FPGA number, B3 as 0, B4 as 0 and B5 as a target writing register address and a target writing value in the target writing FPGA, and a target writing instruction is generated.
And step C42, determining a target writing FPGA based on the target writing instruction.
And step C43, updating the value in the target write register address into a target write value by the target write FPGA.
In step C4, "update the values in all the first registers in the target FPGA to r", "update the values in the second registers in the target port to r", and "update the values in the target port and the third registers in the ports of all the parent FPGAs directly connected to the target port to r" are all implemented by the steps of step C41 to step C43.
As an embodiment, in the step C4, the target writing FPGA is set as the target FPGA, the target writing register address is set as the first register address of the target FPGA, the target writing value is set as r, and the steps C41-C42 are executed to update the values in all the first registers in the target FPGA to r.
As an embodiment, in the step C4, the target writing FPGA is set as the FPGA where the target port is located, the target writing register address is set as the second register address in the target port, the target writing value is set as r, and the steps C41-C42 are executed to update the value in the second register in the target port to r.
In step C4, the target write FPGA is set as the FPGA where the target port is located or the FPGA where the port of the parent FPGA directly connected to the target port is located, the target write register address is set as the third register address in the port of the target port or the parent FPGA directly connected to the target port, the target write value is set as r, and steps C41-C42 are executed to update the values in the third registers in the ports of the target port and all the parent FPGAs directly connected to the target port to r.
Mainly described is that the host directly accesses the preset IP to enable the A2 corresponding to the target port m Set to a value of 1.
As an embodiment, the method further comprises:
and C10, setting the main FPGA as a receiving FPGA if the target instruction is a target reading instruction and a target writing instruction, and setting the target reading FPGA as the receiving FPGA if the target instruction is a target reading return instruction.
If the target instruction is a target read instruction and a target write instruction, the target instruction is generated by the host and sent from the host FPGA. If the target instruction is a target read return instruction, the target instruction is generated by the target read FPGA and sent from the target read FPGA.
And C20, analyzing the target instruction by the receiving FPGA, judging whether B2 is equal to P of the receiving FPGA and B3 is not 0, if B2 is equal to P of the receiving FPGA and B3 is not 0, executing step C30, if B2 is not equal to P of the receiving FPGA and B3 is not 0, judging whether B2 is not equal to C of the receiving FPGA and B2 is not equal to L of the receiving FPGA and P of the receiving FPGA is not equal to C of the receiving FPGA is not equal to 0, if B2 is not equal to C of the receiving FPGA and B2 is not equal to L of the receiving FPGA and C of the receiving FPGA is not equal to C of the receiving FPGA, executing step C40, if B2 is not equal to C of the receiving FPGA and B2 is not equal to L of the receiving FPGA and P of the receiving FPGA is not equal to C of the receiving FPGA is not equal to 0, judging whether B2 = P of the receiving FPGA is met and B2 = 0, if B2 = P of the receiving FPGA is not met and B2 = 0, executing step C < 50.
And step C30, updating B2 and B3 in the target instruction to 0, sending the updated target instruction to the corresponding next-stage FPGA through the port, updating the corresponding next-stage FPGA to the receiving FPGA, and returning to the step C23.
And C40, sending the target instruction to the corresponding next-stage FPGA through the port, updating the corresponding next-stage FPGA into a receiving FPGA, and returning to the step C20.
And step C50, updating the corresponding upper-stage FPGA to a receiving FPGA, and returning to the step C20.
It should be noted that, steps C22, C25 and C42 are all implemented by logic from step C10 to step C50.
In step C22, the target instruction is set as a target read instruction, and steps C10-C50 are performed, where the determined target execution FPGA is the target read FPGA.
In step C25, as an embodiment, the target instruction is set as a target read return FPGA, step C10-step C50 are performed, and the determined target execution FPGA returns the FPGA for the target read.
In step C42, as one embodiment, the target instruction is set as a target write instruction, and steps C10-C50 are performed, where the determined target execution FPGA is the target write FPGA.
According to the embodiment, the first register, the second register and the third register are arranged at each port, then the first register, the second register and the third register are configured in an iterative mode according to connection among FPGAs, finally the first register of each port stores the FPGA number P of the port, the second register stores the FPGA number C directly connected with the port, and the third register stores the number L of the furthest FPGA connected with the port, so that unique address codes are quickly and accurately arranged for each port, and the communication efficiency of the ultra-large-scale cluster FPGA is improved.
Based on the first embodiment and the second embodiment, the invention further provides a third embodiment, wherein the ultra-large-scale cluster FPGA can realize communication between FPGAs.
Example III
An embodiment III provides a communication method of a super-large cluster FPGA, wherein the super-large cluster FPGA comprises P interconnected first FPGAs { F } 1 ,F 2 ,…,F p ,…,F P }，Wherein F is p For the P first FPGA, the value range of P is 1 to P, the first FPGA comprises a switching module and M first ports, two first ports can communicate through the switching module, each first port can be cascaded with one first FPGA, and each F p Can pass through at least one first port and { F 1 ,F 2 ,…,F p ,…,F P Divide F in } p And any other first FPGA communicates, each first port is provided with a corresponding PCL code, and the PCL code comprises a first FPGA number P where the first port is located, a first FPGA number C directly connected with the first port and a number L of the furthest first FPGA connected with the first port.
As shown in fig. 4, the method includes:
step D1, the FPGA to be processed acquires a communication instruction generated based on a preset protocol structure, wherein the FPGA to be processed is { F } 1 ,F 2 ,…,F p ,…,F P One of the first FPGAs in the first FPGA, the preset protocol structure includes { B1, B2, B5}, where B1 is an operation type identifier, b1=1 represents a read instruction, b1=2 represents a read reply instruction, b1=3 represents a write instruction, B2 is a target first FPGA number, and B5 is a target address and target data.
And D2, judging whether a first port which satisfies B2 is more than or equal to C and B is less than or equal to L exists in the FPGA to be processed, if the first port which satisfies B2 is more than or equal to C and B is less than or equal to L exists, executing the step D3, if the first port which satisfies B2 is more than or equal to C and B is less than or equal to L does not exist, judging whether B2 is equal to P of the FPGA to be processed, if B2 is equal to P of the FPGA to be processed, determining the current FPGA to be processed as a first target communication FPGA, executing the step D5, if B2 is not equal to P of the FPGA to be processed, judging whether B2 is less than P of the FPGA to be processed, or if B2 is greater than L of the FPGA to be processed and B2 is not equal to P of the FPGA to be processed, executing the step D4.
In general, in step D2, it is determined that one of the conditions is satisfied and the corresponding step is executed, if none of the conditions is satisfied, an error is indicated, the error is directly reported, and the flow is ended.
And D3, sending the communication instruction to a first FPGA connected with the first port, updating the first FPGA connected with the first port into an FPGA to be processed, and returning to the step D2.
And D4, sending the communication instruction to a parent first FPGA of the FPGA to be processed, updating the parent first FPGA of the FPGA to be processed into the FPGA to be processed, and returning to the step D2.
It should be noted that, a main FPGA is designated in the oversized cluster FPGA, and the main FPGA is used as a root node, and then, in the shortest path from the FPGA to be processed to the main FPGA, the first FPGA adjacent to the FPGA to be processed is the parent first FPGA of the FPGA to be processed.
And D5, executing the communication instruction based on the first target communication FPGA.
It should be noted that, the ultra-large scale cluster FPGA implements a full duplex communication mode.
As an embodiment, the step D1 includes:
step D11, from { F 1 ,F 2 ,…,F p ,…,F P And selecting a first FPGA as a main FPGA, wherein the main FPGA is connected with a host.
The host communicates with any one of the ultra-large cluster FPGAs through the main FPGA.
And D12, the host generates a communication instruction based on a preset protocol structure, sends the communication instruction to the main FPGA, and sets the main FPGA as an FPGA to be processed.
As an embodiment, the oversized cluster FPGA further includes Q second FPGAs, the first FPGA further includes N second ports, any two ports in the first FPGA can communicate through the switch module, and each second port can be connected to one second FPGA, Q is less than or equal to p×n; the second FPGA comprises a third port, the third port is used for being interconnected with the second port, and the second FPGA is used for loading a chip to-be-tested design code; any two second FPGAs connected to the same first FPGA can communicate through the corresponding second ports and the switching module. Each F p Can pass through the first port and the switching module and { F 1 ,F 2 ,…,F p ,…,F P Divide F in } p Any one of the other firstAnd (5) FPGA communication. Each connected at F p Any one of the second FPGAs can pass through the corresponding second port, the switching module and { F } 1 ,F 2 ,…,F p ,…,F P Divide F in } p And any other second FPGA connected with any other first FPGA communicates.
As an embodiment, the preset protocol structure further includes B3, where B3 is a target second port number, and the step D5 includes:
and D51, if B3=0, executing the communication instruction in the first target communication FPGA, and if B3 is not equal to 0, determining a second FPGA connected with a second port corresponding to B3 in the first target communication FPGA as a second target communication FPGA.
And step D52, the communication instruction is sent to the second target communication FPGA, and the second target communication FPGA executes the communication instruction.
As an embodiment, the first FPGA further includes at least one first IP, the second FPGA further includes at least one second IP, the preset protocol structure further includes B4, B4 is a target IP number, if b3=0, B4 is set to a first IP identifier, and if b3+.0, B4 is set to a second IP identifier. Note that, if b3=0, access to the first target communication FPGA board is described. The corresponding IP is also the first target communication FPGA board IP, i.e. the first IP. If B3 is not equal to 0, the second FPGA connected with the first target communication FPGA board is accessed, and the corresponding IP is the second IP.
As an embodiment, in the step D51, the executing, at the first target communication FPGA, the communication instruction includes: and D511, in the first IP corresponding to the B4, the first target communication FPGA executes the operation of the type corresponding to the B1 based on the B5.
As an embodiment, in the step D52, the second target communication FPGA executes the communication instruction, including: and D521, the second target communication FPGA executes the operation of the type corresponding to B1 based on B5 in the second IP corresponding to B4.
As an embodiment, if b1=1 and b3=0 of the communication instruction, the step D5 is directly followed by the step D7, and if b1=1 and b3+.0 of the communication instruction, the step D5 is followed by the step D6;
and D6, transmitting the target read data read by the second target communication FPGA to the first target communication FPGA, and executing the step D7.
And D7, setting B1 in a read reply instruction as 2, B2 as a main FPGA number, B3 as 0, B4 as a number of a preset IP for interaction with a host, B5 as target read data, taking the first target communication FPGA as an FPGA to be processed, taking the read reply instruction as the communication instruction, and returning to the step D2.
It should be noted that, the second embodiment and the third embodiment may use two independent preset protocol structures. Since the difference between the preset protocol structures corresponding to the second embodiment and the third embodiment is only the meaning of B3, the same preset protocol structure may be shared, and the preset protocol structures specifically include { B0, B1, B2, B3, B4, B5}, where when b0=1, the preset protocol structure is set as the preset protocol structure used in the second embodiment, and when b0=0, the preset protocol structure is set as the data structure used in the third embodiment. Development costs can be saved by providing a common protocol structure for the second and third embodiments.
In the third embodiment, a PCL code is set at each first port, a communication instruction generated based on a preset protocol structure, and a to-be-processed FPGA receiving the communication instruction is rapidly determined based on the communication instruction and the PCL code until a first target communication FPGA is found, and the communication instruction is executed based on the first target communication FPGA, so that communication of the ultra-large-scale cluster FPGA can be rapidly and accurately achieved.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods described in embodiments two and three.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the methods described in the second and third embodiments of the invention.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.

Claims (8)

1. A prototype verification system for ultra-large-scale clustered FPGA is characterized in that,
first FPGA { F comprising P interconnections 1 ,F 2 ,…,F p ,…,F P And Q second FPGAs, wherein F p Is the p first FPGAThe value range of P is 1 to P;
the first FPGA comprises a switching module, M first ports and N second ports, any two ports in the first FPGA can communicate through the switching module, each first port can be cascaded with one first FPGA, each second port can be connected with one second FPGA, and Q is less than or equal to P multiplied by N;
the second FPGA comprises a third port, the third port is used for being interconnected with the second port, and the second FPGA is used for loading a chip to-be-tested design code;
any two second FPGAs connected to the same first FPGA can communicate through corresponding second ports and switching modules;
each F p Can pass through the first port and the switching module and { F 1 ,F 2 ,…,F p ,…,F P Divide F in } p Any one of the other first FPGAs is communicated;
each connected at F p Any one of the second FPGAs can pass through the corresponding second port, the switching module and { F } 1 ,F 2 ,…,F p ,…,F P Divide F in } p And any other second FPGA connected with any other first FPGA communicates.
2. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the hardware structures of the first port, the second port and the third port are the same.
3. The system of claim 1, wherein the system further comprises a controller configured to control the controller,
the system also comprises a host, wherein the host is connected with a main first FPGA, and the main first FPGA is { F } 1 ,F 2 ,…,F p ,…,F P One of the FPGAs, the host communicates with either one of the first FPGAs or the second FPGAs through the master first FPGA.
4. The system of claim 3, wherein the system further comprises a controller configured to control the controller,
and taking the main first FPGA as a root node, and sequentially setting the number of each first FPGA by adopting a depth-first algorithm, a Guangdong algorithm or a fixed coding mode.
5. The system of claim 4, wherein the system further comprises a controller configured to control the controller,
the first port comprises a first register, a second register and a third register, wherein the first register is used for storing a first FPGA number where the first port is located, the second register is used for storing a first FPGA number directly connected with the first port, the third register is used for storing the number of the furthest first FPGA connected with the first port, and the value of the first register, the value of the second register and the value of the third register corresponding to each first port are combined to form PCL codes corresponding to the first port.
6. The system of claim 5, wherein the system further comprises a controller configured to control the controller,
the first FPGA further comprises at least one first IP, the second FPGA further comprises at least one second IP, the host sends a target communication instruction to the main first FPGA, and the target communication instruction comprises target address information and target communication information.
7. The system of claim 6, wherein the system further comprises a controller configured to control the controller,
the target address information comprises a primary target address and a secondary target address, the primary target address is a target first FPGA number, and the secondary target address is a target second port number, a first IP identifier or a combination of the target second port number and a second IP identifier.
8. The system of claim 7, wherein the system further comprises a controller configured to control the controller,
the system transmits the target communication information to a target first FPGA based on a primary target address and PCL coding of a first port, and transmits the target communication information to a secondary target address based on a secondary target address.
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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020046324A1 (en) * 2000-06-10 2002-04-18 Barroso Luiz Andre Scalable architecture based on single-chip multiprocessing
JP2004157986A (en) * 2002-10-17 2004-06-03 Renesas Technology Corp Logical verification system and fpga module
WO2009039566A1 (en) * 2007-09-25 2009-04-02 Michael Reznik Reconfigurable numeric accelerator
CN102129418A (en) * 2011-03-07 2011-07-20 浪潮(北京)电子信息产业有限公司 High-performance fault-tolerant computer system and implementation method
CN110110355A (en) * 2019-03-25 2019-08-09 电子科技大学 A kind of Prototype Verification Platform based on FPGA
CN114218883A (en) * 2021-12-06 2022-03-22 上海航天计算机技术研究所 UVM-based AOS data processing FPGA simulation verification system
CN114860519A (en) * 2022-04-08 2022-08-05 中国人民解放军国防科技大学 Multi-chip combined verification method and device for large-scale ASIC (application specific integrated circuit) chip
CN115859906A (en) * 2023-03-01 2023-03-28 上海合见工业软件集团有限公司 Chip interconnection system
CN115913795A (en) * 2023-03-10 2023-04-04 湖南泛联新安信息科技有限公司 Encryption method and system based on multi-FPGA prototype verification hybrid cloud platform
CN116050346A (en) * 2023-02-02 2023-05-02 无锡中微爱芯电子有限公司 Verification system based on FPGA and implementation method
CN116796674A (en) * 2023-08-24 2023-09-22 上海合见工业软件集团有限公司 Heterogeneous hardware simulation method and system

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020046324A1 (en) * 2000-06-10 2002-04-18 Barroso Luiz Andre Scalable architecture based on single-chip multiprocessing
JP2004157986A (en) * 2002-10-17 2004-06-03 Renesas Technology Corp Logical verification system and fpga module
WO2009039566A1 (en) * 2007-09-25 2009-04-02 Michael Reznik Reconfigurable numeric accelerator
CN102129418A (en) * 2011-03-07 2011-07-20 浪潮(北京)电子信息产业有限公司 High-performance fault-tolerant computer system and implementation method
CN110110355A (en) * 2019-03-25 2019-08-09 电子科技大学 A kind of Prototype Verification Platform based on FPGA
CN114218883A (en) * 2021-12-06 2022-03-22 上海航天计算机技术研究所 UVM-based AOS data processing FPGA simulation verification system
CN114860519A (en) * 2022-04-08 2022-08-05 中国人民解放军国防科技大学 Multi-chip combined verification method and device for large-scale ASIC (application specific integrated circuit) chip
CN116050346A (en) * 2023-02-02 2023-05-02 无锡中微爱芯电子有限公司 Verification system based on FPGA and implementation method
CN115859906A (en) * 2023-03-01 2023-03-28 上海合见工业软件集团有限公司 Chip interconnection system
CN115913795A (en) * 2023-03-10 2023-04-04 湖南泛联新安信息科技有限公司 Encryption method and system based on multi-FPGA prototype verification hybrid cloud platform
CN116796674A (en) * 2023-08-24 2023-09-22 上海合见工业软件集团有限公司 Heterogeneous hardware simulation method and system

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
凌翔;胡剑浩;王剑;: "基于FPGA阵列的超大规模SoC验证平台", 系统仿真学报, no. 09, 5 May 2007 (2007-05-05), pages 1967 - 1970 *
郭叙海;: "多片大规模FPGA的ASIC原型验证平台快速设计方法", 中国集成电路, no. 12, 5 December 2010 (2010-12-05), pages 53 - 55 *

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