CN116663491B - Method, equipment and medium for covering group condition constraint statement based on BDD solving function - Google Patents
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Abstract
The invention relates to the technical field of chip verification, in particular to a method, equipment and medium for solving a functional coverage group condition constraint statement based on BDD, wherein the method comprises the following steps of S1, obtaining a target variable corresponding to a target condition constraint statement in the functional coverage group; step S2, obtaining each A n Corresponding bit number B n Determining the total number M of bits; s3, constructing M Boolean variables, and converting a target condition constraint statement into a target Boolean function represented by the M Boolean variables; s4, generating target BDDs based on M Boolean variables and target Boolean functions, wherein each path from a root node to a leaf True node in the target BDDs represents a group of variable values meeting target condition constraint statements; and S5, traversing each path from the root node to the leaf True node of the target BDD, and generating a target solution of the target condition constraint statement. The invention improves the solving efficiency of the conditional constraint statement of the functional coverage group.
Description
Technical Field
The invention relates to the technical field of chip verification, in particular to a method, equipment and medium for covering group condition constraint sentences based on BDD solving function.
Background
The functional coverage (functional coverage) module of the chip verification language system verilog is particularly important in the software emulation verification process of the chip, which involves verifying whether the design is working as intended. Verification engineers need to write a functional overlay group (overlay) to overlay data, address and control signals, etc. to verify whether the incentive is for its purpose. In writing the overlay points of a functional overlay group, it is often necessary to define conditional constraint statements (with expressions) of cross terms (cross) that are typically expressed as boolean expressions to ensure that the overlay points meet specific functional requirements. In the prior art, whether the coverage points or the cross terms meet the corresponding condition constraint statement needs to be judged one by one, and a great amount of time needs to be consumed, so that the solving efficiency of the condition constraint statement of the functional coverage group is low, and the chip verification efficiency is low. Therefore, how to improve the solving efficiency of the conditional constraint statement of the functional coverage group becomes a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a method, equipment and medium for constructing conditional constraint type functional coverage based on a binary decision diagram (binary decision diagram, BDD for short), which improves the solving efficiency of conditional constraint sentences of a functional coverage group and further improves the chip verification efficiency.
According to a first aspect of the present invention, there is provided a method for solving a functional coverage group conditional constraint statement based on BDD, comprising:
step S1, obtaining a target variable { A } corresponding to a target condition constraint statement in a function coverage group 1 ,A 2 ,…,A n ,…,A N }，A n N is the nth target variable corresponding to the target condition constraint statement, the value range of N is 1 to N, and the total number N of the target variables corresponding to the target condition constraint statement is more than or equal to 1;
step S2, obtaining each A n Corresponding bit number B n Determining a total number of bits；
S3, constructing M Boolean variables, wherein each Boolean variable corresponds to one bit in one target variable, and converting a target condition constraint statement into a target Boolean function represented by the M Boolean variables;
s4, generating target BDDs based on the M Boolean variables and the target Boolean function, wherein each path from a root node to a leaf True node in the target BDDs represents a set of variable values meeting target condition constraint sentences, and the BDDs are binary decision diagrams;
and S5, traversing each path from the root node to the leaf True node of the target BDD, acquiring a three-state character string corresponding to each path, and generating a target solution of the target condition constraint statement based on the three-state character string corresponding to each path.
According to a second aspect of the present invention, there is provided an electronic device comprising: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method according to the first aspect of the invention.
According to a third aspect of the present invention there is provided a computer readable storage medium storing computer executable instructions for performing the method of the first aspect of the present invention.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the method, the device and the medium for covering the group condition constraint statement based on the BDD solving function can achieve quite technical progress and practicality, have wide industrial utilization value, and have at least the following beneficial effects:
according to the invention, the Boolean variable is constructed based on the target variable, the target Boolean function is constructed based on the Boolean variable target condition constraint statement, the target BDD is generated based on the Boolean variable and the target Boolean function, the three-state character string corresponding to each path is acquired based on the path of the target BDD, the target solution of the target condition constraint statement is generated based on the three-state character string corresponding to each path, the path of the BDD is represented in a three-state character string mode, the number of the character strings required for representing all solutions can be reduced, the intermediate state can be represented in a concise and efficient manner, so that the compression characteristic of the BDD is better adapted, the time complexity of the process of processing the target condition constraint statement is greatly reduced, the required space is compressed, the solving efficiency of the condition constraint statement of the functional coverage group is improved, and the chip verification efficiency is further improved.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for covering a group condition constraint statement based on a BDD solving function according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a method for covering a group condition constraint statement based on a BDD solving function, which comprises the following steps as shown in figure 1:
step S1, obtaining a target variable { A } corresponding to a target condition constraint statement in a function coverage group 1 ,A 2 ,…,A n ,…,A N }，A n And the N-th target variable corresponding to the target condition constraint statement is the value range of N from 1 to N, and the total number N of the target variables corresponding to the target condition constraint statement is more than or equal to 1.
The chip verification simulation is divided into two phases, namely a chip verification compiling phase and a chip verification simulation phase, and before the step S1, the method can further comprise the following steps:
and S0, compiling based on a chip verification source code to obtain an executable file, wherein the chip verification source code comprises variable definitions and function coverage group definitions, and in the chip verification compiling stage, the variable definitions and the function coverage group definitions are transferred (dump) into a preset storage file.
It can be understood that, in the chip verification compiling stage, the variable definition and the functional coverage group definition dump need to be stored in a preset storage file for direct reading in the subsequent processing process.
As an embodiment, the step S1 includes:
and S11, in a chip verification simulation stage, reading the definition of the functional coverage group of the preset storage file, and acquiring a target variable corresponding to a target condition constraint statement in the functional coverage group.
Step S2, obtaining each A n Corresponding bit number B n Determining a total number of bits。
Wherein, the step S2 can acquire each A by storing variable definition of the file n Corresponding bit number B n 。
And S3, constructing M Boolean variables, wherein each Boolean variable corresponds to one bit in one target variable, and converting the target condition constraint statement into a target Boolean function represented by the M Boolean variables.
For example, there are two target variables, each corresponding to 8 bits, then 16 boolean variables each corresponding to one bit of the target variable need to be constructed. The target boolean function is a function that uses and, or, not, and exclusive or expressions. The existing mode of converting the conditional constraint statement into the boolean function falls within the protection scope of the present invention, and is not described herein.
And S4, generating target BDDs based on the M Boolean variables and the target Boolean function, wherein each path from the root node to the leaf True node in the target BDDs represents a set of variable values meeting the target condition constraint statement.
It should be noted that, there are two leaf nodes in the BDD, specifically, a leaf True node and a leaf false node, there are two types of paths in the BDD, and a path from the root node to the leaf True node in one type represents a set of variable values satisfying the constraint statement of the target condition; the other is a path from the root node to the leaf node, and the present invention only needs to pay attention to the path from the root node to the leaf True node, and thus only needs to generate the path from the root node to the leaf True node in the target BDD.
And S5, traversing each path from the root node to the leaf True node of the target BDD, acquiring a three-state character string corresponding to each path, and generating a target solution of the target condition constraint statement based on the three-state character string corresponding to each path.
As an embodiment, the step S4 includes:
and S41, setting a corresponding level for each Boolean variable, generating M Boolean variable levels, and constructing a mapping relation between each level and the bit of the target variable.
The mapping relation between each level and the bit of the target variable can be stored in a preset storage area, and the mapping relation can be directly read from the preset storage area in the subsequent use process.
And step S42, setting a bottom level at the bottoms of the M Boolean variable levels, and setting leaf True nodes at the bottom level.
It will be appreciated that a total of m+1 levels are included in the target BDD.
Step S43, setting corresponding state nodes at each level based on the target Boolean function, constructing directional connection lines between the state nodes along the direction from the root node to the leaf True node, and generating X paths { D from the root node to the leaf True node 1 ,D 2 ,…,D x ,…,D X -obtaining said target BDD, wherein D x For the xth path, the value range of X is 1 to X, X is the total number of paths in the target BDD, and the directional connecting line is a solid line or a broken line.
Wherein the directional connection line points from one layer of state nodes to the other layer of state nodes, and the nodes at two ends of the directional connection line can be positioned on two continuous layers; it is also possible to locate two discrete layers, i.e. a cross-layer connection. If the directional connection line is a solid line, the state value of the state node corresponding to the end point of the directional connection line is 1, and if the directional connection line is a broken line, the state value of the state node corresponding to the end point of the directional connection line is 0. If the layers are connected, the corresponding state value of the crossed layer in the path is 0 or 1.
As an embodiment, the step S5 includes:
step S51, traversing each D x If at D x If there is no state node corresponding to the mth level, the state corresponding to the mth level is set to "? ","? "indicates that the state corresponding to the mth hierarchy is 0 or 1, and if so, step S52 is executed.
Step S52, judging to be D x The type of the directional connection line taking the state node corresponding to the mth level as the starting point is set as '1' if the state node is a solid line, and the state corresponding to the mth level is set as '0' if the state node is a broken line, based on D x D is generated according to states corresponding to all levels in the hierarchy x Corresponding three-state character string (d 1 x ,d 2 x ,…,d m x ,…,d M x ），d m x For D x The corresponding state of the mth level in the corresponding three-state character string, d m x Equal to "0", "1" or "? ".
The D is represented by means of a three-state character string x The number of character strings required for representing all solutions can be reduced, intermediate states can be represented succinctly and efficiently, and compression characteristics of BDDs can be better adapted.
Step S53, based on D x And generating a target solution of the target condition constraint statement according to the corresponding three-state character string and the mapping relation between each level and the bit of the target variable.
Wherein, based on the mapping relation between each level and the bit of the target variable, and D x The corresponding three-state string can determine the value of each bit of the target variable, thereby obtaining the target solution of the target condition constraint statement.It should be noted that, if the ".
As an embodiment, in step S41, a corresponding hierarchy is set for each boolean variable in a random order. Correspondingly, in the step S53, a value of each bit of each target variable is determined based on the mapping relationship between each level and the bit of the target variable, and a target solution of the target condition constraint statement is generated.
As an embodiment, n=1, that is, the target condition constraint statement corresponds to only one target variable, in the step S41, a corresponding hierarchy is set for each boolean variable according to the order of the bits of the target variable; correspondingly, in step S53, D x The corresponding three-state character string is the target solution of the target condition constraint statement.
In a preferred embodiment, N >1, that is, the target condition constraint statement corresponds to a plurality of target variables, in step S41, a corresponding hierarchy is set for each boolean variable in such a way that N target variable bits are alternately set, so that the calculation amount can be reduced in the process of generating the target BDD, and the construction efficiency of the target BDD can be improved. In the step S53, a value of each bit of each target variable is determined based on the mapping relationship between each hierarchy and the bit of the target variable, and a target solution of the target condition constraint statement is generated.
As an embodiment, the step S53 includes:
step S531, based on D x And generating the effective value of the target variable according to the corresponding three-state character string and the mapping relation between each level and the bit of the target variable.
Step S532, if the type of the target solution is the coverage point value or the cross item value, the effective value of the target variable is directly determined as the target solution of the target condition constraint statement, and if the type of the target solution is the coverage point bin or the bin cross item generated based on the coverage point bin, step S533 is executed.
Step S533, acquiring candidate coverage point bins or candidate bin cross terms generated based on the coverage point bins, solving intersection of an effective value set of target variables consisting of effective values of all target variables and the candidate coverage point bins or candidate bin cross terms, determining the candidate coverage point bins or candidate bin cross terms with the intersection as target solutions, and eliminating the candidate coverage point bins or candidate bin cross terms without the intersection.
As an embodiment, in the step S533, acquiring the candidate coverage point bin includes:
step S501, initially set n=1, and step S502 is executed.
Step S502, if A n There is corresponding internal constraint information, step S503 is performed.
The internal constraint definition is arranged in the functional coverage group definition, and the internal constraint definition comprises a variable identifier, a variable constraint range corresponding to the variable identifier and/or the number of variable bins.
Step S503, based on A n Corresponding variable definition range information, internal constraint information and bin division identification in the internal constraint information to generate A n Corresponding bin sets, each A n The corresponding bin at least comprises one numerical value, if n=n, the process is ended, if N<N, n=n+1 is set, and the process returns to step S502.
If the candidate bin cross item generated based on the bin of the coverage point needs to be acquired in step S502, in step S503, if n=n, the method further includes: step S504, based on all A n And combining the corresponding bin sets to generate candidate bin cross items generated by the bins of the coverage points.
Wherein, as an example, there are two target variables, specifically, a and b, the bin set of a generated in step S503 is { bin a [1], bin a [2] }, the bin set of b generated is { bin b [1], bin b [2] }, and the candidate bin cross item generated based on the bin of the coverage point is generated in step S504 as bin a [1], bin b [1]; bin a [1], bin b [2]; bin a 2, bin b 1; bin a 2, bin b 2.
As an embodiment, in the step S503, a is based on n Corresponding variable definition range information, internal constraint information and bin division identification generation in the internal constraint informationA n A corresponding set of bins, comprising:
step S5031, if A n If the corresponding internal constraint information does not include the variable constraint range, then A is n Corresponding variable definition range information is determined to be A n Corresponding variable constraint ranges.
Namely, setting a corresponding variable constraint range in the internal constraint, dividing the range of the bin by taking the variable constraint range as a variable, and if the variable constraint range is not set, setting A n The corresponding variable defines the range as A n Corresponding variable constraint ranges. It should be noted that, the variable constraint range is less than or equal to the variable definition range.
Step S5032, if A n The corresponding internal constraint information comprises a first class bin partition identification bin A n [b n ]，b n Is A n Corresponding variable bin number, will A n D in the corresponding variable constraint range n The numerical value is evenly divided into b n In each bin, generate A n Corresponding b n The number of bins d n Is A n The number of values within the corresponding variable constraint range.
Step S5033, if A n The corresponding internal constraint information comprises a second class bin partition identification bin A n Will A n D in the corresponding variable constraint range n The number value is divided into A n In the corresponding bin set.
Step S5034, if A n The corresponding internal constraint information comprises a third class bin partition identification bin []Will A n Each value in the corresponding variable constraint range is independently divided into one A n Generating d in the corresponding bin set n A A is that n A corresponding set of bins. I.e. there is only one value in each bin.
Step S5031 needs to be performed before step S5032, step S5033, and step S5034, and step S5032, step S5033, and step S5034 may be performed in parallel or may be performed in the order of interchange.
As an example, in the step S502, if a n If there is no corresponding internal constraint information, then executingLine step S5020:
step S5020, step A n The corresponding numerical values in the variable constraint range are evenly divided into C bins to generate A n Corresponding C bins, C is the preset default bin number, if n=n, execute step S504, if N<N, n=n+1 is set, and the process returns to step S502.
By setting internal constraint information, candidate coverage point bins or candidate bin cross terms generated based on the coverage point bins can be quickly and accurately acquired, and then a target solution with the type of coverage point value or cross term value can be generated by combining the effective value of the target variable.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
According to the embodiment of the invention, the Boolean variable is constructed based on the target variable, the target Boolean function is constructed based on the target condition constraint statement of the Boolean variable, the target BDD is generated based on the Boolean variable and the target Boolean function, the three-state character string corresponding to each path is acquired based on the path of the target BDD, the target solution of the target condition constraint statement is generated based on the three-state character string corresponding to each path, the path of the BDD is represented in the three-state character string mode, the number of the character strings required for representing all solutions can be reduced, the intermediate state can be expressed simply and efficiently, the compression characteristic of the BDD is better adapted, the time complexity of the process of processing the target condition constraint statement is greatly reduced, the required space is compressed, the solving efficiency of the condition constraint statement of the functional coverage group is improved, and the chip verification efficiency is further improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.
Claims (6)
1. A method for solving a functional coverage group conditional constraint statement based on BDD, comprising:
step S1, obtaining a target variable { A } corresponding to a target condition constraint statement in a function coverage group 1 ,A 2 ,…,A n ,…,A N }，A n N is the nth target variable corresponding to the target condition constraint statement, the value range of N is 1 to N, and the total number N of the target variables corresponding to the target condition constraint statement is more than or equal to 1;
step S2, obtaining each A n Corresponding bit number B n Determining a total number of bits；
S3, constructing M Boolean variables, wherein each Boolean variable corresponds to one bit in one target variable, and converting a target condition constraint statement into a target Boolean function represented by the M Boolean variables;
s4, generating target BDDs based on the M Boolean variables and the target Boolean function, wherein each path from a root node to a leaf True node in the target BDDs represents a set of variable values meeting target condition constraint sentences, and the BDDs are binary decision diagrams;
step S5, traversing each path from the root node to the leaf True node of the target BDD, acquiring a three-state character string corresponding to each path, and generating a target solution of a target condition constraint statement based on the three-state character string corresponding to each path;
the step S4 includes:
step S41, setting a corresponding level for each Boolean variable, generating M Boolean variable levels, and constructing a mapping relation between each level and the bit of the target variable;
step S42, setting a bottom level at the bottoms of the M Boolean variable levels, wherein the bottom level is provided with leaf True nodes;
step S43, setting corresponding state nodes at each level based on the target Boolean function, constructing directional connection lines between the state nodes along the direction from the root node to the leaf True node, and generating X paths { D from the root node to the leaf True node 1 ,D 2 ,…,D x ,…,D X -obtaining said target BDD, wherein D x For the xth path, the value range of X is 1 to X, and the directional connecting line is a solid line or a broken line;
the step S5 includes:
step S51, traversing each D x If at D x If there is no state node corresponding to the mth level, the state corresponding to the mth level is set to "? ","? "indicates that the state corresponding to the mth level is 0 or 1, if yes, executing step S52, where the value range of M is 1 to M;
step S52, judging to be D x The type of the directional connection line taking the state node corresponding to the mth level as the starting point is set as '1' if the state node is a solid line, and the state corresponding to the mth level is set as '0' if the state node is a broken line, based on D x D is generated according to states corresponding to all levels in the hierarchy x Corresponding three-state character string (d 1 x ,d 2 x ,…,d m x ,…,d M x ），d m x For D x The corresponding state of the mth level in the corresponding three-state character string, d m x Equal to "0", "1" or "? ";
step S53, based on D x Generating a target solution of a target condition constraint statement according to the corresponding three-state character string and the mapping relation between each level and the bit of the target variable;
the step S53 includes:
step S531, based on D x Generating an effective value of the target variable according to the corresponding three-state character string and the mapping relation between each level and the bit of the target variable;
step S532, if the type of the target solution is the coverage point value or the cross item value, directly determining the effective value of the target variable as the target solution of the target condition constraint statement, and if the type of the target solution is the coverage point bin or the bin cross item generated based on the coverage point bin, executing step S533;
step S533, acquiring candidate coverage point bins or candidate bin cross terms generated based on the coverage point bins, solving intersection of an effective value set of target variables consisting of effective values of all target variables and the candidate coverage point bins or candidate bin cross terms, determining the candidate coverage point bins or candidate bin cross terms with the intersection as target solutions, and eliminating the candidate coverage point bins or candidate bin cross terms without the intersection.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
in step S41, a corresponding hierarchy is set for each boolean variable according to a random sequence;
in the step S53, a value of each bit of each target variable is determined based on the mapping relationship between each hierarchy and the bit of the target variable, and a target solution of the target condition constraint statement is generated.
3. The method of claim 1, wherein the step of determining the position of the substrate comprises,
n=1, in the step S41, a corresponding hierarchy is set for each boolean variable according to the order of the target variable bits;
in step S53, D x The corresponding three-state character string is the target solution of the target condition constraint statement.
4. The method of claim 1, wherein the step of determining the position of the substrate comprises,
n >1, in the step S41, a corresponding hierarchy is set for each boolean variable in a manner of alternately setting N target variable bits;
in the step S53, a value of each bit of each target variable is determined based on the mapping relationship between each hierarchy and the bit of the target variable, and a target solution of the target condition constraint statement is generated.
5. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-4.
6. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-4.
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| US6389374B1 (en) * | 1998-06-03 | 2002-05-14 | Fujitsu Limited | OBDD variable ordering using sampling based schemes |
| CN102411534A (en) * | 2011-07-25 | 2012-04-11 | 中国科学院声学研究所 | Breakpoint debugging method and debugger |
| CN103645930A (en) * | 2013-12-18 | 2014-03-19 | 中国科学院声学研究所 | Method for establishing assemble level cross-file scheduling framework |
| CN105302573A (en) * | 2015-11-20 | 2016-02-03 | 浪潮集团有限公司 | Method for establishing function point matching setting automation platform for function verification platform |
| CN113378009A (en) * | 2021-06-03 | 2021-09-10 | 上海科技大学 | Binary neural network quantitative analysis method based on binary decision diagram |
| CN113868061A (en) * | 2021-09-29 | 2021-12-31 | 深圳大普微电子科技有限公司 | Chip verification method and device and server |
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