CN113868061A - Chip verification method and device and server - Google Patents
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Abstract
The embodiment of the application relates to the technical field of chips, and discloses a chip verification method, a device and a server, wherein the chip verification method comprises the following steps: acquiring a functional coverage rate model; determining all functional points needing to be covered according to the functional coverage rate model; generating a regression file according to all functional points needing to be covered, wherein the regression file comprises: test cases of all the functional points; performing regression testing based on the regression file; and counting the function coverage rate to confirm that the function coverage rate meets the preset requirement. By utilizing the function coverage rate model, all function points needing to be covered are determined, and a regression file is generated, wherein the regression file comprises test cases of all the function points so as to perform regression testing.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a chip verification method, an apparatus, and a server.
Background
Along with the continuous increase of chip design scale, functions become more and more complex, and the complexity of chip verification is greatly improved, which gradually becomes one of the bottlenecks restricting chip design.
The conventional authentication method includes: a method for artificially developing directional test cases and a constrained random verification method. The method for manually developing the directional test case is low in efficiency, and completeness of a verification result is not fully guaranteed. And the constrained random verification method needs to perform multiple rounds of regression simulation iteration, still cannot cover all the function points by 100%, and needs to analyze uncovered function points after multiple rounds of regression and then perform manual supplement test case coverage. The biggest drawback of constrained random verification methods is that coverage of all functions cannot be done in the fastest time. Meanwhile, when the chip scale is large and the number of function points is large, a large number of repeated function points are often randomly obtained through multiple rounds of regression, and resources of the server are wasted.
In the process of implementing the embodiment of the invention, the inventor finds that the related technology has at least the following problems: the test time of chip verification is long and the efficiency is insufficient due to the multi-round regression simulation iteration mode.
Disclosure of Invention
The embodiment of the application provides a chip verification method, a chip verification device and electronic equipment, which solve the technical problem of low efficiency of the existing chip verification and improve the chip verification efficiency.
In order to solve the above technical problem, an embodiment of the present application provides the following technical solutions:
in a first aspect, an embodiment of the present application provides a chip verification method, where the method includes:
acquiring a functional coverage rate model;
determining all functional points needing to be covered according to the functional coverage rate model;
generating a regression file according to all functional points needing to be covered, wherein the regression file comprises: test cases of all the functional points;
performing a regression test based on the regression file;
and counting the function coverage rate to confirm that the function coverage rate meets the preset requirement.
In some embodiments, the determining all functional points that need to be covered according to the functional coverage rate model includes:
determining a coverage bin corresponding to each variable in the functional coverage rate model;
determining cross coverage bins corresponding to all variables in the functional coverage rate model;
and counting the total number of the functional points in each cross covering bin according to the cross covering bins, and determining the maximum value of the total number of the functional points.
In some embodiments, after generating the regression file, the method further comprises:
setting an array or a queue for each covering bin, wherein the array or the queue is used for storing the corresponding function point of the covering bin;
determining the value quantity of the use case control parameters according to the quantity of the numerical values corresponding to each variable;
calculating a parameter index value corresponding to each variable according to the value number of the use case control parameters;
selecting a parameter value from an array or a queue corresponding to each covering bin according to the parameter index value;
and configuring parameters in the test case according to the selected parameter values.
In some embodiments, the method further comprises:
after the parameters in the test cases are configured, a case parameter analysis file is generated, wherein the case parameter analysis file comprises the parameters in all the test cases.
In some embodiments, said performing a regression test based on said regression file comprises:
configuring corresponding parameters for each test case in the regression file through the case parameter analysis file to generate a regression file with configured parameters;
and performing regression testing based on the regression file of the configuration parameters.
In some embodiments, the obtaining the functional coverage model comprises:
acquiring a functional coverage rate model file;
and acquiring a functional coverage rate model according to the functional coverage rate model file.
In some embodiments, the preset requirements include a functional coverage of up to 100%.
In a second aspect, an embodiment of the present application provides a chip verification apparatus, where the apparatus includes:
the functional coverage rate model obtaining module is used for obtaining a functional coverage rate model;
the function point determining module is used for determining all function points needing to be covered according to the function coverage rate model;
the regression file generation module is used for generating a regression file according to all the function points to be covered, wherein the regression file comprises: test cases of all the functional points;
the regression testing module is used for carrying out regression testing based on the regression file;
and the function coverage rate counting module is used for counting the function coverage rate so as to confirm that the function coverage rate meets the preset requirement.
In a third aspect, an embodiment of the present application provides a server, including:
at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the chip verification method according to the first aspect.
In a fourth aspect, embodiments of the present application provide a non-transitory computer-readable storage medium storing computer-executable instructions for enabling a server to perform the chip verification method according to the first aspect.
The beneficial effects of the embodiment of the application are that: in contrast to the prior art, an embodiment of the present application provides a chip verification method, where the method includes: acquiring a functional coverage rate model; determining all functional points needing to be covered according to the functional coverage rate model; generating a regression file according to all functional points needing to be covered, wherein the regression file comprises: test cases of all the functional points; performing a regression test based on the regression file; and counting the function coverage rate to confirm that the function coverage rate meets the preset requirement. Determining all functional points needing to be covered by utilizing a functional coverage rate model, and generating a regression file, wherein the regression file comprises: the test cases of all the function points are used for carrying out regression test, iteration times can be reduced, the function coverage rate of preset requirements can be met, and the chip verification efficiency is improved.
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One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic flow diagram of a constrained random verification method in the prior art;
fig. 2 is a schematic flowchart of a chip verification method according to an embodiment of the present application;
FIG. 3 is a schematic flow chart diagram illustrating another chip verification method according to an embodiment of the present disclosure;
FIG. 4 is a detailed flowchart of step S32 in FIG. 3;
FIG. 5 is a schematic flowchart illustrating configuring parameters in a test case according to an embodiment of the present application;
fig. 6 is a schematic flowchart of another chip verification method provided in an embodiment of the present application;
FIG. 7a is a functional point coverage trend graph of a constrained random verification method in the prior art;
FIG. 7b is a functional point coverage trend graph in the embodiment of the present application;
fig. 8 is a schematic structural diagram of a chip verification apparatus according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a server according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In addition, the technical features mentioned in the embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, fig. 1 is a flow chart illustrating a constrained random verification method in the prior art;
as shown in fig. 1, the constrained random verification method includes:
starting;
step S101: using a random use case;
step S102: performing regression testing;
step S103: counting functional coverage rate;
step S104: judging whether the functional coverage rate reaches 100%;
finishing;
it can be seen that the constrained random verification method needs to perform multiple rounds of regression simulation iteration, may still not cover all the function points by 100%, and needs to analyze the uncovered function points after multiple rounds of regression, and then perform manual supplementary test case coverage. The biggest drawback of constrained random verification methods is that coverage of all functions cannot be done in the fastest time. Meanwhile, when the chip scale is large and the number of function points is large, a large number of repeated function points are often randomly reached by multiple rounds of regression, which results in waste of server resources.
Based on this, the embodiment of the application provides a chip verification method to improve the efficiency of chip verification.
Specifically, please refer to fig. 2, fig. 2 is a schematic flow chart of a chip verification method according to an embodiment of the present disclosure;
as shown in fig. 2, the chip verification method includes:
step S21: analyzing the functional coverage rate model;
specifically, the functional coverage model is analyzed using a scripting tool, wherein the scripting tool includes, but is not limited to: perl script, tcl script, Python script, and other scripting tools.
Step S22: generating all test cases;
specifically, a script tool is used to generate all test cases.
Step S23: performing regression testing;
specifically, a regression simulation test (regression simulation) is performed.
Step S24: counting the functional coverage rate, and confirming that the functional coverage rate meets the preset requirement;
specifically, the function coverage rate is counted, so that the function coverage rate meets a preset requirement, wherein the preset requirement is that the function coverage rate is 100%.
Further, please refer to fig. 3, fig. 3 is a schematic flow chart of another chip verification method according to an embodiment of the present application;
the chip verification method is applied to a server, and in particular, to one or more processors of the server, that is, an execution subject of the chip verification method is the one or more processors of the server.
As shown in fig. 3, the chip verification method includes:
step S31: acquiring a functional coverage rate model;
specifically, the obtaining the functional coverage rate model includes: acquiring a functional coverage rate model file; and acquiring a functional coverage rate model according to the functional coverage rate model file. Wherein the functional coverage model is used to identify all functional points.
Step S32: determining all functional points needing to be covered according to the functional coverage rate model;
specifically, referring back to fig. 4, fig. 4 is a detailed flowchart of step S32 in fig. 3;
as shown in fig. 4, the step S32: determining all functional points needing to be covered according to the functional coverage rate model, including:
step S321: determining a coverage bin corresponding to each variable in the functional coverage rate model;
specifically, the functional coverage rate model includes at least one variable, and each variable corresponds to at least one numerical value, for example: the variable A corresponds to 0,1 …, m-1 is m values, the variable B corresponds to 0,1 …, n-1 is n values, and the variable C corresponds to 0,1 …, j-1 is k values; the variable D corresponds to 0,1 …, p-1 for p values, and the variable E corresponds to 0,1 …, q-1 for q values. Wherein, three variables A, B and C need to be cross-covered, and variables D and E need to be cross-covered.
Let m be 3, n be 2, and k be 2, in which case the variable a corresponds to a coverage bin that includes three values {10,20,30}, the variable B corresponds to a coverage bin that includes two values {100, 200}, and the variable C corresponds to a coverage bin that includes two values {1000, 2000}, in other words, three values 10,20,30 need to be covered for the variable a, {10,20,30} is a coverage bin for the variable a, and similarly {100, 200} is a coverage bin for the variable B, and {1000, 2000} is a coverage bin for the variable C.
Let p be 4 and q be 2, in this case, the variable D corresponds to a coverage bin including four values of {50,60,70,80}, and the variable E corresponds to a coverage bin including two values of {500, 600}, in other words, it is necessary for the variable D to cover four values of 50,60,70,80, {50,60,70,80} which is the coverage bin of the variable D, and similarly, {500, 600} which is the coverage bin of the variable E.
It is understood that each variable corresponds to a covering bin, each covering bin comprises at least one numerical value, each numerical value is a covering point, and each variable needs to cover all the numerical values in the covering bin, that is, each variable needs to cover all the covering points in the covering bin.
Step S322: determining cross coverage bins corresponding to all variables in the functional coverage rate model;
specifically, for each variable, in addition to all coverage points of the coverage bin corresponding to the variable, coverage points of other variables also need to be covered, so that a cross coverage bin is formed, and the cross coverage bin comprises a plurality of cross coverage points obtained by arranging and combining at least two variables.
As shown in table 1 below, it is assumed that variables a, B, and C collectively cover total ═ m.n.k, where m ═ 3, n ═ 2, and k ═ 2, i.e., collectively cover 3x2x2 ═ 12 cases. Where m has three cases, assuming three values of {10,20,30}, n has two cases, assuming two values of {100, 200}, and k has two cases, assuming two values of {1000, 2000 }.
For three values of m needed to cover 10,20,30, {10,20,30} is the covering bin of m, similarly, {100, 200} is the covering bin of n, and {1000, 2000} is the covering bin of k.
For each variable, in addition to covering the bins described above, the following cross-coverage points need to be covered. The 12 crossed covering points obtained by the following arrangement and combination form a crossed covering bin.
TABLE 1
As shown in table 2 below, it is assumed that variables D and E need to cover total p.q cases, where p is 4 and q is 2, i.e. 4x2 is 8 cases. Where p has four cases, assuming four values of 50,60,70,80, and q has two cases, assuming two values of 500, 600.
For D needs to cover four values of 50,60,70,80, {50,60,70,80} is the coverage bin for D, and similarly, {500, 600} is the coverage bin for E.
For variable D and variable E, each variable needs to cover the following cross-coverage points in addition to the above-mentioned coverage bins. The following 8 crossed covering points are arranged and combined to form a crossed covering bin.
| Numbering | p | q |
| 0 | 50 | 500 |
| 1 | 50 | 600 |
| 2 | 60 | 500 |
| 3 | 60 | 600 |
| 4 | 70 | 500 |
| 5 | 70 | 600 |
| 6 | 80 | 500 |
| 7 | 80 | 600 |
TABLE 2
Step S323: and counting the total number of the functional points in each cross covering bin according to all the cross covering bins, and determining the maximum value of the total number of the functional points.
Specifically, according to all the cross coverage points in the cross coverage bins, the total number of the function points in each cross coverage bin is counted, the maximum value of the total number of the function points is determined, and all the function points corresponding to the maximum value of the total number of the function points are determined as all the function points to be covered, wherein each cross coverage point in the cross coverage bin is one function point to be covered, that is, one coverage point is one function point, and all the function points to be covered can be determined by the cross coverage points in the cross coverage bins.
Wherein, the crossing coverage points of the three variables A, B and C are m × n × k in total, the crossing coverage points of the two variables D and E are p × q in total, the magnitudes of m × n × k and p × q are compared, and the maximum value of the two is taken as the maximum value Vmax of the total number of the functional points. As described above, since m × n × k is 12 and p × q is 8, the maximum value Vmax of the total number of functional points is m × n × k is 12.
Step S33: generating a regression file according to all functional points needing to be covered, wherein the regression file comprises: test cases of all the functional points;
specifically, a test case is generated for each functional point to be covered, and multiple test cases are combined to generate a regression file, where the regression file includes: test cases of all functional points, wherein the test cases are generated by a script tool, for example: perl script, tcl script, Python script, and other scripting tools.
For example: assume that a total of m.n.k, where m is 3, n is 2, and k is 2, i.e., a total of 3x2x2 is required to be covered 12. The script needs to generate 12 test cases in total, and each case is different except that one parameter needs to be transmitted, and the other cases are the same. That is to say, to cover 12 cases, it is necessary to generate test0 and test1 … test11 through scripts, and the 12 use cases respectively deliver parameters 0,1 and 2 … 11.
In the embodiment of the present application, after generating the regression file, parameters in the test case also need to be configured, specifically, please refer to fig. 5, where fig. 5 is a schematic flow diagram for configuring parameters in the test case provided in the embodiment of the present application;
as shown in fig. 5, the process of configuring parameters in a test case includes:
step S501: setting an array or a queue for each covering bin, wherein the array or the queue is used for storing the corresponding function point of the covering bin;
specifically, each covering bin is allocated with an array or a queue one by one, and each array or each queue is used for storing all the function points, namely the covering points, in the corresponding covering bin.
Step S502: determining the value quantity of the use case control parameters according to the quantity of the numerical values corresponding to each variable;
specifically, assume that a chip project includes A, B, C, D, E five variables, where variable a needs to cover m values of 0,1 …, m-1, variable B needs to cover n values of 0,1 …, n-1, variable C needs to cover k values of 0,1 …, k-1, variable D needs to cover p values of 0,1 …, p-1, and variable E needs to cover q values of 0,1 …, q-1. And A, B and C, the three variables need cross coverage, and the two variables D and E need cross coverage. In the case where the maximum value Vmax ═ m × n × k, the number of values of the use case control parameter is determined to be m × n × k, which is in the range of [0, (m × n × k) -1 ].
Step S503: calculating a parameter index value corresponding to each variable according to the value number of the use case control parameters;
specifically, it is assumed that m is 3, n is 2, k is 2, and m has three values of {10,20,30 }; n has two cases, take two values of 100, 200; k has two cases, namely two values of {1000, 2000}, the value range of the case control parameter val is [0, 11], and there are 12 cases in total.
Assuming that p is 4, q is 2, and p has four cases, taking four values of {50,60,70,80 }; q has two cases, take two values of 500, 600; the value range of the case control parameter val is [0, 11], and there are 12 cases in total.
Determining a parameter index value corresponding to each variable according to the use case control parameters, wherein the parameter index value comprises the following steps:
determining the number of values of each variable, and determining a parameter index value corresponding to each variable corresponding to each use-case control parameter according to the number of values of each variable, wherein for a use-case control parameter val, at this time, for a parameter m, the parameter index value m _ idx is (val/(n × k))% m, for a parameter n, the parameter index value n _ idx is (val/(k))% n, for a parameter k, the parameter index value k _ idx is val% k, for a parameter p, the parameter index value p _ idx is (val/(q))% p, and for a parameter q, the parameter index value q _ idx is val% q,% is a remainder operation.
For example:
when val is 0, for m, idx is (val/(2 × 2))% 3 is 0, i.e., the 0 th value of m is 10;
when val is 0, for n, idx is (val/2)% 2 is 0, i.e. the 0 th value of n is taken as 100;
when val is 0, for k, idx is 0, i.e. the 0 th value of k is 1000;
when val is 0, for p, idx is (val/2)% 4 is 0, i.e. the 0 th value of p is taken as 50;
when val is 0, for q, idx is 0, i.e. the 0 th value of q is 500;
and so on;
when val is 4, for m, idx is (val/(2 × 2))% 3 is 1, i.e., the 1 st value of m is 20;
when val is 4, for n, idx is (val/2)% 2 is 0, i.e. the 0 th value of n is taken as 100;
when val is 4, for k, idx is 0, that is, the 0 th value of k is 1000;
when val is 4, for p, idx is (val/2)% 4 is 0, i.e. the 2 nd value of p is 70;
when val is 4, for q, idx is 0, that is, the 0 th value of q is 500;
and so on;
when val is 5, for m, idx is (val/(2 × 2))% 3 is 1, i.e., the 1 st value of m is 20;
when val is 5, for n, idx is (val/2)% 2 is 0, i.e. the 0 th value of n is taken as 100;
when val is 5, for k, idx is 1, i.e. the 1 st value of k is 2000;
when val is 5, for p, idx is (val/2)% 4 is 0, i.e. the 2 nd value of p is 70;
when val is 5, for q, idx is 1, i.e. the 1 st value of q is 600;
and so on;
when val is 11, for m, idx is (val/(2 × 2))% 3 is 2, i.e., the 2 nd value of m is 30;
when val is 11, for n, idx is (val/2)% 2 is 1, i.e. the 1 st value of n is 200;
when val is 11, for k, idx is 1, i.e. the 1 st value of k is 2000.
When val is 11, for p, idx is (val/2)% 4 is 1, i.e. the 1 st value of p is 60;
when val is 11, for q, idx is 1, that is, the 1 st value of q is 600;
as shown in table 3 and table 4 below:
| val | m | n | k |
| 0 | 10 | 100 | 1000 |
| 1 | 10 | 100 | 2000 |
| 2 | 10 | 200 | 1000 |
| 3 | 10 | 200 | 2000 |
| 4 | 20 | 100 | 1000 |
| 5 | 20 | 100 | 2000 |
| 6 | 20 | 200 | 1000 |
| 7 | 20 | 200 | 2000 |
| 8 | 30 | 100 | 1000 |
| 9 | 30 | 100 | 2000 |
| 10 | 30 | 200 | 1000 |
| 11 | 30 | 200 | 2000 |
TABLE 3
TABLE 4
Step S504: selecting a parameter value from an array or a queue corresponding to each covering bin according to the parameter index value;
specifically, according to the parameter index value corresponding to each variable, the parameter value corresponding to the variable is selected from the array or queue corresponding to the coverage bin corresponding to each variable, for example: when val is 0, for m, idx is (val/(2 × 2))% 3 is 0, i.e., the 0 th value of m is 10; when val is 0, for n, idx is (val/2)% 2 is 0, i.e. the 0 th value of n is taken as 100; when val is 0, for k, idx is 0, i.e. the 0 th value of k is 1000; when val is 0, for p, idx is (val/2)% 4 is 0, i.e. 0 value of p is taken as 50; when val is 0, for q, idx is 0, i.e. 0 value of q is 500;
step S505: and configuring parameters in the test case according to the selected parameter values.
Specifically, the selected parameter values are used as parameters in a test case to perform case testing.
Step S34: performing a regression test based on the regression file;
specifically, after parameters in the test cases are configured, a case parameter analysis file is generated, where the case parameter analysis file includes parameters in all test cases.
Specifically, the performing a regression test based on the regression file includes:
configuring corresponding parameters for each test case in the regression file through the case parameter analysis file to generate a regression file with configured parameters; and performing regression testing based on the regression file of the configuration parameters. The batch configuration parameters of a plurality of test cases in the regression file can be realized through the case parameter analysis file, and the test environment can be favorably loaded with the plurality of test cases at one time for simulation, so that the regression test can be quickly carried out.
It is understood that regression testing refers to verifying that after a bug is repaired or a new function is added, the hardware still passes through all previous test cases (test cases) and new test cases which may be added. Possible environmental changes include improvements in the hardware design itself, bug fixes, addition of functionality, and updates to the verification environment. New defects may be discovered, new test cases may be added, or the verification environment may be updated in each regression test. Each regression test helps to accomplish two goals:
(1) ensuring that the change does not introduce new defects, repairing previous bugs, or implementing new functions according to a preset target.
(2) Random verification, the default random seed is different at each delivery, which is also significant for repeated delivery of a set of regression test charts. Along with functional coverage, the completeness of verification can be gradually improved through a reciprocating regression test and a supplementary directional test.
Step S35: and counting the function coverage rate to confirm that the function coverage rate meets the preset requirement.
It will be appreciated that functional coverage is a measure of whether or not the various functions of the design are implemented and executed in the intended behavior. Functional coverage concerns the input, output and internal states of a design, and the signal sampling requirements are typically described in the following manner:
(1) for the input, it detects the input of the data end and the combination type of the command, and the combination condition of the control signal and the data transmission.
(2) For the output, it detects whether there is a complete data transmission class, and the feedback timing for each case.
(3) And for the inside of the design, the signal needing to be checked corresponds to the functional point needing to be covered in the verification plan. Whether the function is triggered and performed correctly is checked by a single override, a cross override, or a timing override of the signal.
In the embodiment of the present application, the preset requirement includes that the functional coverage rate reaches 100%. Judging whether the number of the function coverage points is equal to the function needing to be covered or not by counting the number of the function coverage points
Assume that in a certain chip project, four variables are included, namely variable a, variable B, variable C, and variable D, where variable a needs to cover 50 values, variable B needs to cover 2 values, variable C needs to cover 20 values, variable D needs to cover 6 values, and the four variables a, B, C, and D need to be cross-covered. Then a total of 12000 different cases need to be covered by permutation and combination.
Referring to fig. 7a and 7b together, fig. 7a is a functional point coverage trend chart of the constrained random verification method in the prior art; FIG. 7b is a functional point coverage trend graph in the embodiment of the present application;
it can be seen that, in the constrained random verification method, the cases of 9669 are covered when 20000 cases are run in the random run simulation, and the cases of 11998 are covered when 100000 cases are run in the random run simulation, but 2 cases are not covered, and cases need to be manually supplemented for covering. Moreover, since a large number of test cases randomly arrive at the same parameter, the server resources are wasted, and the chip verification convergence time is slowed. In the chip verification method in the embodiment of the application, 12000 cases need to be covered, only 12000 cases need to be run at least, and the functional coverage rate of 100% can be met.
In the embodiment of the application, all the function points to be covered are predetermined, and the regression test is performed on the test cases corresponding to all the function points to be covered, so that all the function points can be covered without repeated iterative computation, the iteration times can be reduced, the preset required function coverage rate can be met, and the chip test efficiency is improved.
Referring to fig. 6, fig. 6 is a schematic flowchart illustrating another chip verification method according to an embodiment of the present disclosure;
as shown in fig. 6, the chip verification method includes:
starting;
step S601: acquiring a function coverage rate model file, wherein the function coverage rate model file comprises a function coverage rate model;
step S602: determining the number of all functional points to be covered;
step S603: generating a regression file according to all functional points needing to be covered, wherein the regression file comprises: test cases of all the functional points;
step S604: generating a use case parameter analysis file according to all coverage points extracted from the functional coverage rate model file;
step S605: performing regression testing;
finishing;
in an embodiment of the present application, there is provided a chip verification method, including: acquiring a functional coverage rate model; determining all functional points needing to be covered according to the functional coverage rate model; generating a regression file according to all functional points needing to be covered, wherein the regression file comprises: test cases of all the functional points; performing a regression test based on the regression file; and counting the function coverage rate to confirm that the function coverage rate meets the preset requirement. Determining all functional points needing to be covered by utilizing a functional coverage rate model, and generating a regression file, wherein the regression file comprises: the test cases of all the function points are used for carrying out regression testing, iteration times can be reduced, the function coverage rate of preset requirements can be met, and the chip testing efficiency is improved.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a chip verification apparatus according to an embodiment of the present disclosure;
as shown in fig. 8, the chip verification apparatus 80 includes:
a functional coverage rate model obtaining module 81, configured to obtain a functional coverage rate model;
a function point determining module 82, configured to determine all function points to be covered according to the function coverage rate model;
the regression file generating module 83 is configured to generate a regression file according to all the function points that need to be covered, where the regression file includes: test cases of all the functional points;
a regression testing module 84, configured to perform a regression test based on the regression file;
and the function coverage rate counting module 85 is used for counting the function coverage rate so as to confirm that the function coverage rate meets the preset requirement.
It should be noted that the chip verification apparatus can execute the chip verification method provided by the embodiment of the present application, and has functional modules and beneficial effects corresponding to the execution method. For technical details that are not described in detail in the embodiments of the chip verification apparatus, reference may be made to the chip verification method provided in the embodiments of the present application.
In an embodiment of the present application, there is provided a chip verification apparatus, including: the functional coverage rate model obtaining module is used for obtaining a functional coverage rate model; the function point determining module is used for determining all function points needing to be covered according to the function coverage rate model; the regression file generation module is used for generating a regression file according to all the function points to be covered, wherein the regression file comprises: test cases of all the functional points; the regression testing module is used for carrying out regression testing based on the regression file; and the function coverage rate counting module is used for counting the function coverage rate so as to confirm that the function coverage rate meets the preset requirement. Determining all functional points needing to be covered by utilizing a functional coverage rate model, and generating a regression file, wherein the regression file comprises: the test cases of all the function points are used for carrying out regression testing, iteration times can be reduced, the function coverage rate of preset requirements can be met, and the chip testing efficiency is improved.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a server according to an embodiment of the present disclosure;
as shown in fig. 9, the server 90 includes: one or more processors 91 and memory 92. In fig. 9, one processor 91 is taken as an example.
The processor 91 and the memory 92 may be connected by a bus or other means, and fig. 9 illustrates the connection by a bus as an example.
The memory 92 is used as a non-volatile computer-readable storage medium, and can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as a module or a unit corresponding to a chip verification method in the embodiment of the present invention. The processor 91 executes various functional applications of the chip authentication method and data processing, i.e., functions of the chip authentication method of the above-described method embodiment and the respective modules or units of the above-described apparatus embodiment, by executing the nonvolatile software program, instructions, and modules stored in the memory 92.
The memory 92 may include high speed random access memory and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, the memory 92 may optionally include memory located remotely from the processor 91, and such remote memory may be connected to the processor 91 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The modules are stored in the memory 92 and, when executed by the one or more processors 91, perform the chip verification method in any of the method embodiments described above.
The server 90 of the embodiment of the present application exists in various forms, and when the steps of the chip verification method described above are performed, the server 90 includes, but is not limited to: one or more of a tower server, a rack server, a blade server, and a cloud server.
Embodiments of the present application also provide a non-volatile computer storage medium, where the computer storage medium stores computer-executable instructions, and the computer-executable instructions are executed by one or more processors, for example, the one or more processors may execute the chip verification method in any of the method embodiments, for example, execute the steps described above.
The above-described embodiments of the apparatus or device are merely illustrative, wherein the unit modules described as separate parts may or may not be physically separate, and the parts displayed as module units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a general hardware platform, and certainly can also be implemented by hardware. Based on such understanding, the technical solutions mentioned above may be embodied in the form of a software product, which may be stored in a computer-readable storage medium, such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute the method according to each embodiment or some parts of the embodiments.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; within the context of the present application, where technical features in the above embodiments or in different embodiments can also be combined, the steps can be implemented in any order and there are many other variations of the different aspects of the present application as described above, which are not provided in detail for the sake of brevity; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (10)
1. A method of chip verification, the method comprising:
acquiring a functional coverage rate model;
determining all functional points needing to be covered according to the functional coverage rate model;
generating a regression file according to all functional points needing to be covered, wherein the regression file comprises: test cases of all the functional points;
performing a regression test based on the regression file;
and counting the function coverage rate to confirm that the function coverage rate meets the preset requirement.
2. The method according to claim 1, wherein the determining all functional points that need to be covered according to the functional coverage model comprises:
determining a coverage bin corresponding to each variable in the functional coverage rate model;
determining cross coverage bins corresponding to all variables in the functional coverage rate model;
and counting the total number of the functional points in each cross covering bin according to the cross covering bins, and determining the maximum value of the total number of the functional points.
3. The method of claim 2, wherein after generating the regression file, the method further comprises:
setting an array or a queue for each covering bin, wherein the array or the queue is used for storing the corresponding function point of the covering bin;
determining the value quantity of the use case control parameters according to the quantity of the numerical values corresponding to each variable;
calculating a parameter index value corresponding to each variable according to the value number of the use case control parameters;
selecting a parameter value from an array or a queue corresponding to each covering bin according to the parameter index value;
and configuring parameters in the test case according to the selected parameter values.
4. The method of claim 3, further comprising:
after the parameters in the test cases are configured, a case parameter analysis file is generated, wherein the case parameter analysis file comprises the parameters in all the test cases.
5. The method of claim 4, wherein performing a regression test based on the regression file comprises:
configuring corresponding parameters for each test case in the regression file through the case parameter analysis file to generate a regression file with configured parameters;
and performing regression testing based on the regression file of the configuration parameters.
6. The method of claim 1, wherein the obtaining a functional coverage model comprises:
acquiring a functional coverage rate model file;
and acquiring a functional coverage rate model according to the functional coverage rate model file.
7. The method according to any of claims 1-6, wherein the preset requirements include a functional coverage of up to 100%.
8. A chip verification apparatus, the apparatus comprising:
the functional coverage rate model obtaining module is used for obtaining a functional coverage rate model;
the function point determining module is used for determining all function points needing to be covered according to the function coverage rate model;
the regression file generation module is used for generating a regression file according to all the function points to be covered, wherein the regression file comprises: test cases of all the functional points;
the regression testing module is used for carrying out regression testing based on the regression file;
and the function coverage rate counting module is used for counting the function coverage rate so as to confirm that the function coverage rate meets the preset requirement.
9. A server, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the chip verification method of any one of claims 1-7.
10. A non-transitory computer-readable storage medium storing computer-executable instructions for enabling a server to perform the chip verification method according to any one of claims 1 to 7.
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