CN110569979B

CN110569979B - Logical-physical bit remapping method for noisy medium-sized quantum equipment

Info

Publication number: CN110569979B
Application number: CN201910865893.9A
Authority: CN
Inventors: 张昱; 李权熹; 邓皓巍
Original assignee: University of Science and Technology of China USTC
Current assignee: University of Science and Technology of China USTC
Priority date: 2019-09-09
Filing date: 2019-09-09
Publication date: 2022-09-06
Anticipated expiration: 2039-09-09
Also published as: CN110569979A

Abstract

The invention discloses a logic-physical bit remapping method for noisy medium-sized quantum equipment, aiming at the limitation of quantum hardware, in order to effectively execute a quantum program on the quantum equipment, the necessary remapping is completed by changing the order of quantum instructions and inserting SWAP operation, so that the quantum program is suitable for the limitation of the quantum equipment, and the execution cost of execution time, the number of quantum gates and the like is as low as possible.

Description

Logical-physical bit remapping method for noisy medium-sized quantum equipment

Technical Field

The invention relates to the technical field of quantum computing, in particular to a logical-physical bit remapping method for noisy medium-sized quantum equipment.

Background

Quantum computing is a device that uses quantum mechanical phenomena (such as stacking and entanglement) to perform computations. At present, it is proved that quantum computation can solve some NP difficult problems in a classical computer in quantum polynomial time, for example, the Shor algorithm can solve the difficult problems of large prime factors and discrete logarithms in quantum polynomial time, so that the RSA public key can be cracked.

In quantum computing, information is stored in qubits. Similar to a classical bit, a qubit also has a state, which can be either the |0> or |1> ground states, or a linear combination of |0> and |1>, called the superposition state. For example, the state of a single qubit (i.e., its wave function) | ψ > can be expressed as:

|ψ>＝α|0>+β|1> (1)

alpha and beta are complex numbers satisfying | alpha- ² +|β| ² As 1, a single-quantum-bit state can also be represented as a vector (α, β) with dimension 2 ^T The modulo length of the vector is 1.

When multiple qubits are entangled, the corresponding ground state number rises exponentially. The N quanta bit entanglement system has 2 ^N The system state may be represented as a linear superposition of ground states. For example, a two-quantum bit system has a value of 00>,|01>,|10>,|11>Four ground states, the states of which may also be in a linear superposition of these four ground states, such as:

|ψ>＝a|00>+b|01>+c|10>+d|11>

a, b, c, d are plural numbers and satisfy | a ² +|b| ² +|c| ² +|d| ² 1. The state can also be represented as a vector (a, b, c, d) of modulo length 1 and dimension 4 ^T . In general, the wave function of N qubits can be represented by a2 ^N Vector representation of the dimension.

By utilizing the superposition property of qubits, the information storage capability of quantum computers increases exponentially as the number of qubits increases. The measurement operation on a quantum system will randomly collapse the system to the ground state with a probability dependent on the coefficients preceding each ground state. As for the qubits in the aforementioned equation (1), there is | α $ ² Is collapsed to |0>、|β| ² To |1>。

The technology stack derived from quantum computing over the past 10 years of development is generally shown in fig. 1. The top layer is a quantum algorithm, such as a Shor algorithm for decomposing prime factors; various quantum programming languages and corresponding compilers are provided in the following; further down are quantum instruction set architectures and quantum computing platforms (simulators or quantum hardware). Currently, the common independent quantum programming languages include OpenQASM at quantum line level, Q # at Microsoft and the like, which are introduced by IBMQ; there are also languages ProjectQ, Quil, etc. that may be embedded in Python for use by programmers. The high-level programming language is translated by a compiler into a quantum assembly language or a set of quantum microinstructions.

The body of a quantum program is a sequence of operations on a qubit, called a quantum gate, which can change the state of one or more qubits. Quantum programs implement algorithms by operating to change the state of a qubit. For example, FIG. 2 shows an OpenQASM code, lines 1-2 qreg and creg declare qubits and classical bit registers, respectively, followed by a quantum gate operation on 1 or 2 qubits per line.

The quantum gate g acting on n quantum bits can be implemented with a2 ⁿ ×2 ⁿ Is represented by the matrix M, the quantum gate operation g ═ g (q) ₁ ,...,q _n ) Equivalent to multiplying the matrix represented by the quantum gate by the vector corresponding to the qubit (using the wave function | ψ)>Representation), | ψ'>＝M|ψ>Is the wave function after quantum gate action. Wherein g is the operation of the quantum gate containing the parameter information, and g is a name of the quantum gate. In fact, in a system of N qubits, the global wave function | ψ>The direct product form of each qubit can be written:

so that for a single quantum gate g acting on the ith (1. ltoreq. i.ltoreq.N) bit, its matrix is M _g For a global wave function | ψ>Can be used as M _g Direct product with (N-1) unit arrays, i.e.

(M _g The ith operand in the direct product operation). The matrix M also contains the information on which bits the gate g acts on.

Set two quantum gates operation g ₁ ＝g ₁ (Q ₁ )、g ₂ ＝g ₂ (Q ₂ ) Acting on qubit arrays Q respectively ₁ And Q ₂ Upper (Q) ₁ And Q ₂ Possibly intersecting), g ₁ And g ₂ Matrix M for the impact on the Global wave function ₁ 、M ₂ And (4) showing. If g is executed first ₁ And then executing step g ₂ Its effect | ψ'>＝M ₂ M ₁ |ψ>And executing g first ₂ Then, g is executed ₁ Effect of (v) | ψ ">＝M ₁ M ₂ |ψ>Always the same, i.e. M ₂ M ₁ |ψ>＝M ₁ M ₂ |ψ>Then call g ₁ And g ₂ Is easy to operate. Considering that the calculation satisfies the binding law, g can be obtained ₁ And g ₂ The necessary condition for the convenience is M ₁ M ₂ ＝M ₂ M ₁ 。

The quantum program has strong parallel capability in operation. Two quantum gates are said to be in parallel if there is no overlap of the qubits they are to operate on, two quantum gates in parallel with each other being generally performed simultaneously. For example, row 3 of FIG. 2 is a quantum gate operating on qubit Q [1], and row 4 is a quantum gate operating on qubit Q [2], so that both quantum gates can be performed simultaneously. To reduce the time for program execution, quantum computers may employ a maximum parallelization strategy, i.e., execute as many quantum gates as possible per instant.

The quantum program may run on a quantum program simulator or a quantum computer. The platforms such as project Q, Qiskit, ScaffCC, HiQ and the like provide quantum program simulators; the quantum computer potentially realized by the quantum computer has various types, such as superconductivity, ion trap, neutral atom, optics and the like, and the quantum computer constructed based on the superconductivity and the ion trap is available at present, wherein the IBM Q5 Yorktown based on superconductivity, the Melbourne based on Tenerife and the Melbourne based on Q14 based on superconductivity and the like can be used on line.

Quantum computers entered the NISQ (noisy medium quantum) stage in 2018. The quantum computer at this stage is characterized in that: 1) consisting of 50 to 100 qubits. The number of quantum bits on the one hand already exceeds the upper limit that a classical computer can simulate in a reasonable time, and on the other hand is far from sufficient to perform a bit error correction function similar to that of a classical computer. 2) The hardware contains a lot of noise, resulting in information distortion. Qubits in the superimposed state can become entangled with the surrounding environment over time and cause distortion of the information stored in the qubits (decoherence of the quanta); and because the quantum gate is limited by hardware, there is a certain error rate in its implementation, further resulting in distortion of the information stored by the qubit.

In addition, a plurality of quantum bits under different quantum system physical realization have different characteristics in the arrangement and the quantum gate types and operation and control supported by the quantum bitsAnd a limitation. The multiple quantum gates applied directly to multiple qubits are physically difficult to implement, currently only limited double quantum gates (e.g., the quantum controlled not gate CNOT) are supported and can only act on certain qubit pairs. Such a qubit pair is said to involve two qubits that are adjacent. If two qubits q ₁ And q is ₂ Adjacent, suppose a dual quantum gate g acts on q ₁ And q is ₂ Two operations g (q) ₁ ,q ₂ ) And g (q) ₂ ,q ₁ ) Are all allowed; and if the platform supports multiple kinds of double quantum gates, the number of the quantum gates g is any two ₁ 、g ₂ If operation g is allowed ₁ (q ₁ ,q ₂ ) Then g is ₂ (q ₁ ,q ₂ ) And must also be allowed. Gates acting on more than two qubits can be indirectly implemented by breaking them into a set of single-quantum gates and double-quantum gates. Different kinds of quantum gates, even the same quantum gate acting on different qubit positions, may differ in terms of execution time and introduced distortion rate, etc.

Quantum algorithm design and programmers often do not understand or have difficulty understanding the limitations on quantum hardware. Generally, the quantum bit used in the weighing subroutine is a logic bit and is not affected by the limitation of quantum hardware; the limited quantum bit in the actual quantum hardware is called as a physical bit; the quantum gates acting on the logical bits in the weighing subroutine are logical gates and the gates acting on the physical bits are physical gates. In order for a quantum program to be executed on quantum hardware, a quantum program compiling system needs to perform logical-physical bit mapping and quantum wire transformation at its back end.

For logical-to-physical bit mapping, each logical bit used in the quantum program is typically first mapped to a physical bit, referred to as the initial mapping π. If gates are present in the program that cannot be implemented due to quantum hardware constraints, the program needs to be transformed and the corresponding logical bits remapped to other physical bits. One common approach is to use SWAP gates to exchange information between two adjacent physical bits, thereby routing the qubit information to a position where the qubit gates can be implemented, which corresponds to changing the gate's positionMapping positions of logical bits. Performing s-SWAP (q) when setting to map π ₁ ',q ₂ ') wherein q is ₁ ' and q ₂ ' is a physical bit, SWAP (q) ₁ ',q ₂ ') actual exchange of physical bits q ₁ ' and q ₂ ' inter-state, mapping after swapping will become π non-memory _s Wherein

The logic gate needing routing operation is called a remote gate; and the logic gates that can be executed without routing are immediate gates. In most quantum systems, a SWAP gate can be generally implemented by breaking down into three CNOT gates or other gate operations. The quantum program can be adapted to hardware limitations and executed by mapping and remapping.

The qubit mapping problem is proved to be an NP-complete problem, so that space-time consumption is overlarge by adopting a global solution mode, and only a program with a very small scale can be processed; in practice, heuristic methods are mostly adopted to solve the problems. For the qubit remapping problem, the existing research results assume that the execution time of various quantum gates is the same, and on the basis, a remapping method which enables the program to have shorter running time is solved. However, in actual quantum hardware, execution times of different kinds of quantum gates have large deviations. Therefore, the methods cannot effectively utilize the parallel capability of the quantum computer and find a remapping method for reducing the actual running time as much as possible because the difference of the execution time of the quantum gate is not considered.

Disclosure of Invention

The invention aims to provide a logic-physical bit remapping method for a noisy medium-sized quantum device, which can enable a quantum program to adapt to the limitation of the quantum device and enable execution cost such as execution time, the number of quantum gates and the like to be as small as possible. The invention designs a remapping method which considers the context of a quantum program and the difference of the execution time of a quantum gate by modeling quantum hardware and based on an abstract model. Compared with the traditional mapping scheme, the code execution time after remapping by the method is generally shorter than that of the existing similar method.

The purpose of the invention is realized by the following technical scheme:

a logical-physical bit remapping method for a noisy medium-sized quantum device is characterized by comprising the following steps:

acquiring a logic gate sequence of a quantum program and initial mapping of logic-physical bits;

combining constraint information of quantum equipment for running the quantum program with initial mapping of logic-physical bits, completing remapping by changing the order of logic gates and inserting SWAP operation, obtaining an instruction scheduling sequence meeting the constraint information of the quantum equipment, and ensuring the minimum execution cost; each element in the instruction dispatch sequence is a doublet of a physical gate to be executed and its starting execution time.

It can be seen from the above technical solutions that, for the limitation of quantum hardware, in order to enable a quantum program to be effectively executed on a quantum device, the quantum program is adapted to the limitation of the quantum device by changing the order of quantum instructions and inserting SWAP operation to complete necessary remapping, and the execution cost such as the execution time and the number of quantum gates is as small as possible.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a diagram of a quantum computer technology stack provided in the background of the invention;

FIG. 2 is a schematic diagram of an OpenQASM code provided in the background of the present invention;

fig. 3 is a schematic diagram illustrating a compiling and executing process of a quantum program according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a flag word of a physical bit according to an embodiment of the present invention;

FIG. 5 is a diagram illustrating a quantum instruction simulation execution and maximum parallelization algorithm according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a qubit rectangular network according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

The embodiment of the invention provides logical-physical bit remapping for noisy medium-sized quantum equipment; firstly, acquiring a logic gate sequence of a quantum program and initial mapping of logic-physical bits; then, combining constraint information of quantum equipment for running the quantum program and initial mapping of logic-physical bits, completing remapping by changing the order of logic gates and inserting SWAP operation (exchange operation), obtaining an instruction scheduling sequence meeting the constraint information of the quantum equipment, and ensuring the minimum execution cost; each element in the instruction dispatch sequence is a doublet of a physical gate to be executed and its starting execution time.

As will be appreciated by those skilled in the art, a swap operation, acting on two physical bits, is used to swap the states of the two physical bits.

Fig. 3 is a schematic diagram illustrating the compiling and executing processes of the quantum program. The quantum program is a line-level quantum assembler program (for example, OpenQASM) generated by manual writing or compiling from a high-level language. First, a quantum program is preprocessed to adapt to an instruction set of a target platform, and is flattened (implemented by a flattening module shown in fig. 3) into a logic gate sequence executed in a continuous sequence; other optimization techniques may also be implemented on the quantum program during the preprocessing. After that, the preprocessed quantum program is initially mapped and remapped (implemented by the remapping module shown in fig. 3) to obtain the instruction sequence acting on the physical bits. The initial mapping is responsible for mapping logical bits in a program to physical bits when the program starts to execute, and the result after mapping may have a violation that a double quantum gate acts on non-adjacent physical bits. The remapping algorithm obtains an instruction sequence meeting the physical bit constraint according to the input initial mapping and the logic gate sequence, wherein part of instructions can be executed in parallel. The remapped output will mark the scheduled start time and end time of all instructions under maximum parallelization as the reference of hardware issue instruction time, where time is relative time. The main contribution of the present invention is focused on the design and implementation of the remapping algorithm.

The remapping algorithm provided by the invention focuses on considering the context environment at the remapping position and the parallelization characteristics of the instruction. Because of the parallelism that may exist between quantum gates in a quantum program and the interchangeability between certain pairs of quantum gates, there are often multiple quantum gates that can begin executing at each time without changing the program semantics. Remapping algorithms require routing logic gates where execution is desired to begin, but cannot be performed due to hardware geometry constraints (e.g., the qubits being applied are not adjacent). For logic gates that have met the geometric constraints and can be executed, the remapping algorithm will schedule the quantum gates required for execution in situ; for logic gates where hardware constraints cannot be enforced in place, the algorithm will route according to a heuristic strategy, remapping the logic bits to physical bits at another location and implementing the required quantum gates. In order to make the routing path as reasonable as possible, the remapping algorithm takes into account as much as possible the routing effect on the next possible quantum gates to execute and arranges the instruction execution order appropriately. Thus, the algorithm needs to know which quantum gate order can be changed, the impact of the route to be implemented on subsequent quantum gates, etc.

The remapping algorithm simulates the process of quantum program execution once, and can partially disturb the gate sequence and add SWAP operation without changing the program semantics. In the simulation execution process, for an unexecuted logic gate operation sequence G and one gate operation G, if all unexecuted gate operations before G and G are simple, then executing G first does not change the execution result of the sequence, and such G is called a candidate gate. It should be noted that the elements in the candidate gate set of a program point in a quantum program are not necessarily all parallel, for example, the Y gate and the H gate acting on the same bit are easy but not parallel.

Before introducing a concrete implementation mode of a remapping algorithm, quantum hardware is abstracted:

suppose quantum hardware has N physical bits

And provide m quantum gates

Initialization and measurement operations, which are referred to as quantum instructions.

Consider two logic gates g ₁ (Q ₁ ) And g ₂ (Q ₂ ) If, if

The two doors must be easy; otherwise, whether it is easy depends on the door g ₁ 、g ₂ The nature of (c). If the bit Q belongs to Q ₁ ∩Q ₂ Then, q is called g ₁ (Q ₁ ) And g ₂ (Q ₂ ) The coacting bit of (c). For the case of a multi-bit quantum gate, the reciprocity relationship is related to the position of the common effect bit at the parameter position of the multi-bit quantum gate, and the ith parameter position of the g is g.i. If g is a single bit gate, its parameter position can be directly denoted by g. Such as CX (q) ₁ ,q ₂ ) And X (q) ₁ ) Uneasy, CX (q) ₂ ,q ₁ ) But is combined with X (q) ₁ ) Easy to match, where q ₁ And q is ₂ Are different bits. For this reason, if for any quantum gate g ₁ (Q ₁ ) And g ₂ (Q ₂ ) And Q ₁ ∩Q ₂ Q is g ₁ Is g ₂ The jth actual ginseng of (1) must have g ₁ (Q ₁ ) And g ₂ (Q ₂ ) For easy, record g ₁ I and g ₂ J pairs of ease. If it isFor controlled gate or single quantum gate g ₁ (Q ₁ ) And g ₂ (Q ₂ ) Each co-acting bit q of _k Let q denote _k Is g ₁ I th of (1) _k A parameter is g ₂ J (d) of _k Each parameter having g ₁ .i _k And g ₂ .j _k Easy pair, then g ₁ (Q ₁ ) And g ₂ (Q ₂ ) Is easy to operate. If it is

A table of reciprocity relationships like table 1 can be obtained, the two-dimensional table being symmetrical. Wherein, H, X, Y, Rz, CX, etc. are quantum gate symbols.

Note that: the headings of each row and each column in table 1 of the table of reciprocity relationships represent each parameter position of the physical door supported; since the single-bit quantum gate g (g can be one of H, X, Y, Z, Rz) has only one parameter, g.1 is abbreviated as g; the first and second parameter positions of the two-bit quantum gate CX represent the control bit C and the controlled bit T, respectively, so cx.1 and cx.2 are also denoted as cx.c and cx.t, respectively.

TABLE 1 table of reciprocity relationships between quantum operations

The invention assumes that different quantum instructions (including quantum gates and measurement operations) and especially the various quantum gates have different execution times, and the execution of the same quantum gate at different times or on physical bits has the same execution duration. In order to design a quantum bit mapping algorithm suitable for different quantum hardware, the invention abstracts the quantum instruction execution time of the quantum hardware by taking an instruction scheduling period (hereinafter referred to as scheduling period) as a basic unit. Assume that the time when the first instruction starts to execute in the quantum program is recorded as 0, each quantum instruction is executed from the start time of a certain scheduling cycle, and the execution duration is an integer multiple of the scheduling cycle (i.e. the minimum integer multiple for ensuring that the quantum instruction is executed completely). The present invention expresses the execution time length of an instruction by a multiple and allows a user to set the execution time length of each quantum instruction. For example, in a superconducting computer implemented by IBM, the execution times of a single-quantum unitary gate (U) and a quantum controlled not gate (CNOT, also called CX) are 1 and 2, and the SWAP operation is implemented by using three CNOT gates, so that the execution time is set to 6.

If a quantum instruction is executing, its active bit is said to be busy, otherwise it is said to be idle. The invention assumes that two instructions that cannot be parallelized (i.e. they both act on a same bit) cannot be executed simultaneously, and that the remaining instructions can be executed at the start of any subsequent scheduling cycle as long as all the physical bits required by the instruction are free.

The following is a detailed description of preferred embodiments of the remapping scheme and associated algorithms involved in performing the remapping scheme according to the present invention.

One, the overall scheme of quantum bit remapping.

Given the quantum hardware abstraction in the foregoing, given a sequence of logic gates G and an initial mapping pi of a quantum program, a quantum bit remapping will output an instruction schedule sequence that satisfies quantum hardware constraints, with each element in the sequence being a doublet of a physical gate to be executed and its starting execution time. The remapping algorithm accomplishes the qubit mapping and the scheduling of the quantum instruction by simulating the execution of the quantum instruction. To track the idle condition of physical bits, a t is defined for each physical bit _end Attribute to indicate the busy moment of the end of the corresponding bit, for a physical bit q, t _end The attribute is noted as q.t _end T of the totality of physical bits _end The attribute set is denoted T _end (ii) a Initially, t of each bit _end The attribute is 0, if the current time t is more than or equal to q.t _end If so, bit q is idle;

the step of remapping comprises:

step A1, setting the current time t to be 0, and initializing an output instruction scheduling sequence I to be { };

step A2, initialize t _end Attribute, t of each physical bit _end Setting the attribute as 0;

step A3, calculating a current candidate gate set C by using an approximate solution algorithm of the candidate gate set, combining a logic gate sequence G and a mapping pi of logic-physical bits (the pi is the mapping from the current logic bit to the physical bit, the mapping is called as initial mapping when the remapping is started to execute and is transmitted from the outside; the candidate gate is that, for one logic gate g, if the logic gate g and all the logic gates which are not executed before the logic gate g are simple, the logic gate g is executed first next without changing the execution result of the sequence, and the logic gate g is the candidate gate;

step A4, set of immediate gates C in set C for current candidate gates _I Sequentially traverse C _I Performs: step A41, if the physical bits mapped by the logic bits acted by the logic gate g are all idle, then using quantum instruction simulation execution and maximum parallelization algorithm, combining the instruction scheduling sequence I and the attribute set T _end Transmitting a physical instruction (consisting of a physical gate corresponding to the logic gate G and an active physical bit) corresponding to the logic gate G, and removing the logic gate G from the logic gate sequence G; step A42, get immediate gate set C _I Continues to perform step a41 until the immediate set of gates C _I Is empty; otherwise, executing step A5;

step A5, for remote set of doors C in current set of candidate doors C _R Executing the following steps: step A51, using heuristic algorithm of optimal route, combining logical-physical bit mapping pi and attribute set T _end And remote door set C _R Obtaining an SWAP operation sequence S; step A52, for each SWAP operation in the SWAP operation sequence S, firstly updating the corresponding bit mapping in the logic-physical bit mapping pi according to two physical bits exchanged by the corresponding SWAP operation, and then combining the instruction scheduling sequence I and the attribute set T by utilizing the quantum instruction simulation execution and maximum parallelization algorithm _end Issue a corresponding physical instruction (e.g., a SWAP operation corresponds to 3 CX instructions); the remote gate is a logic gate needing routing operation, and the immediate gate is a logic gate capable of executing without routing;

step a6, setting the current time t to t + 1;

step A7, return to step A3 until logic gate sequence G is empty.

It should be noted that, in the step a5, the heuristic algorithm that adopts the optimal route may not output the route SWAP at times, which will be described in detail later. In very special cases it may happen that bits are free in the global or in a certain local domain, but neither immediate gates of the candidate gates can be executed, nor heuristic algorithms give a feasible routing bit. A similar situation is called "deadlock". The deadlock is discussed in more detail below.

And II, an approximate solution algorithm of the candidate gate set.

In the previous step A3, the current candidate set of gates C is solved using an approximate solution algorithm for the candidate set of gates.

Given the sequence of unexecuted logic gates G at the current time t, the set of candidate gates can be solved by the definition of the candidate gates, but it takes time. Considering that the number of quantum bits supported by actual hardware and the types of quantum gates are very limited, a flag word with a fixed length is introduced into each physical bit, and a flag bit is set for each parameter position g.i of each physical gate g in the flag word; and sequentially reading the logic gates in the logic gate sequence G, wherein the flag bit is true to indicate that the corresponding parameter positions of the logic gates and all the read logic gates are easy. Fig. 4 shows a schematic diagram of a physical bit flag word.

The embodiment of the invention provides two methods for rapidly solving a candidate set, wherein the first method comprises the following steps:

step B1, initially, the current candidate gate set C is a null set, and each flag bit of each physical bit is true;

step B2, all the unexecuted logic gates are traversed in the forward direction in sequence, and the following steps are executed:

step B21, setting the current logic gate as g ═ g (Q), where Q represents the logic bit array acted by the logic gate g; if each logic bit Q belongs to Q, Q is the ith parameter of g, and the g.i flag bit of the corresponding physical bit Q' ═ pi (Q) is true, the logic gate g is put into a candidate gate set C;

step B22, for all logic bits Q ∈ Q, setting Q to be the ith parameter of g, searching the column where the g.i flag bit of the physical bit Q ' corresponding to the logic bit Q is located (the column named g.i can be found by searching the table 1 of the easy relation table), if the column has a unit with a value of 0, the row name of the unit is g '. j, which indicates that g '. j and g.i are not easy, the flag bit corresponding to g '. j of the physical bit Q ' is false;

and step B23, taking down a logic gate, and continuing to loop until the traversal is finished or all the flag bits are false.

The first approach can theoretically find all the candidate gates. However, the time and space consumption of the algorithm is still large for quantum gate sequences with more gate types or not implemented. In addition, the above algorithm cannot make effective use of the last results because the subsequent algorithms need to update the candidate gate set frequently. Suppose the last acquired set of candidate gates is C ₀ After that, C is executed ₀ Several doors in C ₀ Is changed into C ₀ ', then C ₀ The gates in' are still candidates, and therefore, the first method can be improved:

1) the initial candidate set of gates utilizes the last results to avoid a large number of duplicate calculations.

2) And (4) increasing a cycle termination condition, and only screening candidate gates from the gates within a certain range to avoid overlong time consumption.

The above improvements can further significantly reduce the execution time of the algorithm. The improved algorithm is an approximation algorithm, and the obtained set is a subset of the actual candidate gate set, but the difference is not significant.

The second method is then:

step C1, in each iteration process of remapping, a candidate gate set is required to be solved, and when the candidate gate set is solved for the first time, the candidate gate set C is an empty set;

step C2, when solving the candidate gate set in the remapping iterative process, recording the candidate gate set solved last as C _last Is provided with C _last Subset C _emitted Having been launched and removed in the last remapping, record set C ₀ ＝C _last -C _emitted ；

C3, recording each flag bit of each physical bit is true;

step C4, traversing the set C ₀ A middle logic gate g ═ g (Q), Q denotes the array of logic bits acted on by the logic gate g; for each logic bit Q ∈ Q, setting Q as the ith parameter of g, searching for a column where a g.i flag bit of a physical bit Q ' corresponding to the logic bit Q is located, if a unit with a value of 0 exists in the corresponding column, marking a row name of the corresponding unit as g '. j, indicating that g '. j and g.i are not easy, and setting the flag bit corresponding to g '. j of the physical bit Q ' ═ pi (Q) as false;

step C5, sequentially traversing all unexecuted logic gates in the forward direction, and executing:

step C51, if g is already in the candidate gate set C, continuing to take the next logic gate; otherwise, go to step C52;

step C52, if each logic bit Q belongs to Q, Q is the ith parameter of g, and g.i flag bit of the corresponding physical bit Q' is true, putting g into the candidate gate set C; otherwise, go to step C53;

step C53, for all logic bits Q belonging to Q, setting Q as the ith parameter of g, searching the column where the g.i flag bit of the physical bit Q ' corresponding to the logic bit Q is located, if the corresponding column has a unit with a value of 0, the row name of the corresponding unit is g '. j, and if the g '. j and the g.i are not easy to match, the flag bit corresponding to g '. j of the physical bit Q ' is false;

and step C54, taking down a logic gate, and continuing to loop until the traversal is finished or the total number of traversed logic gates exceeds a set value N.

And thirdly, performing quantum instruction simulation execution and a maximum parallelization algorithm.

The quantum instruction simulation execution and maximum parallelization algorithm is applied to the foregoing steps a4 and a5, and is responsible for transmitting a physical instruction corresponding to a physical gate g' or SWAP operation acting on a physical bit, and setting and judging a busy or idle state of the physical bit.

In the embodiment of the present invention, before performing the quantum instruction simulation execution and the maximum parallelization algorithm, the mapping pi is used to convert the logical bit array Q acted by the logic gate g into the physical bit array Q '═ pi (Q), so that the logic gate g becomes the physical gate g', it should be noted that the actual operation content of the logic gate and the physical gate is not changed, and the difference is only that the operation object is changed from the logical bit to the physical bit.

Whenever an instruction g ' ═ g (Q ') (where Q ' is a physical bit array) or SWAP operation is to be transmitted in the remapping algorithm, the quantum instruction emulation execution and maximum parallelization algorithm receives the corresponding instruction and then performs the following operations:

1) for each physical bit Q ' ∈ Q ' acted on by physical gate g ', its latest ending busy time t is found _m ＝max{q’.t _end Since the command can only be transmitted when the physical bit is free, it is obvious that t _m T is less than or equal to t; let the execution time of the physical gate g 'be tau, then for each physical bit Q'. epsilon.Q ', set Q'. t _end ＝t _m +τ。

2) For SWAP operation, a physical implementation instruction corresponding to the SWAP operation is transmitted, such as 3 CX operations and the start execution time thereof.

In the embodiment of the invention, the physical instruction g ' received by the quantum instruction simulation execution and maximum parallelization algorithm at the time t is not directly executed at the time t, but the earliest moment after all physical bits for tracing the action of the physical instruction forward end a busy state is used as the moment when the g ' starts to execute, and the moment is the earliest moment when the g ' can execute. Given the locality of the remapping algorithm, it may happen that an instruction (typically SWAP) that is not anticipated in time is sent later. Quantum instruction simulation execution and maximum parallelization algorithms are the maximum parallelization algorithms, assuming that quantum computers have sufficient parallelism capability to execute immediately when all instructions can begin execution. Under the condition of giving an instruction sequence, the quantum instruction simulation execution and the maximum parallelization algorithm ensure the early execution of the instruction, so that the received quantum instruction is parallelized maximally.

As shown in part (a) of fig. 5, CX (q1, q3) is currently required to be performed, and since q1 and q3 are not adjacent, the heuristic of optimal routing arranges a SWAP (q2, q3) operation so that CX operations can then be performed on adjacent q1 and q 2. The quantum instruction emulation execution and maximum parallelization algorithm does not directly schedule the SWAP instruction to begin execution at the current time (dashed line), but instead traces back as early as possible (as shown in part (b) of fig. 5), thereby advancing both the SWAP and subsequent CXs (and other potentially affected gates) (as shown in part (c) of fig. 5).

And fourthly, performing heuristic algorithm of the optimal route.

The embodiment of the invention provides a heuristic algorithm of an optimal route, which is used for collecting a non-empty candidate remote gate set C _R A set of approximately optimal SWAP operations S is given. Is provided with C _R The set of physical bits in each gate action is Q'. For idle bits Q in physical bit array Q ₁ ', if any, associated with the physical bit q ₁ ' Adjacent physical bits q ₂ ' and q ₂ ' Idle, then call q ₁ ' and q ₂ The SWAP operation between' is a candidate SWAP, and the set of all candidate SWAPs is referred to as a SWAP candidate set.

The step of obtaining the SWAP operation sequence S by using the heuristic algorithm of the optimal route comprises the following steps:

step D1, making the SWAP operation sequence S { };

step D2, finding the current SWAP candidate set S _c (ii) a Assuming that the logic gate g is a remote gate, the logic bit array Q acted on by the logic gate g is converted into a physical bit array Q ' (Q ' ═ pi (Q)) by mapping pi, the logic gate g becomes a physical gate g ', here called remote gate g ', for the free bits Q ' in the physical bit array Q ₁ ', if any, associated with the physical bit q ₁ ' Adjacent physical bit q ₂ ' and q ₂ 'Idle', then physical bit q is called ₁ ' and q ₂ SWAP operations between' are candidate SWAP;

step D3, for each candidate SWAP operation s _k ∈S _c Calculating the priority (the specific manner will be described later);

d4, selecting the SWAP operation s with the highest priority, if the priority of the SWAP operation s is less than 1; or if the adjacent relation between the physical bits can be modeled as a rectangular grid, the priority of the SWAP operation S is less than <1,0>, the algorithm is terminated, and the currently obtained SWAP operation sequence S is output;

step D5, update SWAP operation sequence: s ═ es { S };

step D6, selecting the SWAP candidate set S _c Removing the SWAP operation s and the SWAP operation with the common physical bit with the SWAP operation s;

step D7, updating mapping, pi ═ pi- _s That is, the mapping pi change is updated to pi _ memory after the SWAP operation s is performed during the mapping pi _s ；

And D8, returning to the step D3 until the SWAP candidate set is empty.

Each time the SWAP is selected during the execution of the algorithm, the SWAP that is not parallel to the selected SWAP is excluded from the candidate SWAPs, so that all the resulting SWAP operations S are parallel to each other and can be executed immediately. The return value of the algorithm is S, i.e., the SWAP operation sequence.

However, all of the candidate SWAP operations s may be performed as described above _k The priority of the epsilon S is less than 1 or less than<1,0>At this time, there may be two cases:

in the first case, some candidate gates need routing, but some physical bit acted by these candidate gates is in busy state, or the routing will interfere with other executing gates (already in the instruction scheduling sequence and executing quantum gates, here, execution refers to simulation execution);

in the second case, there are candidate gates that need routes that do not interfere with the gate being executed;

the reason for this second situation arises is that the algorithm believes that, for any one route, it will decrease the distance of some remote gates, but may increase the distance of the same or a greater number of remote gates. The routing scheduling system is locked at this time-similar to a deadlock in the operating system, and is referred to as a deadlock. For the case of deadlock, the following resolution strategy is used:

1) from SWAP candidate set S _c Selecting the SWAP operation s with the highest priority;

2) from SWAP candidate set S _c Removing SWAP operation s and SWAP operation having common bit with SWAP operation s, executing s and updating mapping pi ═ pi- _s ；

3) The normal routing algorithm (i.e., steps D1-D8 above) is re-executed until there are no candidate SWAP with a priority of no less than 1 or <1,0> (for the physical bit rectangular grid).

Both theoretical analysis and practice show that even if all bits are free and the candidate SWAP set S _c If not, it is still possible to find a SWAP with a priority greater than or equal to 1. This is because some of the SWAP-involved bits may involve different remote gates, and neither route reduces the total distance of the remote gates. As in the case of fig. 6, there are 4 candidate gates waiting to be executed on a rectangular grid device, with one candidate CX gate (controlled not gate, a type of two quantum gate) between the bits of the same padding. The distance of each CX is 1, but swapping any adjacent bits does not reduce the total distance (from 1+1+1+1 to 2+1+1+0 at most)

For this case, a candidate SWAP with the highest priority (although still less than 1) may be selected for execution, breaking this. Such a highest priority may prove to be at least 0, meaning that performing it does not make the situation worse and must be advantageous for shortening the distance of a certain candidate gate.

The following describes the candidate SWAP operations s _k The calculation mode of the priority:

defining the distance (distance) of the remote gate g as the minimum SWAP operand required to implement the remote gate g, noted as g.d; the dual quantum gates on two non-adjacent bits are remote gates; in addition, a single bit quantum gate is also a remote gate if it cannot be executed at the current location and needs to remap bits to another location.

Defining a total candidate distance

For each candidate SWAP operation s _k ＝SWAP(q ₁ ’,q ₂ ') performs the candidate SWAP operation s _k Updating logical-to-physical bit mapping

Defining a heuristic function:

H _basic the higher (π, s), the SWAP operation s _k The greater the positive impact, the higher the priority H (π, s) _k )＝H _basic (π, s); in general, H (. pi., s) can be used directly _k )＝H _basic (π,s _k ) Measure each candidate SWAP operation s _k The positive effect of (2) is to select s which maximizes H (π, s).

If the neighborhood between physical bits can be modeled as a rectangular grid; then a heuristic optimization may be further performed by considering the features of its candidate SWAP operation on a rectangular grid for each candidate dual-quantum remote gate g. In a rectangular grid, each physical bit has location attributes x and y, and if logic gate g is a dual-quantum remote gate, then g is equal to g (q) ₁ ,q ₂ ) Two logical bits q of its effect ₁ And q is ₂ The horizontal distance and the vertical distance therebetween are respectively defined as:

HD(π,g)＝|q ₁ ’.x-q ₂ ’.x|

VD(π,g)＝|q ₁ ’.y-q ₂ ’.y|

wherein q is ₁ ’.x、q ₁ '. y represents a logical bit q ₁ Corresponding physical bit q ₁ ' row, column coordinates in a rectangular grid; q. q.s ₂ ’.x、q ₂ '. y represents a logical bit q ₂ Corresponding physical bit q ₂ ' row, column coordinates in a rectangular grid;

then the distance d (pi, g) ═ HD (pi, g) + VD (pi, g) -1; for g, it is necessary to introduce a SWAP operation to route bit information to a physical bit that the quantum gate can execute, and its shortest route may have

And (4) seed preparation.

In the rectangular grid, for a bit pair with an arbitrary distance d (pi, g), when | VD (pi, g) -HD (pi, g) | of the bit pair is smaller, the number of shortest routing paths possible between the bit pair is larger; using this property, for each candidate SWAP operation s _k And introducing the following heuristic function for auxiliary selection:

wherein G is ₂ For a set of dual-quantum remote gates, for the case that can be modeled as a rectangular grid, let the priority be H (π, s) _k )＝<H _basic (π,s _k ),H _fine (π,s _k )>。

Defining H (π, s) ₁ )＞H(π,s ₂ ) If and only if H _basic (π,s ₁ )＞H _basic (π,s ₂ ) Or H _basic (π,s ₁ )＝H _basic (π,s ₂ )∧H _fine (π,s ₁ )＞H _fine (π,s ₂ ). If H (π, s) ₁ )＞H(π,s ₂ ) Or as H (π, s) ₂ )＜H(π,s ₁ ) Then call s ₁ Priority ratio s of ₂ High.

As will be understood by those skilled in the art, the priority is represented by a binary, and the ">, <" represents the partial order relationship of the binary priority.

For a sufficiently ideal quantum computer, any supported gate operation can be performed on any qubit. But remapping is required on a typical quantum computer to ensure program execution. In the remapping process, SWAP operation is introduced, so that the total number of the remapped instructions and the total execution time are not less than those before remapping conversion. We can use two simple indicators to measure how good the remapping algorithm is: the additional introduction of SWAP operands, and the introduction of SWAP results in increased execution time (than on ideal hardware).

The logical-physical bit remapping method for the noisy medium-sized quantum device provided by the invention is called COntext-and DurThe ation-Aware Remapping algorithm (CODAR). The algorithm for benchmarking is the SABRE algorithm which is currently known to work best. Tests were performed on three models, IBM Q16, IBM Q20Tokyo and Enfield 6 x 6, respectively. The test samples include typical quantum algorithms such as Quantum Fourier Transform (QFT), schuler algorithm (shors), and the like. The test results are shown in tables 2 to 3. Wherein, the bits is the logic bit number, g, used by the quantum program _t Is the total gate number of the program, T _S 、T _C The shortest execution time after SABRE transformation and CODAR transformation is shown, wherein the execution time of the single quantum gate is 1, CX is 2, and SWAP is 6. Both CODAR and SABRE undergo 12 forward and backward bi-directional iterations in the above test to find the initial mapping.

TABLE 2 test results (front half)

volume_n5_d2	5	40	20	20	20	100.0％	20	20	100.0％	20	20	100.0％
													4mod5-v1_22	5	21	22	42	53	79.2％	22	22	100.0％	42	47	89.4％
9symml_195	11	34881	32084	74352	81711	91.0％	59755	60884	98.2％	71816	78153	91.9％
													adr4_197	13	3439	3088	6977	7737	90.2％	5345	5444	98.2％	6747	7479	90.2％
alu-v0_27	5	36	35	61	71	85.9％	49	39	125.6％	68	71	95.8％
													cvcle10_2_110	12	6050	5662	12871	14113	91.2％	10077	10626	94.8％	12492	13682	91.3％
ising_model_10	10	480	90	89	90	98.9％	89	90	98.9％	89	90	98.9％
													ising_model_13	13	633	91	91	91	100.0％	91	91	100.0％	91	178	51.1％
ising_model_16	16	786	91	91	91	100.0％	91	180	50.6％	91	130	70.0％
													misex1_241	15	4813	4473	9816	10775	91.1％	7196	6940	103.7％	9296	10663	87.2％
mod5mils_65	5	35	37	76	80	95.0％	63	59	106.8％	76	80	95.0％
													radd_250	13	3213	2990	6727	7404	90.9％	5061	5375	94.2％	6494	7159	90.7％
rd73_252	10	5321	4829	10970	12287	89.3％	8834	8933	98.9％	10694	11780	90.8％
													rd84_142	15	343	191	452	493	91.7％	378	412	91.8％	459	463	99.1％
rd84_253	12	13658	12176	28256	31365	90.1％	22054	23183	95.1％	27237	30133	90.4％
													sqn_258	10	10223	9176	20916	23170	90.3％	16741	16694	100.3％	20581	22263	92.4％
square_root_7	15	7630	6367	12399	16269	76.2％	10247	10710	95.7％	12058	15744	76.6％
													sym6_145	7	3888	3686	8129	9011	90.2％	5885	6221	94.6％	8066	8847	91.2％
sym9_193	11	34881	32084	74352	81711	91.0％	59805	60777	98.4％	71920	78153	92.0％
													z4_268	11	3073	2756	6248	6892	90.7％	5010	5140	97.5％	6082	6827	89.1％

TABLE 3 test results (latter half)

In the three models of IBM Q16, IBM Q20Tokyo, and Enfield 6 x 6, the runtime of the program for CODAR transformation compared to the time of the program for SABRE transformation was 82.5%, 82.4%, 80.6%, respectively. CODAR successfully reduced program run times by 17.5% to 19.4% on different platforms.

Through the description of the above embodiments, it is clear to those skilled in the art that the above embodiments may be implemented by software, or by software plus a necessary general hardware platform. Based on such understanding, the technical solutions of the embodiments may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.), and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods according to the embodiments of the present invention.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A logical-physical bit remapping method for a noisy medium-sized quantum device is characterized by comprising the following steps:

combining constraint information of quantum equipment for running the quantum program with initial mapping of logic-physical bits, completing remapping by changing the order of logic gates and inserting SWAP operation, obtaining an instruction scheduling sequence meeting the constraint information of the quantum equipment, and ensuring the minimum execution cost; each element in the instruction scheduling sequence is a binary group consisting of a physical gate to be executed and the initial execution time of the physical gate;

wherein a t is defined for each physical bit _end Attribute to indicate the busy moment of the end of the corresponding bit, for the physical bit q, its t _end The attribute is noted as q.t _end T of the totality of physical bits _end The attribute set is denoted T _end (ii) a Initially, t of each bit _end The attribute is 0, if the current time t is more than or equal to q.t _end If so, bit q is idle;

the step of remapping comprises:

step A3, calculating a current candidate gate set C by using an approximate solution algorithm of the candidate gate set and combining a logic gate sequence G and a mapping pi of logic-physical bits; the candidate gate is that, for one logic gate g, if the logic gate g and all the logic gates which are not executed before the logic gate g are all easy, the logic gate g is executed first next without changing the execution result of the sequence, and then the logic gate g is the candidate gate;

step A4, set of immediate gates C in set C for current candidate gates _I Sequentially traverse C _I Performs: step A41, if the physical bits mapped by the logic bits acted by the logic gate g are all idle, then using quantum instruction simulation execution and maximum parallelization algorithm, combining the instruction scheduling sequence I and the attribute set T _end Transmitting a physical instruction corresponding to the logic gate G, wherein the physical instruction consists of a physical gate corresponding to the logic gate G and an acting physical bit, and removing the logic gate G from the logic gate sequence G; step A42, get immediate gate set C _I Continues to perform step a41 until the immediate set of gates C _I Is empty; otherwise, executing step A5;

step A5, for remote set of doors C in current set of candidate doors C _R And executing: step A51, utilizing heuristic algorithm of optimal route, combining logic-physical bit mapping pi and attribute set T _end And remote door set C _R Obtaining a SWAP operation sequence S; step A52, for each SWAP operation in the SWAP operation sequence S, firstly updating the corresponding bit mapping in the logic-physical bit mapping pi according to two physical bits exchanged by the corresponding SWAP operation, and then combining the instruction scheduling sequence I and the attribute set T by utilizing the quantum instruction simulation execution and maximum parallelization algorithm _end Transmitting a corresponding physical instruction; the remote gate is a logic gate needing routing operation, and the immediate gate is a logic gate which can be executed without routing;

step a6, setting the current time t to t + 1;

step A7, return to step A3 until logic gate sequence G is empty.

2. The method of claim 1, wherein the remapping by changing the order of logic gates and inserting SWAP operations comprises:

during remapping, the process of quantum program execution is simulated, the context environment of the quantum program and the parallelization characteristics of the logic gates are combined, the order of part of the logic gates is changed and SWAP operation is inserted on the premise of not changing the semantics of the quantum program, so that the instruction scheduling sequence obtained after remapping can be directly executed in corresponding quantum equipment.

3. The method of claim 1, wherein the step of computing the current candidate set of gates C comprises:

introducing a flag word with fixed length for each physical bit, and setting a flag bit for each parameter position g.i of each physical gate g in the flag word; sequentially reading in the logic gates in the logic gate sequence G, wherein the flag bit is true to indicate that the corresponding parameter positions of the logic gates and all the read logic gates are easy;

step B2, all the logic gates which are not executed are traversed forward in sequence, and the following steps are executed:

step B21, setting the current logic gate as g ═ g (Q), where g is the quantum gate operation including parameter information, g is a quantum gate name, and Q represents the logic bit array acted by the logic gate g; if each logic bit Q belongs to Q, Q is the ith parameter of g, and the g.i flag bit of the corresponding physical bit Q' ═ pi (Q) is true, the logic gate g is put into a candidate gate set C;

step B22, for all logic bits Q belonging to Q, setting Q as the ith parameter of g, searching the column where the g.i flag bit of the physical bit Q ' corresponding to the logic bit Q is located, if the corresponding column has a unit with a value of 0, the row name of the corresponding unit is g '. j, and if the g '. j and the g.i are not easy to match, the flag bit corresponding to g '. j of the physical bit Q ' is false;

4. The method of claim 1, wherein the step of computing the current candidate set of gates C comprises:

step C1, in each remapping iteration process, a candidate gate set needs to be solved, and when the candidate gate set is solved for the first time, the candidate gate set C is an empty set;

step C2, when solving the candidate gate set in the remapping iterative process, recording the candidate gate set solved last as C _last Is provided with C _last Subset C _emitted Having been launched and removed in the last remapping, set C is marked ₀ ＝C _last -C _emitted ；

C3, recording each flag bit of each physical bit is true;

step C4, traversing the set C ₀ The logic gate g ═ g (Q), where g is a quantum gate operation containing parameter information, g is a quantum gate name, and Q represents a bit array acted on by the logic gate g; for each logic bit Q belongs to Q, setting Q to be the ith parameter of g, searching a column where a g.i flag bit of a physical bit Q ' corresponding to the logic bit Q is located, if a unit with a value of 0 exists in the corresponding column, the row name of the corresponding unit is named as g '. j, and if the g '. j and the g.i are not easy, setting the flag bit corresponding to the g '. j of the physical bit Q '. pi (Q) as false;

step C51, if the logic g is already in the candidate gate set C, continuing to take the next logic gate; otherwise, go to step C52;

5. The method for remapping the logical-physical bits of the noisy medium-sized quantum device according to claim 1, wherein before the quantum instruction simulation execution and the maximum parallelization algorithm are performed, the logical bit array Q acted by the logical gate g is transformed into a physical bit array Q '═ pi (Q) by using a mapping pi, so that the logical gate g becomes the physical gate g', actual operation contents of the logical gate and the physical gate are not changed, and only the operation object is changed from the logical bit to the physical bit; the quantum instruction simulation execution and maximum parallelization algorithm is responsible for transmitting a physical instruction corresponding to a physical gate g' or SWAP operation acting on a physical bit, and comprises the following steps:

for each physical bit Q ' ∈ Q ' acted on by physical gate g ', its latest ending busy time t is found _m ＝max{q.t _end }，t _m T is less than or equal to t; let the execution time of the physical gate g 'be tau, then for each physical bit Q'. epsilon.Q ', set Q'. t _end ＝t _m +τ；

And for the SWAP operation, transmitting a physical implementation instruction corresponding to the SWAP operation.

6. The logical-physical bit remapping method for the noisy medium-sized quantum device according to claim 1, wherein the step of obtaining the SWAP operation sequence S by using the heuristic algorithm of the optimal route comprises:

step D1, let SWAP operation sequence S { };

step D2, finding the current SWAP candidate set S _c (ii) a Assuming that the logic gate g is a remote gate, the logic bit array Q acted on by the logic gate g is converted into a physical bit array Q 'by mapping pi to pi (Q), and the logic gate g becomes a physical gate g', here called remote gate g ', for the free bits Q' in the bit array Q ₁ ', if any, associated with the physical bit q ₁ ' Adjacent bits q ₂ ' and physical bit q ₂ 'Idle', physical bit q is called ₁ ' and q ₂ SWAP operations between' are candidate SWAP;

step D3, for each candidate SWAP operation s _k ∈S _c Calculating the priority;

d4, selecting the SWAP operation s with the highest priority, if the priority of the SWAP operation s is less than 1; or if the adjacent relation between the physical bits can be modeled as a rectangular grid, the priority of the SWAP operation S is less than <1,0>, the algorithm is terminated, and the SWAP operation sequence S obtained at the current stage is output;

step D5, update SWAP operation sequence: s ═ es { S };

step D6, from SWAP candidate set S _c Removing SWAP operation s and SWAP operation with common physical bit with the SWAP operation s;

step D7, updating mapping, pi ═ pi- _s That is, the SWAP operation s is performed at the initial mapping of π, and the mapping becomes π! memory cells _s ；

And D8, returning to the step D3 until the SWAP candidate set is empty.

7. The method of claim 6, wherein the candidate SWAP operations s are selected from a group consisting of a global operation, a motion, a global operation, a motion, a global operation, a motion, a, and a _k The priority calculation method comprises the following steps:

defining the distance of the logic gate g as the minimum SWAP operand required for realizing the logic gate g, noted as g.d;

defining a total candidate distance

For each candidate SWAP operation s _k ＝SWAP(q ₁ ’,q ₂ ') perform a candidate SWAP operation s _k Updating the initial mapping pi ═ pi _ non conducting phosphor _s Defining a heuristic function:

H _basic the higher (π, s), the SWAP operation s _k The greater the positive impact, the higher the priority H (π, s) _k )＝H _basic (π,s)；

If the neighborhood between physical bits can be modeled as a rectangular grid; each physical bit has location attributes x and y, g ═ g (q) if logic gate g is a dual-quantum remote gate ₁ ,q ₂ ) Two bits q of its effect ₁ And q is ₂ The horizontal and vertical distances therebetween are defined as:

HD(π,g)＝|q ₁ ’.x-q ₂ ’.x|

VD(π,g)＝|q ₁ ’.y-q ₂ ’.y|

then the distance d (pi, g) ═ HD (pi, g) + VD (pi, g) -1;

in the rectangular grid, for a bit pair with an arbitrary distance d (pi, g), when | VD (pi, g) -HD (pi, g) | of the bit pair is smaller, the number of shortest routing paths possible between the bit pair is larger; using this property, for each candidate SWAP operation s _k The following heuristic function is introduced for auxiliary selection:

8. The method of claim 7, wherein if all candidate SWAP operations s are performed, the method comprises _k Are all less than 1 or less than<1,0>At this time, there may be two cases: in the first case, some candidate gates need routing, but some physical bit corresponding to these candidate gates is in busy state, or the routing will interfere with other executing gates; in the second case, there are candidate gates that need routes that do not interfere with existing gates;

for the second case, the following processing is adopted:

from SWAP candidate set S _c Selecting the SWAP operation s with the highest priority;

from SWAP candidate set S _c Removing SWAP operation s and SWAP operation having common bit with SWAP operation s, executing s and updating mapping pi ═ pi- _s ；

The normal routing algorithm is re-executed until there are no candidate SWAP with a priority of no less than 1 or <1,0 >.