CN117594658A - Groove type field effect transistor and preparation method thereof - Google Patents

Abstract

The invention discloses a groove type field effect transistor and a preparation method thereof, which belong to the technical field of semiconductors, and the groove type field effect transistor comprises: a substrate layer; an epitaxial layer; a first body region; a second body region; a first trench; a second trench; a first source region; and a second source region. According to the invention, the depth of the first body region and the depth of the second body region are preset, so that the depth of the second body region is smaller than that of the first body region, and the second body region with the shallower depth compared with that of the first body region is obtained, so that the length of the body region is reduced, and the threshold voltage for starting the diode is further reduced, and the body diode is started at a lower threshold voltage, thereby reducing the reverse freewheeling power consumption.

Description

Groove type field effect transistor and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a trench type field effect transistor and a preparation method thereof.

Background

The trench field effect transistor plays an indispensable role in the field of semiconductor technology, and is critical for the development of power semiconductor devices. However, due to the high complexity in the semiconductor technology field, the parasitic diode of the conventional trench MOS is a PN junction diode formed by a P-type body base region and an N-type epitaxial layer, the turn-on voltage is about 1V, and when reverse freewheeling occurs, current flows through the body diode, so that the turn-on voltage is higher and the power consumption is larger.

Therefore, how to turn on the body diode with a lower turn-on voltage to reduce the reverse freewheeling power consumption is a urgent problem to be solved.

Disclosure of Invention

Based on this, the embodiment of the application provides a trench field effect transistor and a preparation method thereof, so as to solve the problems that current passes through a body diode when a parasitic diode of a conventional trench MOS is in reverse freewheeling, and the turn-on voltage is high and the power consumption is high.

In a first aspect, embodiments of the present application provide a trench field effect transistor and a method for manufacturing the same, including:

a substrate layer of a first conductivity type;

an epitaxial layer of a first conductivity type, the epitaxial layer being located on the substrate layer;

a first body region of a second conductivity type, the first body region being located on the epitaxial layer;

a second body region of a second conductivity type, the second body region being located on the epitaxial layer, the first body region being adjacent the second body region, the second body region having a depth less than a depth of the first body region;

the first groove penetrates through the first body region along the depth direction and extends into the epitaxial layer, and a first grid structure is arranged in the first groove;

the second groove penetrates through the second body region along the depth direction and extends into the epitaxial layer, and a second grid structure is arranged in the second groove;

a first source region of a first conductivity type, the first source region being located on the first body region;

a second source region of the first conductivity type, the second source region being located on the second body region.

Optionally, the second body region has an ion doping concentration that is less than the ion doping concentration of the first body region.

Optionally, forming the first gate structure includes: forming a first dielectric layer of the first gate structure and a first gate electrode positioned on the first dielectric layer;

forming the second gate structure includes: and forming a second dielectric layer of the second gate structure, and a second gate positioned on the second dielectric layer, wherein the thickness of the second dielectric layer is smaller than that of the first dielectric layer.

Optionally, forming the second dielectric layer of the second gate structure includes: forming a bottom dielectric layer above the bottom of the second trench, an upper wall dielectric layer on the side wall of the second trench, and a lower wall dielectric layer on the side wall of the second trench, wherein the upper wall dielectric layer is above the lower wall dielectric layer, and the thickness of the upper wall dielectric layer is smaller than that of the lower wall dielectric layer.

Optionally, a first contact hole with a preset shape is disposed on the second gate structure, a second contact hole is disposed between the first source region and the second source region, and metal is filled in the first contact hole and the second contact hole, so that the second gate structure is connected with the first source region and the second source region through the first contact hole, the metal and the second contact hole.

Optionally, the depth range of the first contact hole and the second contact hole is 0.3um-0.5um, and the width range is 0.2um-0.4um.

Optionally, the depth range of the first body region is 1um-2um, and the depth range of the second body region is 0.5um-1um.

Optionally, an interlayer dielectric layer is located on the first source region and the second source region.

Optionally, a metal layer is located on the interlayer dielectric layer.

In a second aspect, embodiments of the present application provide a trench field effect transistor and a method for manufacturing the same, including:

providing a substrate layer of a first conductivity type;

forming an epitaxial layer of a first conductivity type on the substrate layer;

forming a first groove extending to the inside of the epitaxial layer along the depth direction, and forming a first grid structure in the first groove; forming a second groove extending to the inside of the epitaxial layer along the depth direction, and forming a second grid structure in the second groove;

forming a first body region of a second conductivity type on the epitaxial layer, enabling the first trench to penetrate through the first body region, forming a second body region of the second conductivity type on the epitaxial layer, enabling the second trench to penetrate through the second body region, and enabling the depth of the second body region to be smaller than that of the first body region;

a first source region of a first conductivity type is formed over the first body region and a second source region of the first conductivity type is formed over the second body region.

Optionally, forming the first gate structure in the first trench includes:

growing a first dielectric layer with a first preset thickness on the inner wall of the first groove, etching the first dielectric layer, and reserving the first dielectric layer at the bottom of the first groove;

and growing a first dielectric layer with a second preset thickness on the side wall of the first groove, depositing a first grid electrode on the first dielectric layer, and etching part of the first grid electrode to obtain a first grid electrode structure in the first groove.

Optionally, forming the second gate structure in the second trench includes:

coating photoresist on a first grid structure in the first groove, etching the upper part of the grid and the upper part of the dielectric layer in the second groove, reserving the lower part of the grid, and taking the lower part of the dielectric layer as a bottom dielectric layer and a lower wall dielectric layer of the second dielectric layer;

etching the lower part of the grid electrode, removing the photoresist, and growing an upper wall dielectric layer, wherein the upper wall dielectric layer is positioned above the lower wall dielectric layer, and a second dielectric layer is formed by the bottom dielectric layer, the lower dielectric layer and the upper wall dielectric layer;

and depositing a second grid electrode on the second dielectric layer, and etching part of the second grid electrode to obtain a second grid electrode structure in the second groove.

Compared with the prior art, the embodiment of the application has the beneficial effects that: by presetting the depths of the first body region and the second body region, the depth of the second body region is smaller than that of the first body region, so that a second body region with shallower body region depth compared with the first body region is obtained, the length of the body region is reduced, and then the threshold voltage for starting the diode is reduced, and the body diode is started at a lower threshold voltage, so that the reverse freewheeling power consumption is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a trench type field effect transistor structure according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a corresponding structure obtained during each manufacturing process of a trench type field effect transistor according to an embodiment of the present invention;

fig. 3 is a schematic diagram of a corresponding structure obtained during each manufacturing process of a trench field effect transistor according to an embodiment of the present invention;

fig. 4 to 14 are flowcharts of a method for manufacturing a trench field effect transistor according to an embodiment of the present invention;

fig. 15 is a flowchart of a method for manufacturing a trench field effect transistor according to an embodiment of the present invention;

fig. 16 is a flowchart of a method for manufacturing a trench field effect transistor according to an embodiment of the present invention;

fig. 17-27 are flowcharts of a method for manufacturing a trench field effect transistor according to another embodiment of the present invention;

description of the reference numerals:

101. a substrate layer; 102. an epitaxial layer; 103. a first body region; 104. a second body region; 105. a first trench; 106. a first gate structure; 107. a second trench; 108. a second gate structure; 109. a first source region; 110. a second source region; 111. a first gate; 112. a first dielectric layer; 112-1, a first bottom dielectric layer; 113. a second gate; 114. a second dielectric layer; 114-1 bottom dielectric layer; 114-2 lower wall dielectric layer; 114-3 upper wall dielectric layer; 115. an interlayer dielectric layer; 116. a metal layer; 117. a first contact hole; 118. a second contact hole; 119. a hard mask dielectric layer; 120. and (3) photoresist.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system configurations, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It should also be understood that the term "and/or" as used in this specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".

In addition, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used merely to distinguish between descriptions and are not to be construed as indicating or implying relative importance.

Reference in the specification to "one embodiment" or "some embodiments" or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," and the like in the specification are not necessarily all referring to the same embodiment, but mean "one or more but not all embodiments" unless expressly specified otherwise. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless expressly specified otherwise.

It should be understood that the sequence numbers of the steps in the following embodiments do not mean the order of execution, and the execution order of the processes should be determined by the functions and the internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

In order to illustrate the technical solution of the present application, the following description is made by specific examples.

In one embodiment, as shown in fig. 1, a trench field effect transistor is provided, including:

a substrate layer 101 of a first conductivity type;

an epitaxial layer 102 of a first conductivity type, the epitaxial layer 102 being located on the substrate layer 101;

a first body region 103 of a second conductivity type, said first body region 103 being located on said epitaxial layer 102;

a second body region 104 of a second conductivity type, the second body region 104 being located on the epitaxial layer 102, the first body region 103 being adjacent to the second body region 104, the second body region 104 having a depth less than a depth of the first body region 103;

a first trench 105, wherein the first trench 105 penetrates through the first body region 103 along the depth direction and extends into the epitaxial layer 102, and a first gate structure 106 is disposed in the first trench 105;

a second trench 107, wherein the second trench 107 penetrates through the second body region 104 along the depth direction and extends into the epitaxial layer 102, and a second gate structure 108 is disposed in the second trench 107;

a first source region 109 of a first conductivity type, said first source region 109 being located on said first body region 103;

second source regions 110 of the first conductivity type the second source regions 110 are located on the second body region 104.

In the trench field effect transistor, the substrate layer 101 may be of a first conductivity type, the first conductivity type may be N-type or P-type, the ions doped In the substrate layer 101 may be N-type heavily doped ions, and the N-type doped ions may be aluminum ions, boron ions, indium (In), gallium (Ga), and the like.

In the trench field effect transistor, the epitaxial layer 102 is of the first conductivity type, the doped ions in the epitaxial layer 102 are N-type lightly doped ions, and the N-type lightly doped ions may be nitrogen ions, phosphorus ions, or the like.

In the trench field effect transistor, the first body 103 is P-type, and the first body 103 is usually opposite to the epitaxial layer 102, for example, a dopant such as phosphorus (P) is usually added in the N-type body, and a dopant such as boron (B) is usually added in the P-type body.

In the trench field effect transistor, the second body region 104 is P-type, and the second body region 104 is typically formed by a doping technique such as ion implantation and diffusion, and the second body region 104 is typically of a conductivity type opposite to that of the epitaxial layer 102.

In the trench field effect transistor, the first trench 105 is etched according to a predetermined shape, and extends into the epitaxial layer 102 through the first body 103 of the semiconductor device. For example, trenches are typically created by a manufacturing process such as photolithography, which is used to define the shape of the trench, or etching, which is used to etch the trench into the semiconductor material in a predetermined direction, the depth and shape of the trench depending on the design and desired function of the device.

In the trench field effect transistor, the second trench 107 is etched according to a predetermined shape, and extends into the epitaxial layer 102 through the second body region 104 of the semiconductor device. For example, trenches are typically used to isolate different portions of the device, define the boundaries or shape of electronic components, and in semiconductor devices, trenches are typically used to separate different electronic components to ensure that the electronic components do not interfere with each other.

In the trench field effect transistor, the first source region 109 is N-type, and the conductivity type is the same as that of the substrate layer 101 and the epitaxial layer 102, and is the first conductivity type.

In the trench field effect transistor, the second source region 110 is of N type, for example, the source region is usually of N type or P type semiconductor material, and the formation of the source region generally includes ion implantation or other doping process again, and the doping type can be set according to the actual situation in the practical application process.

According to the trench type field effect transistor, the depth of the first body region 103 and the depth of the second body region 104 are preset, so that the second body region 104 with the shallower depth compared with the depth of the first body region 103 is obtained, and the threshold voltage for starting the diode is reduced by presetting the length of the body region, so that the body diode is started with the lower threshold voltage, and the reverse freewheeling power consumption is reduced.

In an embodiment, the second body region 104 has an ion doping concentration that is less than the ion doping concentration of the first body region 103.

As shown in fig. 1, the first body region 103 is a P-type body region, and the ion doping concentration of the first body region 103 is 1×10 ¹⁷ cm ^-3 The second body region 104 is a P-type body region, and the doping concentration of the second body region 104 is 5×10 ¹⁶ cm ^-3 . The first body region 103 has a greater ion doping concentration than the second body region 104, i.e. dopingThe higher the impurity concentration, the larger the threshold voltage, the lower the doping concentration, the smaller the threshold voltage, and the specific doping degree can be set according to the use condition.

The ion doped in the body region may be boron ion, and the ion doping concentration refers to the density of a specific type of ion in the semiconductor crystal, and in the semiconductor manufacturing process, the conductive property of the semiconductor material is adjusted by controlling and adjusting the doping concentration of the ion, so that a region with high ion doping concentration has better conductivity, and a region with low ion doping concentration may show higher resistance or other properties.

According to the trench type field effect transistor, on the basis of limiting the depths of the first body region 103 and the second body region 104, the ion doping concentrations of the first body region 103 and the second body region 104 are further limited, so that the ion doping concentration of the second body region 104 is smaller than that of the first body region 103, the on-voltage of a diode of a trench MOS device is further reduced, and the on-loss of the diode is reduced.

In one embodiment, as shown in fig. 2, forming the first gate structure 106 includes: forming a first dielectric layer 112 of the first gate structure 106, and a first gate 111 on the first dielectric layer 112;

forming the second gate structure 108 includes: and forming a second dielectric layer 114 of the second gate structure 108, and a second gate 113 on the second dielectric layer 114, wherein the thickness of the second dielectric layer 114 is smaller than the thickness of the first dielectric layer 112.

Specifically, the first dielectric layer 112 and the second dielectric layer 114 are grown by a chemical vapor deposition process, where the first dielectric layer 112 and the second dielectric layer 114 may be silicon dioxide, polysilicon, metal, or other oxide materials, and the thickness of the second dielectric layer 114 is smaller than the thickness of the first dielectric layer 112, for example, the thickness of the first dielectric layer 112 ranges from 0.2um to 2um, the thickness of the lower wall dielectric layer 114-2 in the second dielectric layer 114 ranges from 0.2um to 2um, and the thickness of the upper wall dielectric layer 114-3 in the second dielectric layer 114 ranges from 0.1um to 1um.

In the trench field effect transistor of the embodiment of the present application, on the basis of defining the depths of the first body region 103 and the second body region 104 and defining the ion doping concentrations of the first body region 103 and the second body region 104, the thicknesses of the dielectric layers in the first gate structure 106 and the second gate structure 108 are further limited, the threshold voltage for diode turn-on is further reduced, the body diode is turned on with a lower threshold voltage, and the effect of reducing the reverse freewheeling power consumption is enhanced.

In one embodiment, as shown in fig. 2, forming the second dielectric layer 114 of the second gate structure 108 includes: a bottom dielectric layer 114-1 located above the bottom of the second trench 107, an upper wall dielectric layer 114-3 located on the sidewall of the second trench 107, and a lower wall dielectric layer 114-2 located on the sidewall of the second trench 107 are formed, the upper wall dielectric layer 114-3 is located above the lower wall dielectric layer 114-2, and the thickness of the upper wall dielectric layer 114-3 is smaller than the thickness of the lower wall dielectric layer 114-2.

For example, the bottom dielectric layer 114-1, the lower wall dielectric layer 114-2, and the upper wall dielectric layer 114-3 may be formed by an etching process, and for example, the thickness of the etched bottom dielectric layer 114-1 ranges from 0.06um to 0.3um, the thickness of the etched lower wall dielectric layer 114-2 ranges from 0.02um to 0.1um, and the thickness of the etched upper wall dielectric layer 114-3 ranges from 0.01um to 0.05um.

In the trench field effect transistor of the embodiment, the second gate structure 108 includes the second dielectric layer 114, the second dielectric layer 114 is formed by the bottom dielectric layer 114-1, the upper wall dielectric layer 114-3 and the lower wall dielectric layer 114-2, wherein the bottom dielectric layer 114-1 has the functions of reducing capacitance and increasing voltage resistance, and the threshold voltage of the diode on is reduced by the upper wall dielectric layer 114-3 and the lower wall dielectric layer 114-2.

In an embodiment, as shown in fig. 1, a first contact hole 117 with a preset shape is disposed on the second gate structure 108, a second contact hole 118 is disposed between the first source region 109 and the second source region 110, and the first contact hole 117 and the second contact hole 118 are filled with a metal 116, so that the second gate structure 108 is connected to the first source region 109 and the second source region 110 through the first contact hole 117, the metal 116, and the second contact hole 118.

Specifically, a first contact hole 117 is located on the second gate structure 108, a second contact hole 118 is located between the first source region 109 and the second source region 110, a metal 116 is generally used as a conductive material, the metal 116 is filled into the first contact hole 117 and the second contact hole 118, and an electrical connection is established through the first contact hole 117, the second contact hole 118, and the metal 116, thereby connecting the second gate structure 108, the first source region 109, and the second source region 110.

According to the trench type field effect transistor, the first contact hole 117, the second contact hole 118 and the metal 116 are arranged, and the second gate structure 108, the first source region 109 and the second source region 110 are connected, so that when the device in fig. 1 freewheels reversely, the source electrode is high in potential, the drain electrode is low in potential, and therefore the body diode is started at a lower threshold voltage, and normal operation and reliability of the device are ensured through current.

In one embodiment, the depth of the first contact hole 117 and the second contact hole 118 is in the range of 0.3um to 0.5um, and the width is in the range of 0.2um to 0.4um.

As shown in fig. 1, the depth refers to the distance from the aperture to the bottom of the aperture, the depth is used to determine the aperture depth, the width refers to the aperture span, the diameter or lateral dimension is used to determine the aperture diameter, and the contact holes are typically located on the surface of the semiconductor device, and are used to establish electrical connections to different parts of the device, and the shape of the first contact hole 117 and the second contact hole 118 may be pre-designed according to the specific situation, and the shape of the contact holes may be regular quadrilaterals, irregular polygons, circles, etc.

According to the trench field effect transistor, the first contact hole 117 and the second contact hole 118 are electrically connected with the second gate structure 108, the first source region 109 and the second source region 110 so as to be connected to different parts of a device, so that the body diode is turned on at a lower threshold voltage, and the reverse freewheeling power consumption is reduced.

In an embodiment, the depth of the first body region 103 ranges from 1um to 2um, and the depth of the second body region 104 ranges from 0.5um to 1um.

Specifically, the depth of the first body region 103 ranges from 1um to 2um, the depth of the second body region 104 ranges from 0.5um to 1um, and for example, the depth of the first body region 103 may also range from 0.8um to 1.8um, from 1.2um to 2.2um, and so on, and the depth of the second body region 104 may also range from 0.2um to 0.7um, from 0.8um to 1.3um.

According to the trench field effect transistor, the depth of the body region is deeper, the threshold voltage is higher, the length of the body region is reduced through presetting the depth ranges of the first body region 103 and the second body region 104, and then the threshold voltage for starting the diode is reduced, so that the body diode is started with lower threshold voltage, and the reverse freewheeling power consumption is reduced.

In one embodiment, a trench field effect transistor as shown in fig. 1 further includes: an interlayer dielectric layer 115 is located on the first source region 109 and the second source region 110.

Specifically, the material of the interlayer dielectric layer 115 may be silicon dioxide, silicon nitride, or the like.

In the trench field effect transistor of the embodiment of the present application, the interlayer dielectric layer 115 is disposed in the first source region 109 and the second source region 110, so as to obtain a structure and performance meeting design requirements in a subsequent step.

In one embodiment, a trench field effect transistor as shown in fig. 1 further includes: a metal layer 116 is located on the interlayer dielectric layer 115.

Specifically, the material of the metal layer 116 may be aluminum, silicon, copper alloy, or the like, and the metal layer 116 is generally used to draw out an electron current so as to input or output a current to the semiconductor device.

In a trench field effect transistor according to the embodiments of the present application, the metal layer 116 is generally used for connection, wire bonding, control of electronic channels, or external connection, and the metal layer 116 is generally precisely manufactured and arranged to ensure the normal operation and reliability of the device.

In an embodiment, as shown in fig. 3, the preparation method of the trench field effect transistor includes the following steps:

step S21 of providing a substrate layer 101 of a first conductivity type;

as shown in fig. 4, the first conductive type substrate layer 101 is heavily doped N-type, the substrate layer 101 may be a semiconductor material such as silicon (Si) or silicon carbide (SiC), and the first conductive type substrate layer 101 may be an N-type semiconductor material or a P-type semiconductor material. When the substrate layer 101 is of an N-type semiconductor material, the epitaxial layer 102 of the first conductivity type is also of an N-type semiconductor material formed on said substrate layer 101.

Step S22 of forming an epitaxial layer 102 of the first conductivity type on the substrate layer 101;

as shown in fig. 4, the epitaxial layer 102 of the first conductivity type is a lightly doped N-type epitaxial layer 102, and the epitaxial layer 102 has the same conductivity type as the substrate layer 101.

Step S23, forming a first trench 105 extending to the inside of the epitaxial layer 102 along the depth direction, and forming a first gate structure 106 in the first trench 105; forming a second trench 107 extending into the epitaxial layer 102 in the depth direction, and forming a second gate structure 108 in the second trench 107;

as shown in fig. 5, a hard mask dielectric layer 119 is deposited on the epitaxial layer 102, and the hard mask dielectric layer 119 may be silicon dioxide, first silicon oxide, first silicon nitride, or the like. Photoresist 120 is coated on the hard mask dielectric layer 119, photolithography is performed according to a preset trench pattern, dry etching is performed on the hard mask dielectric layer 119, the photoresist 120 is removed, the hard mask dielectric layer 119 is removed, and the first trench 105 and the second trench 107 are formed as shown in fig. 6.

As shown in fig. 7, a chemical vapor deposition process is used to grow a first dielectric layer 112 and a second dielectric layer 114 on the first trench 105 and the second trench 107, where the first dielectric layer 112 and the second dielectric layer 114 may be silicon dioxide, or may be polysilicon, metal, or other oxide materials. First dielectric layer 112 and second dielectric layer 114 are etched, as shown in fig. 8, leaving first bottom dielectric layer 112-1 and bottom dielectric layer 114-1. As shown in fig. 9, the first dielectric layer 112 is grown on the sidewall of the first trench 105, and the second dielectric layer 114 is grown on the sidewall of the second trench 107, and the growth speed and thickness may be preset according to the specific situation. As shown in fig. 10, the first gate 111 and the second gate 113 are deposited, and the first gate 111 and the second gate 113 may be polysilicon, metal, or the like. The first gate 111 and the second gate 113 are etched, as shown in fig. 11, to finally obtain a first gate structure 106 and a second gate structure 108, where the etching degree and the etching times may be preset according to specific usage conditions.

Step S24, forming a first body region 103 of a second conductivity type on the epitaxial layer 102, making the first trench 105 penetrate the first body region 103, forming a second body region 104 of the second conductivity type on the epitaxial layer 102, making the second trench 107 penetrate the second body region 104, and making the depth of the second body region 104 smaller than the depth of the first body region 103;

as shown in fig. 12, after the first gate structure 106 and the second gate structure 108 are obtained, first, a photoresist 120 is coated on the second gate structure 108, and ions with a higher doping concentration are implanted into the first body region 103, so as to form the first body region 103. The photoresist 120 is then removed, and as shown in fig. 13, ions with a lower doping concentration are implanted into the second body region 104 to form the second body region 104, wherein the depth of the second body region 104 is smaller than the depth of the first body region 103, for example, when the depth of the first body region 103 is 2um, the depth of the second body region 104 may be 1um, and when the depth of the first body region 103 is 1.8um, the depth of the second body region 104 may be 0.8um.

In step S25, a first source region 109 of the first conductivity type is formed on the first body region 103, and a second source region 110 of the first conductivity type is formed on the second body region 104.

As shown in fig. 14, the first source region 109 and the second source region 110 are formed by implanting ions of different doping concentrations into the first body region 103 and the second body region 104. The implanted ions may be arsenic ions, phosphorus ions, or the like.

Then, silicon dioxide is deposited on the first source region 109 and the second source region 110 to form an interlayer dielectric layer 115, a first contact hole 117 and a second contact hole 118 are etched into the interlayer dielectric layer 115, and finally a metal 116 is deposited in the first contact hole 117 and the second contact hole 118.

According to the preparation method of the embodiment, the depths of the first body region 103 and the second body region 104 are preset, so that the second body region 104 with the shallower depth compared with the first body region 103 is obtained, and the threshold voltage for starting the diode is reduced by reducing the length of the body region, so that the body diode is started with the lower threshold voltage, and the reverse freewheeling power consumption is reduced. In step S25, ions with more concentration are implanted into the first body region 103, ions with less concentration are implanted into the second body region 104, which is equivalent to implanting ions with different concentrations into the first body region 103 twice, so that the ion doping concentration of the second body region 104 is smaller than that of the first body region 103.

In one embodiment, as shown in fig. 15, in step S23, forming the first gate structure 106 in the first trench 105 includes:

step S231, growing a first dielectric layer 112 with a first preset thickness on the inner wall of the first trench 105, etching the first dielectric layer 112, and retaining the first dielectric layer 112 at the bottom of the first trench 105;

as shown in fig. 7 and 8, a first preset first dielectric layer 112 is grown on the inner wall of the first trench 105 by using a chemical vapor deposition process, for example, the thickness range of the first preset dielectric layer is 0.2um-2um, the first dielectric layer 112 is etched, the first bottom dielectric layer 112-1 is reserved, and the thickness range of the first bottom dielectric layer 112-1 is 0.06um-0.3um.

Step S232, growing a first dielectric layer 112 with a second preset thickness on the sidewall of the first trench 105, depositing a first gate 111 on the first dielectric layer 112, and etching a portion of the first gate 111 to obtain a first gate structure 106 in the first trench 105.

As shown in fig. 9-11, a dielectric layer with a second preset thickness is grown on the sidewall of the first trench 105, for example, the thickness of the dielectric layer with the second preset thickness ranges from 0.02um to 0.1um, the first gate 111 is deposited on the first dielectric layer 112, the thickness of the first gate 111 ranges from 0.2um to 2um, and the first gate 111 is etched to obtain the first gate structure 106 in the first trench 105.

According to the preparation method of the embodiment of the application, the thickness of the first grid structure 106 is limited, the threshold voltage for starting the diode is reduced, the body diode is started with lower threshold voltage, and the effect of reducing the reverse freewheeling power consumption is enhanced.

In one embodiment, as shown in fig. 16, in step S23, forming the second gate structure 108 in the second trench 107 includes:

step S233, coating photoresist 120 on the first gate structure 106 in the first trench 105, etching the upper part of the gate and the upper part of the dielectric layer in the second trench 107, reserving the lower part of the gate, and taking the lower part of the dielectric layer as the bottom dielectric layer 114-1 and the lower wall dielectric layer 114-2 of the second dielectric layer 114;

as shown in fig. 17, after the photoresist 120 is coated on the first gate structure 106 in the first trench 105, the second gate 113 of the second trench 107 is etched, and the upper second gate 113 and the upper second dielectric layer 114 are respectively etched. As shown in fig. 18, a lower second gate electrode 113 and a lower second dielectric layer 114 are obtained, and the lower second dielectric layer 114 is composed of a bottom dielectric layer 114-1 and a lower wall dielectric layer 114-2.

Step S234, etching the lower part of the grid electrode, removing the photoresist 120, and growing an upper wall dielectric layer 114-3, wherein the upper wall dielectric layer 114-3 is positioned above the lower wall dielectric layer 114-2, and a second dielectric layer 114 is formed by the bottom dielectric layer 114-1, the lower dielectric layer and the upper wall dielectric layer 114-3;

as shown in fig. 19, the lower portion of the second gate electrode 113 is etched to remove the photoresist 120. As shown in fig. 20, the upper wall dielectric layer 114-3 is grown, wherein the shape of the second dielectric layer 114 is a step-like shape, i.e. the thickness of the dielectric layers sequentially increases in order from top to bottom, for example, the thickness of the bottom dielectric layer 114-1 ranges from 0.06um to 0.3um, the thickness of the lower wall dielectric layer 114-2 ranges from 0.01um to 0.05um, the thickness of the upper wall dielectric layer 114-3 ranges from 0.005um to 0.025um, for example, the thickness of the upper wall dielectric layer 114-3 ranges from 0.025um, the thickness of the lower wall dielectric layer 114-2 ranges from 0.01um, and the thickness of the bottom dielectric layer 114-1 ranges from 0.06um.

In step S235, a second gate 113 is deposited on the second dielectric layer 114, and a portion of the second gate 113 is etched, so as to obtain a second gate structure 108 in the second trench 107.

As shown in fig. 21, a second gate 113 is deposited over the second dielectric layer 114. As shown in fig. 22, the second gate electrode 113 is etched. The second gate structure 108 is obtained, wherein the degree and number of depositions, etches may be preset according to the specific use case.

After the second gate structure 108 is formed, in step S25, a first body region 103 of a second conductivity type is formed on the epitaxial layer 102, the first trench 105 penetrates the first body region 103, a second body region 104 of the second conductivity type is formed on the epitaxial layer 102, the second trench 107 penetrates the second body region 104, and a depth of the second body region 104 is smaller than a depth of the first body region 103, including:

specifically, after the first gate structure 106 and the second gate structure 108 are obtained, as shown in fig. 23, first, a photoresist 120 is coated on the second gate structure 108, and ions with a higher concentration are implanted into the first body region 103, thereby forming the first body region 103. The photoresist 120 is then removed and less concentrated ions are implanted into the second body region 104 to form the second body region 104, as shown in fig. 24.

In step S26, forming a first source region 109 of a first conductivity type on the first body region 103 and forming a second source region 110 of the first conductivity type on the second body region 104 includes:

as shown in fig. 25, ions of different doping concentrations are implanted into the first body region 103 and the second body region 104, forming a first source region 109 and a second source region 110.

Then, as shown in fig. 25, silicon dioxide is deposited on the first source region 109 and the second source region 110 to form an interlayer dielectric layer 115. As shown in fig. 26, first contact hole 117 and second contact hole 118 are etched in interlayer dielectric layer 115. As shown in fig. 27, a metal 116 is finally deposited in the first contact hole 117 and the second contact hole 118.

In the preparation method of the embodiment, the depth of the first contact hole 117 is increased, two contact holes with equal depth are provided, and the first contact hole 117, the second contact hole 118 and the metal 116 are used for connecting the second gate structure 108, the first source region 109 and the second source region 110, so that the source electrode is at a high potential and the drain electrode is at a low potential during reverse freewheeling of the device in fig. 27, thereby starting the body diode with a lower threshold voltage and enhancing the effect of reducing the power consumption of the reverse freewheeling. So as to ensure the normal operation and reliability of the device through the current.

The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims (12)

1. A trench field effect transistor, comprising:

a substrate layer of a first conductivity type;

an epitaxial layer of a first conductivity type, the epitaxial layer being located on the substrate layer;

a first body region of a second conductivity type, the first body region being located on the epitaxial layer;

a second body region of a second conductivity type, the second body region being located on the epitaxial layer, the first body region being adjacent the second body region, the second body region having a depth less than a depth of the first body region;

the first groove penetrates through the first body region along the depth direction and extends into the epitaxial layer, and a first grid structure is arranged in the first groove;

the second groove penetrates through the second body region along the depth direction and extends into the epitaxial layer, and a second grid structure is arranged in the second groove;

a first source region of a first conductivity type, the first source region being located on the first body region;

a second source region of the first conductivity type, the second source region being located on the second body region.

2. The trench field effect transistor of claim 1 wherein the second body region has a lower ion doping concentration than the first body region.

3. The trench field effect transistor of claim 1, wherein forming said first gate structure comprises: forming a first dielectric layer of the first gate structure and a first gate electrode positioned on the first dielectric layer;

forming the second gate structure includes: and forming a second dielectric layer of the second gate structure, and a second gate positioned on the second dielectric layer, wherein the thickness of the second dielectric layer is smaller than that of the first dielectric layer.

4. The trench field effect transistor of claim 3, wherein forming the second dielectric layer of the second gate structure comprises: forming a bottom dielectric layer above the bottom of the second trench, an upper wall dielectric layer on the side wall of the second trench, and a lower wall dielectric layer on the side wall of the second trench, wherein the upper wall dielectric layer is above the lower wall dielectric layer, and the thickness of the upper wall dielectric layer is smaller than that of the lower wall dielectric layer.

5. The trench fet of claim 3 wherein a first contact hole of a predetermined shape is provided in the second gate structure, a second contact hole is provided between the first source region and the second source region, and metal is filled in the first contact hole and the second contact hole to connect the second gate structure to the first source region and the second source region through the first contact hole, the metal, and the second contact hole.

6. The trench fet of claim 5 wherein the first and second contact holes have a depth in the range of 0.3um to 0.5um and a width in the range of 0.2um to 0.4um.

7. A trench field effect transistor as claimed in claim 1 or 2 wherein the depth of the first body region is in the range 1um to 2um and the depth of the second body region is in the range 0.5um to 1um.

8. The trench field effect transistor of claim 1, further comprising:

and the interlayer dielectric layer is positioned on the first source region and the second source region.

9. The trench field effect transistor of claim 8, further comprising:

and the metal layer is positioned on the interlayer dielectric layer.

10. The preparation method of the trench field effect transistor is characterized by comprising the following steps of:

providing a substrate layer of a first conductivity type;

forming an epitaxial layer of a first conductivity type on the substrate layer;

forming a first groove extending to the inside of the epitaxial layer along the depth direction, and forming a first grid structure in the first groove; forming a second groove extending to the inside of the epitaxial layer along the depth direction, and forming a second grid structure in the second groove;

forming a first body region of a second conductivity type on the epitaxial layer, enabling the first trench to penetrate through the first body region, forming a second body region of the second conductivity type on the epitaxial layer, enabling the second trench to penetrate through the second body region, and enabling the depth of the second body region to be smaller than that of the first body region;

a first source region of a first conductivity type is formed over the first body region and a second source region of the first conductivity type is formed over the second body region.

11. The method of manufacturing of claim 10, wherein forming a first gate structure in the first trench comprises:

growing a first dielectric layer with a first preset thickness on the inner wall of the first groove, etching the first dielectric layer, and reserving the first dielectric layer at the bottom of the first groove;

and growing a first dielectric layer with a second preset thickness on the side wall of the first groove, depositing a first grid electrode on the first dielectric layer, and etching part of the first grid electrode to obtain a first grid electrode structure in the first groove.

12. The method of manufacturing of claim 11, wherein forming a second gate structure in the second trench comprises:

coating photoresist on a first grid structure in the first groove, etching the upper part of the grid and the upper part of the dielectric layer in the second groove, reserving the lower part of the grid, and taking the lower part of the dielectric layer as a bottom dielectric layer and a lower wall dielectric layer of the second dielectric layer;

etching the lower part of the grid electrode, removing the photoresist, and growing an upper wall dielectric layer, wherein the upper wall dielectric layer is positioned above the lower wall dielectric layer, and a second dielectric layer is formed by the bottom dielectric layer, the lower dielectric layer and the upper wall dielectric layer;

and depositing a second grid electrode on the second dielectric layer, and etching part of the second grid electrode to obtain a second grid electrode structure in the second groove.