CN117594600A

CN117594600A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN117594600A
Application number: CN202310550260.5A
Authority: CN
Inventors: 刘贤琯; 李善英; 全夏英; 全辉锡; 车知勋
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2022-08-09
Filing date: 2023-05-16
Publication date: 2024-02-23
Also published as: JP2024024581A; US20240055428A1; EP4333041A3; TW202408012A; KR20240020876A; EP4333041A2

Abstract

A semiconductor device, comprising: a substrate including an NMOSFET region and a PMOSFET region; first and second channel patterns respectively located on the NMOSFET region and the PMOSFET region, each including respective semiconductor patterns spaced apart from each other and vertically stacked; first and second source/drain patterns on the NMOSFET region and the PMOSFET region and connected to the first and second channel patterns, respectively; and a gate electrode on the first channel pattern and the second channel pattern. The gate electrode includes a first internal electrode between adjacent semiconductor patterns of the first channel pattern and a second internal electrode between adjacent semiconductor patterns of the second channel pattern. The top surface of the first inner electrode is more convex than the top surface of the second inner electrode.

Description

Semiconductor device and method for manufacturing the same

Cross Reference to Related Applications

The present application claims the benefit of korean patent application No.10-2022-0099142 filed at the korean intellectual property office on day 8 and 9 of 2022, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present inventive concept relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a field effect transistor and a method of manufacturing the same.

Background

A semiconductor device includes an integrated circuit including a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). As the size and design rules of semiconductor devices have been reduced, the size of MOSFETs has also been reduced. The shrinking size of the MOSFET may deteriorate the operation properties of the semiconductor device. Accordingly, various researches have been conducted to develop a method of manufacturing a semiconductor device having superior performance while overcoming limitations caused by high integration of the semiconductor device.

Disclosure of Invention

Some example embodiments of the inventive concepts provide a semiconductor device having increased reliability and improved electrical properties.

Some example embodiments of the inventive concepts provide a method of manufacturing a semiconductor device having increased reliability and improved electrical properties.

According to some example embodiments of the inventive concepts, a semiconductor device may include:

a substrate including an NMOSFET region and a PMOSFET region opposite to each other; a first channel pattern on the NMOSFET region and a second channel pattern on the PMOSFET region, each of the first and second channel patterns including a plurality of semiconductor patterns spaced apart from each other and vertically stacked; a first source/drain pattern on the NMOSFET region, the first source/drain pattern being connected to the first channel pattern, and a second source/drain pattern on the PMOSFET region, the second source/drain pattern being connected to the second channel pattern; and a gate electrode on the first channel pattern and the second channel pattern. The gate electrode may include: a first internal electrode located between adjacent semiconductor patterns of the plurality of semiconductor patterns of the first channel pattern; and a second internal electrode located between adjacent semiconductor patterns of the plurality of semiconductor patterns of the second channel pattern. The top surface of the first inner electrode may be more convex than the top surface of the second inner electrode.

According to some example embodiments of the inventive concepts, a semiconductor device may include: a substrate including an active pattern; a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked; a source/drain pattern connecting the plurality of semiconductor patterns to each other; and a gate electrode on the plurality of semiconductor patterns. The gate electrode may include a first internal electrode and a second internal electrode adjacent to each other. The plurality of semiconductor patterns may include a first semiconductor pattern between the first and second internal electrodes. The first semiconductor pattern may include: a central portion located between the raised top surface of the first inner electrode and the raised bottom surface of the second inner electrode; and a side portion connected to the source/drain pattern. The thickness of the central portion may have a minimum value at the center of the central portion of the first semiconductor pattern, and may gradually increase in a direction from the center of the central portion of the first semiconductor pattern toward the side portion of the first semiconductor pattern, the minimum value of the thickness of the central portion of the first semiconductor pattern being the minimum thickness of the central portion of the first semiconductor pattern. The ratio of the minimum thickness of the central portion of the first semiconductor pattern to the thickness of the side portions of the first semiconductor pattern may be in the range of about 0.2 to about 0.8.

According to some example embodiments of the inventive concepts, a semiconductor device may include: a substrate including an NMOSFET region and a PMOSFET region opposite to each other; a device isolation layer filling the trench between the NMOSFET region and the PMOSFET region; a first channel pattern on the NMOSFET region and a second channel pattern on the PMOSFET region, each of the first and second channel patterns including a plurality of semiconductor patterns spaced apart from each other and vertically stacked; a first source/drain pattern on the NMOSFET region, the first source/drain pattern being connected to the first channel pattern, and a second source/drain pattern on the PMOSFET region, the second source/drain pattern being connected to the second channel pattern; a gate electrode on the first channel pattern and the second channel pattern, the gate electrode including a first internal electrode between adjacent semiconductor patterns of the plurality of semiconductor patterns of the first channel pattern and a second internal electrode between adjacent semiconductor patterns of the plurality of semiconductor patterns of the second channel pattern; a gate dielectric layer surrounding each of the first and second internal electrodes; a gate spacer on sidewalls of the gate electrode; a gate capping pattern on a top surface of the gate electrode; an interlayer dielectric layer on the gate capping pattern; an active contact penetrating the interlayer dielectric layer to be electrically connected with one of the first source/drain pattern and the second source/drain pattern; a metal-semiconductor compound layer between the active contact and the first source/drain pattern or the second source/drain pattern; a gate contact penetrating the interlayer dielectric layer and the gate capping pattern to be electrically connected with the gate electrode; a first metal layer on the interlayer dielectric layer, the first metal layer including a power line and a first wiring line, the first wiring line electrically connected to a separate corresponding contact of the active contact or the gate contact; and a second metal layer on the first metal layer. The second metal layer may include a second wiring line electrically connected to the first metal layer. The first channel pattern may include a first semiconductor pattern adjacent to the convex top surface of the first internal electrode. The second channel pattern may include a second semiconductor pattern adjacent to a top surface of the second internal electrode. The maximum thickness of the first inner electrode may be greater than the maximum thickness of the second inner electrode. The minimum thickness of the first semiconductor pattern may be smaller than the minimum thickness of the second semiconductor pattern.

According to some example embodiments of the inventive concepts, a method of manufacturing a semiconductor device may include: forming a stack pattern on a substrate, the stack pattern including active layers and sacrificial layers alternately stacked on the substrate; forming a sacrificial pattern on the stacked pattern, the sacrificial pattern extending in a first direction; etching the stack pattern using the sacrificial pattern as a mask to form recesses in the stack pattern such that active layers of the stack pattern each include adjacent semiconductor patterns exposed through the recesses; performing a selective epitaxial growth process in which adjacent semiconductor patterns exposed by the recess are used as seeds to form source/drain patterns filling the recess; removing the sacrificial pattern and the sacrificial layer to form an internal region between adjacent semiconductor patterns; partially forming a spacer layer in the inner region; performing a dry etching process on the spacer layer to reduce the thickness of the spacer layer in the vertical direction; performing a wet etching process on the spacer layer to expose the adjacent semiconductor patterns; and forming an internal electrode in the internal region. The wet etching process may overetch the adjacent semiconductor patterns so that the inner region has a convex bottom surface and a convex top surface.

Drawings

Fig. 1, 2 and 3 illustrate conceptual diagrams showing logic units of a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 4 illustrates a plan view showing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 5A, 5B, 5C, and 5D illustrate cross-sectional views taken along lines A-A ', B-B', C-C ', and D-D', respectively, of fig. 4 according to some example embodiments of the inventive concepts.

Fig. 6A illustrates an enlarged view showing an example of the portion M depicted in fig. 5A according to some example embodiments of the inventive concepts.

Fig. 6B illustrates an enlarged view showing an example of the portion N depicted in fig. 5B according to some example embodiments of the inventive concepts.

Fig. 7A, 7B, 8A, 8B, 9A, 9B, 9C, 10A, 10B, 10C, 11A, 11B, 11C, 12A, 12B, and 12C illustrate cross-sectional views showing a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 13A, 14A, 15A and 16A illustrate enlarged views showing a method of forming the portion M depicted in fig. 11A according to some example embodiments of the inventive concepts.

Fig. 13B, 14B, 15B, and 16B illustrate enlarged views showing a method of forming the portion N depicted in fig. 11B according to some example embodiments of the inventive concepts.

Fig. 17 illustrates a cross-sectional view taken along line D-D' of fig. 4, showing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 18 illustrates a plan view taken along line P-P' of fig. 17 according to some example embodiments of the inventive concepts.

Fig. 19, 20, and 21 illustrate cross-sectional views showing methods of manufacturing the semiconductor device depicted in fig. 17 and 18, according to some example embodiments of the inventive concepts.

Fig. 22, 23 and 24 illustrate enlarged views of a portion M depicted in fig. 5A, showing semiconductor devices according to some example embodiments of the inventive concepts.

Fig. 25 illustrates a cross-sectional view taken along line A-A' of fig. 4, showing a semiconductor device according to some example embodiments of the inventive concepts.

Fig. 26A and 26B illustrate enlarged views showing a portion M of fig. 5A and a portion N of fig. 5B, respectively, according to some example embodiments of the inventive concepts.

Fig. 27A and 27B illustrate enlarged views showing a portion M of fig. 5A and a portion N of fig. 5B, respectively, according to some example embodiments of the inventive concepts.

Detailed Description

Referring to fig. 1, a single height unit SHC may be provided. For example, the substrate 100 may be provided with the first and second power lines m1_r1 and m1_r2 thereon. The first power line m1_r1 may be a path for providing the source voltage VSS (e.g., a ground voltage). The second power line m1_r2 may be a path for providing the drain voltage VDD (e.g., a power supply voltage).

The single-height unit SHC may be defined between the first power line m1_r1 and the second power line m1_r2. The single-height unit SHC may include one first active region AR1 and one second active region AR2. One of the first active region AR1 and the second active region AR2 may be a PMOSFET (P-type metal oxide semiconductor field effect transistor) region, and the other of the first active region AR1 and the second active region AR2 may be an NMOSFET (N-type metal oxide semiconductor field effect transistor) region. For example, the single-height cell SHC may have a Complementary Metal Oxide Semiconductor (CMOS) structure disposed between the first power line m1_r1 and the second power line m1_r2.

Each of the first active region AR1 and the second active region AR2 may have a first width W1 in the first direction D1. The first height HE1 may be defined as indicating a length in the first direction D1 of the single-height unit SHC. The first height HE1 may be substantially the same as a distance (e.g., a pitch) between the first power line m1_r1 and the second power line m1_r2.

The single-height unit SHC may constitute one logic unit. In this specification, a logic unit may represent a logic device such as AND, OR, XOR, XNOR and an inverter that performs a specific function. For example, the logic cell may include transistors for constituting a logic device, and may further include wiring lines connecting the transistors to each other.

Referring to fig. 2, a dual height unit DHC may be provided. For example, the substrate 100 may be provided with a first power line m1_r1, a second power line m1_r2, and a third power line m1_r3. The first power line m1_r1 may be arranged between the second power line m1_r2 and the third power line m1_r3. The third power line m1_r3 may be a path for providing the source voltage VSS.

The dual height unit DHC may be defined between the second power line m1_r2 and the third power line m1_r3. The dual height cell DHC may include two first active regions AR1 and two second active regions AR2.

One of the two second active regions AR2 may be adjacent to the second power line m1_r2. The other of the two second active regions AR2 may be adjacent to the third power line m1_r3. The two first active regions AR1 may be adjacent to the first power lines m1_r1. The first power line m1_r1 may be disposed between the two first active regions AR1 when viewed in a plane.

The second height HE2 may be defined to indicate a length of the dual height unit DHC in the first direction D1. The second height HE2 may be approximately twice the first height HE1 of fig. 1. The two first active regions AR1 of the dual height cell DHC may be commonly connected together to serve as one active region.

In the inventive concept, the dual height unit DHC shown in fig. 2 may be defined as a multi-height unit. Although not shown, the multi-level cell may include a three-level cell having a cell height about three times the cell height of the single-level cell SHC.

Referring to fig. 3, a first single-height unit SHC1, a second single-height unit SHC2, and a dual-height unit DHC, which are two-dimensionally arranged, may be provided on the substrate 100. The first single-height unit SHC1 may be located between the first power line m1_r1 and the second power line m1_r2. The second single-height unit SHC2 may be located between the first power line m1_r1 and the third power line m1_r3. The second single-height unit SHC2 may be adjacent to the first single-height unit SHC1 in the first direction D1.

The dual height unit DHC may be disposed between the second power line m1_r2 and the third power line m1_r3. The dual height unit DHC may be adjacent to the first single height unit SHC1 and the second single height unit SHC2 in the second direction D2.

The separation structure DB may be disposed between the first single-height unit SHC1 and the double-height unit DHC and between the second single-height unit SHC2 and the double-height unit DHC. The separation structure DB may electrically separate the active region of the dual height unit DHC from the active region of each of the first single height unit SHC1 and the second single height unit SHC 2.

Fig. 4 illustrates a plan view showing a semiconductor device according to some example embodiments of the inventive concepts. Fig. 5A, 5B, 5C, and 5D illustrate cross-sectional views taken along lines A-A ', B-B', C-C ', and D-D', respectively, of fig. 4, according to some example embodiments of the inventive concepts. Fig. 6A illustrates an enlarged view showing an example of the portion M depicted in fig. 5A according to some example embodiments of the inventive concepts. Fig. 6B illustrates an enlarged view showing an example of the portion N depicted in fig. 5B according to some example embodiments of the inventive concepts. The semiconductor device depicted in fig. 4 and 5A to 5D is a detailed example of the single-height unit SHC shown in fig. 1.

Referring to fig. 4 and 5A to 5D, a single-height unit SHC may be disposed on the substrate 100. The single-height unit SHC may be provided thereon with logic transistors included in a logic circuit. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, or silicon germanium. For example, the substrate 100 may be a silicon substrate.

The substrate 100 may include a first active region AR1 and a second active region AR2. Each of the first active region AR1 and the second active region AR2 may extend in the second direction D2. In some example embodiments, the first active region AR1 may be an NMOSFET region and the second active region AR2 may be a PMOSFET region.

As shown in fig. 4 and 5A to 5D, the first direction D1 may extend parallel to the top surface 100a and/or the bottom surface 100b of the substrate 100, the second direction D2 may extend parallel to the top surface 100a and/or the bottom surface 100b of the substrate 100 and may also extend perpendicular to the first direction D1, and the third direction D3 may extend perpendicular to the top surface 100a and/or the bottom surface 100b of the substrate 100 and may thus extend perpendicular to both the first direction D1 and the second direction D2.

The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed on an upper portion of the substrate 100. The first active pattern AP1 may be disposed on the first active region AR1, and the second active pattern AP2 may be disposed on the second active region AR2. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertically protruding portions of the substrate 100.

The device isolation layer ST may be disposed on the substrate 100. The device isolation layer ST may fill the trench TR. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover any one of the first channel pattern CH1 and the second channel pattern CH2, which will be discussed below.

The first channel pattern CH1 may be disposed on the first active pattern AP 1. The second channel pattern CH2 may be disposed on the second active pattern AP 2. Each of the first and second channel patterns CH1 and CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked in order. The first, second, and third semiconductor patterns SP1, SP2, and SP3 may be spaced apart from each other in the vertical direction (or the third direction D3).

Each of the first, second, and third semiconductor patterns SP1, SP2, and SP3 may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, each of the first, second, and third semiconductor patterns SP1, SP2, and SP3 may include crystalline silicon, e.g., monocrystalline silicon. In some example embodiments of the inventive concepts, the first, second, and third semiconductor patterns SP1, SP2, and SP3 may be stacked nano-sheets.

The plurality of first source/drain patterns SD1 may be disposed on the first active pattern AP 1. A plurality of first recesses RCS1 may be formed at an upper portion of the first active pattern AP 1. The first source/drain pattern SD1 may be correspondingly disposed in the first recess RCS 1. As described herein, where an element ("structure") is described as being "disposed correspondingly" to another element, structure, space, etc., and/or having a surface that "corresponds to" another element, structure, space, etc., it will be understood that the surface of the element may be in contact with, and may have a shape complementary to, the corresponding surface of the other element, structure, space, etc. The first source/drain pattern SD1 may be an impurity region of a first conductivity type (e.g., n-type). The first channel pattern CH1 may be interposed between a pair of first source/drain patterns SD 1. For example, the pair of first source/drain patterns SD1 may be connected to each other through the stacked first, second and third semiconductor patterns SP1, SP2 and SP3.

The plurality of second source/drain patterns SD2 may be disposed on the second active pattern AP 2. A plurality of second recesses RCS2 may be formed at an upper portion of the second active pattern AP 2. The second source/drain pattern SD2 may be correspondingly disposed in the second recess RCS 2. The second source/drain pattern SD2 may be an impurity region of a second conductivity type (e.g., p-type). The second channel pattern CH2 may be interposed between a pair of second source/drain patterns SD 2. For example, the pair of second source/drain patterns SD2 may be connected to each other through the stacked first, second and third semiconductor patterns SP1, SP2 and SP 3.

The first source/drain pattern SD1 and the second source/drain pattern SD2 may be epitaxial patterns formed through a selective epitaxial growth process. For example, each of the first source/drain pattern SD1 and the second source/drain pattern SD2 may have a top surface higher than an upper surface of the third semiconductor pattern SP 3. For another example, at least one of the first source/drain pattern SD1 and the second source/drain pattern SD2 may have a top surface substantially at the same level as the top surface of the third semiconductor pattern SP 3.

In this specification, the terms "horizontal", "vertical horizontal", "depth", "height", and the like may refer to a vertical height (e.g., a vertical distance in a third direction D3) measured from a reference location (e.g., the top surface 100a or the bottom surface 100b of the substrate 100) in a direction perpendicular to a plane or surface at the reference location (e.g., the third direction D3, which may be a vertical direction perpendicular to the top surface 100a and/or the bottom surface 100b of the substrate 100). For example, where elements (e.g., surfaces) are described herein as being at different levels, it will be understood that the respective distances of the elements in the vertical direction (e.g., third direction D3) from a reference location (e.g., top surface 100a of substrate 100) may be different from one another. In another example, where the level of a first element is described herein as being between at least two other elements, it will be understood that the first element is vertically between the at least two other elements. In another example, where the level of a first element is described herein as being lower, less than, or less than the level of a second element, it will be understood that the distance of the first element from a reference location (e.g., the top surface 100a of the substrate 100) in the vertical direction may be less than the distance of the second element from the reference location in the vertical direction. In another example, where the level of a first element is described herein as being higher, greater, or greater than the level of a second element, it will be appreciated that the distance of the first element from a reference location (e.g., the top surface 100a of the substrate 100) in the vertical direction may be greater than the distance of the second element from the reference location in the vertical direction. In another example, where the level of a first element is described herein as being the same or substantially the same as, or "at the level of, a second element, it will be understood that the distance of the first element from a reference location (e.g., the top surface 100a of the substrate 100) in the vertical direction may be the same or substantially the same as the distance of the second element from the reference location in the vertical direction. In some example embodiments, the "height" of an element may refer to the dimension of the element in the vertical direction (e.g., the length between the vertically opposed top and bottom surfaces of the element). The vertical direction as described herein may be a third direction D3 that may be perpendicular to the first direction D1 and the second direction D2. In some example embodiments, a "layer (t ier)" in which an element may be located or a "layer" in which an element may be included may refer to a level in a vertical direction. The vertical direction as described herein may be a third direction D3 that may be perpendicular to the first direction D1 and the second direction D2.

In some example embodiments of the inventive concepts, the first source/drain pattern SD1 may include the same semiconductor element (e.g., si) as that of the substrate 100. The second source/drain pattern SD2 may include a semiconductor element (e.g., siGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. Accordingly, the pair of second source/drain patterns SD2 may provide compressive stress to the second channel pattern CH 2.

Each of the first and second source/drain patterns SD1 and SD2 may have a non-uniform embossed shape at sidewalls thereof. For example, each of the first and second source/drain patterns SD1 and SD2 may have a wavy profile at sidewalls thereof. Sidewalls of each of the first and second source/drain patterns SD1 and SD2 may protrude toward first, second and third internal electrodes PO1, PO2 and PO3 of the gate electrode GE, which will be discussed below. In some example embodiments of the inventive concepts, sidewalls of the second source/drain pattern SD2 may be rougher than sidewalls of the first source/drain pattern SD 1. For example, sidewalls of the second source/drain pattern SD2 may protrude more than sidewalls of the first source/drain pattern SD 1.

The first channel pattern CH1 and the second channel pattern CH2 may have the gate electrode GE disposed thereon. Each of the gate electrodes GE may extend in the first direction D1 while extending across the first and second channel patterns CH1 and CH 2. Each of the gate electrodes GE may vertically overlap the first and second channel patterns CH1 and CH 2. The gate electrodes GE may be arranged at a first pitch in the second direction D2.

The gate electrode GE may include an inner electrode IGE interposed between the nanoplatelets and an outer gate electrode OGE disposed outside the nanoplatelets. For example, the internal electrode IGE may include a first internal electrode PO1 interposed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second internal electrode PO2 interposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third internal electrode PO3 interposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP 3. The outer gate electrode OGE can be disposed on the third semiconductor pattern SP 3.

In some example embodiments, one of the inner electrodes (e.g., the second inner electrode PO 2) of the inner electrode IGE vertically overlapped with the semiconductor pattern of the first channel pattern CH1 may be referred to as a first inner electrode between adjacent semiconductor patterns (e.g., SP1 and SP 2) among the plurality of semiconductor patterns of the first channel pattern CH 1. In some example embodiments, one of the inner electrodes (e.g., the second inner electrode PO 2) of the inner electrode IGE vertically overlapping (e.g., overlapping in the third direction D3) with the semiconductor patterns of the second channel pattern CH2 may be referred to as a second inner electrode between adjacent semiconductor patterns (e.g., SP1 and SP 2) of the plurality of semiconductor patterns of the second channel pattern CH 2. It will be appreciated that the "adjacent" elements as described herein (e.g., the adjacent semiconductor patterns SP1 and SP2 of the first channel pattern CH1 may be interchangeably referred to as "adjacent" elements (e.g., the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the first channel pattern CH1 may be interchangeably referred to as "adjacent" or "neighboring" semiconductor patterns of the plurality of semiconductor patterns of the first channel pattern CH1, and the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the second channel pattern CH2 may be interchangeably referred to as "adjacent" or "neighboring" semiconductor patterns of the plurality of semiconductor patterns of the second channel pattern CH 2).

In some example embodiments, the first semiconductor pattern SP1 of a given channel pattern CH1 and/or CH2 and the active pattern AP1 and/or AP2 vertically overlapping (e.g., overlapping in the third direction D3) may be referred to as "adjacent" and/or "neighboring" semiconductor patterns of the plurality of semiconductor patterns of the given channel pattern CH1 and/or CH2, such that in some example embodiments the first inner electrode PO1 of the first channel pattern CH1 may be referred to as a first inner electrode between neighboring semiconductor patterns of the plurality of semiconductor patterns of the first channel pattern CH1 and the first inner electrode PO1 of the second channel pattern CH2 may be referred to as a second inner electrode between neighboring semiconductor patterns of the plurality of semiconductor patterns of the second channel pattern CH2.

Referring to fig. 5D, the gate electrode GE may be disposed on the top surface TS, the bottom surface BS, and the opposite sidewalls SW of each of the first, second, and third semiconductor patterns SP1, SP2, and SP 3. For example, the transistor according to some example embodiments may be a three-dimensional field effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2.

Referring back to fig. 4 and 5A to 5D, on the first active region AR1, an inner spacer ISP may be interposed between the first source/drain pattern SD1 and the first, second and third inner electrodes PO1, PO2 and PO3, respectively. Each of the first, second, and third internal electrodes PO1, PO2, and PO3 of the gate electrode GE may be spaced apart from the first source/drain pattern SD1 across the internal spacers ISP. The inner spacer ISP may reduce or prevent leakage current from the gate electrode GE.

On the second active region AR2, the inner spacers ISP may be respectively interposed between the second source/drain pattern SD2 and the first, second and third inner electrodes PO1, PO2 and PO3 of the gate electrode GE. In some example embodiments of the inventive concepts, the inner spacer ISP may be omitted from the second active region AR 2.

A pair of gate spacers GS may be disposed on opposite sidewalls of the outer gate electrode OGE, respectively. The gate spacer GS may extend along the gate electrode GE in the first direction D1. The gate spacer GS may have a top surface higher than that of the outer gate electrode OGE. The top surface of the gate spacer GS may be coplanar with the top surface of the first interlayer dielectric layer 110, which will be discussed below. In some example embodiments, the gate spacer GS may include at least one selected from SiCN, siCON, and SiN. In some example embodiments, the gate spacer GS may include a multilayer formed of at least two selected from SiCN, siCON, and SiN.

In some example embodiments of the inventive concepts, referring to fig. 6A, the gate spacer GS may include a first spacer GS1 on a sidewall of the outer gate electrode OGE and a second spacer GS2 on the first spacer GS 1. Each of the first and second spacers GS1 and GS2 may include a silicon-containing dielectric material. For example, the first spacer GS1 may comprise a silicon-containing low-k dielectric material, such as SiCON. The second spacer GS2 may include a silicon-containing dielectric material having excellent etching resistance, for example, siN. The second spacer GS2 may serve as an etch stop layer when the active contact AC is formed as described below. The second spacers GS2 may be used to form the active contacts AC in a self-aligned manner.

Referring again to fig. 4 and 5A to 5D, a gate capping pattern GP may be disposed on the outer gate electrode OGE. The gate capping pattern GP may extend along the gate electrode GE in the first direction D1. The gate capping pattern GP may include a material having an etch selectivity with respect to the first and second interlayer dielectric layers 110 and 120, which will be discussed below. For example, the gate capping pattern GP may include at least one selected from SiON, siCN, siCON and SiN.

The gate dielectric layer GI may be interposed between the gate electrode GE and the first channel pattern CH1 and between the gate electrode GE and the second channel pattern CH 2. The gate dielectric layer GI may cover the top surface TS, the bottom surface BS, and the opposite sidewalls SW of each of the first, second, and third semiconductor patterns SP1, SP2, and SP3 (see fig. 5D). The gate dielectric layer GI may cover a top surface of the device isolation layer ST located under the gate electrode GE.

In some example embodiments of the inventive concepts, the gate dielectric layer GI may include one or more of a silicon oxide layer, a silicon oxynitride layer, and a high-k dielectric layer. For example, the gate dielectric layer GI may have a structure in which a silicon oxide layer and a high-k dielectric layer are stacked. The high-k dielectric layer may comprise a high-k dielectric material having a dielectric constant greater than a dielectric constant of the silicon oxide layer. For example, the high-k dielectric material may include at least one selected from hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

In some example embodiments, a semiconductor device according to the inventive concepts may include a negative capacitance field effect transistor using a negative capacitor. For example, the gate dielectric layer GI may include a ferroelectric material layer exhibiting ferroelectric properties and a paraelectric material layer exhibiting paraelectric properties.

The ferroelectric material layer may have a negative capacitance and the paraelectric material layer may have a positive capacitance. For example, when two or more capacitors are connected in series, and when each capacitor has a positive capacitance, the total capacitance may be reduced to be smaller than the capacitance of each capacitor. Conversely, when at least one of the two or more capacitors connected in series has a negative capacitance, the total capacitance may have a positive value that is increased to be greater than the absolute value of the capacitance of each capacitor.

In the case where the ferroelectric material layer having a negative capacitance and the paraelectric material layer having a positive capacitance are connected in series, the capacitance of the whole of the ferroelectric material layer and the paraelectric material layer connected in series may increase. The increase in total capacitance can be used to enable transistors including ferroelectric material layers to have sub-threshold swings of less than about 60mV/decade at room temperature.

The ferroelectric material layer may have ferroelectric properties. The ferroelectric material layer may include, for example, one or more of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, and lead zirconium titanium oxide. For example, hafnium zirconium oxide may be a material in which hafnium oxide is doped with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr) and oxygen (O).

The ferroelectric material layer may further include impurities doped therein. For example, the impurities may include at least one selected from aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of impurities included in the ferroelectric material layer may vary according to the ferroelectric material included in the ferroelectric material layer.

When the ferroelectric material layer includes hafnium oxide, the ferroelectric material layer may include at least one of impurities such as gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

When the impurity is aluminum (Al), the ferroelectric material layer may include about 3 atomic percent to 8 atomic percent aluminum. In the present specification, the proportion of the impurity may be a proportion of aluminum to the sum of hafnium and aluminum.

When the impurity is silicon (Si), the ferroelectric material layer may include about 2 atomic percent to about 10 atomic percent silicon. When the impurity is yttrium (Y), the ferroelectric material layer may include about 2 atomic percent to about 10 atomic percent yttrium. When the impurity is gadolinium (Gd), the ferroelectric material layer may include gadolinium in an amount of about 1 atomic percent to about 7 atomic percent. When the impurity is zirconium (Zr), the ferroelectric material layer may include about 50 atomic percent to about 80 atomic percent zirconium.

The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one selected from silicon oxide and high-k metal oxide. The metal oxide included in the paraelectric material layer may include, for example, one or more of hafnium oxide, zirconium oxide, and aluminum oxide, but the inventive concept is not limited thereto.

The ferroelectric material layer and the paraelectric material layer may comprise the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not have ferroelectric properties. For example, when the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the hafnium oxide included in the ferroelectric material layer may have a crystal structure different from that of the hafnium oxide included in the paraelectric material layer.

The ferroelectric material layer may have a thickness that includes ferroelectric properties. The thickness of the ferroelectric material layer may be in the range of, for example, about 0.5nm to about 10nm, but the inventive concept is not limited thereto. Since the ferroelectric material has its own critical thickness exhibiting ferroelectric properties, the thickness of the ferroelectric material layer may depend on the ferroelectric material.

For example, the gate dielectric layer GI may comprise a single ferroelectric material layer. For another example, the gate dielectric layer GI may include a plurality of ferroelectric material layers spaced apart from each other. The gate dielectric layer GI may have a stacked structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

Still referring to fig. 4 and 5A to 5D, the gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate dielectric layer GI, and may be adjacent to the first, second, and third semiconductor patterns SP1, SP2, and SP 3. The first metal pattern may include a work function metal that controls a threshold voltage of the transistor. The thickness and composition of the first metal pattern may be adjusted to achieve a desired threshold voltage of the transistor. For example, the first, second and third internal electrodes PO1, PO2 and PO3 of the internal electrode IGE may be formed of a first metal pattern or a work function metal.

The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In addition, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

The second metal pattern may include a metal having a resistance smaller than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the outer gate electrode OGE may include a first metal pattern and a second metal pattern on the first metal pattern.

A first interlayer dielectric layer 110 may be disposed on the substrate 100. The first interlayer dielectric layer 110 may cover the gate spacers GS and the first and second source/drain patterns SD1 and SD2. The first interlayer dielectric layer 110 may have a top surface substantially coplanar with a top surface of the gate capping pattern GP and a top surface of the gate spacer GS. The first interlayer dielectric layer 110 may have a second interlayer dielectric layer 120 disposed thereon to cover the gate capping pattern GP. A third interlayer dielectric layer 130 may be disposed on the second interlayer dielectric layer 120. A fourth interlayer dielectric layer 140 may be disposed on the third interlayer dielectric layer 130. For example, the first to fourth interlayer dielectric layers 110 to 140 may include a silicon oxide layer.

The single-height unit SHC may have a first boundary BD1 and a second boundary BD2 opposite to each other in the second direction D2. The first and second boundaries BD1 and BD2 may extend in the first direction D1. The single-height unit SHC may have a third boundary BD3 and a fourth boundary BD4 opposite to each other in the first direction D1. The third and fourth boundaries BD3 and BD4 may extend in the second direction D2.

The single-height unit SHC may be provided on opposite sides thereof with a pair of separation structures DB opposite to each other in the second direction D2. For example, the pair of separation structures DB may be disposed on the first and second boundaries BD1 and BD2 of the single-height unit SHC, respectively. The separation structure DB may extend in a first direction D1 parallel to the gate electrode GE. The pitch between the separation structure DB and the gate electrode GE adjacent thereto may be the same as the first pitch.

The separation structure DB may penetrate the first and second interlayer dielectric layers 110 and 120 to extend into the first and second active patterns AP1 and AP 2. The separation structure DB may penetrate an upper portion of each of the first and second active patterns AP1 and AP 2. The separation structure DB may electrically separate the active region of the single-height cell SHC from the active region of an adjacent other cell.

The active contacts AC may be disposed to penetrate the first and second interlayer dielectric layers 110 and 120 to be electrically connected with the first and second source/drain patterns SD1 and SD 2. A pair of active contacts AC may be correspondingly disposed on opposite sides of the gate electrode GE. The active contact AC may have a bar shape extending in the first direction D1 when viewed in a plan view.

The active contact AC may be a self-aligned contact. For example, the gate capping pattern GP and the gate spacer GS may be used to form the active contact AC in a self-aligned manner. The active contact AC may cover at least a portion of the sidewall of the gate spacer GS, for example. Although not shown, the active contact AC may cover a portion of the top surface of the gate capping pattern GP.

A metal-semiconductor compound layer SC (such as a silicide layer) may be interposed between the active contact AC and the first source/drain pattern SD1 and between the active contact AC and the second source/drain pattern SD 2. The active contact AC may be electrically connected to one of the first source/drain pattern SD1 and the second source/drain pattern SD2 through the metal-semiconductor compound layer SC. For example, the metal-semiconductor compound layer SC may include at least one selected from titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

The gate contact GC may be disposed to penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP to be electrically connected with the gate electrode GE. The gate contact GC may be correspondingly disposed to overlap the first and second active regions AR1 and AR2 when viewed in a plan view. For example, the gate contact GC may be disposed on the second active pattern AP2 (see fig. 5B).

In some example embodiments of the inventive concepts, referring to fig. 5B, the active contact AC may have an upper portion adjacent to the gate contact GC, and the upper dielectric pattern UIP may fill the upper portion of the active contact AC. The upper dielectric pattern UIP may have a lower bottom surface than that of the gate contact GC. For example, the upper dielectric pattern UIP may cause the active contact AC adjacent to the gate contact GC to have a lower top surface than the bottom surface of the gate contact GC. Accordingly, a short circuit caused by contact between the gate contact GC and its neighboring active contact AC may be reduced or prevented.

Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover sidewalls and bottom surfaces of the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may include at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and a platinum nitride (PtN) layer.

The first metal layer M1 may be disposed in the third interlayer dielectric layer 130. For example, the first metal layer M1 may include a first power line m1_r1, a second power line m1_r2, and a first routing line m1_i. The lines m1_r1, m1_r2, and m1_i of the first metal layer M1 may extend in parallel in the second direction D2.

For example, the first power line m1_r1 and the second power line m1_r2 may be disposed on the third boundary BD3 and the fourth boundary BD4 of the single-height unit SHC, respectively. The first power line m1_r1 may extend along the third boundary BD3 in the second direction D2. The second power line m1_r2 may extend along the fourth boundary BD4 in the second direction D2.

The first wiring m1_i of the first metal layer M1 may be disposed between the first power line m1_r1 and the second power line m1_r2. The first wirings m1_i of the first metal layer M1 may be arranged at a second pitch along the first direction D1. The second pitch may be smaller than the first pitch. Each of the first routing lines m1_i may have a line width smaller than that of each of the first and second power lines m1_r1 and m1_r2.

The first metal layer M1 may further include a first via VI 1. The first via VI 1 may be disposed under the lines m1_r1, m1_r2, m1_i of the first metal layer M1, respectively. The first via VI 1 may electrically connect the active contact AC to one of the lines m1_r1, m1_r2, and m1_i of the first metal layer M1. The first via VI 1 may electrically connect the gate contact GC to one of the lines m1_r1, m1_r2, and m1_i of the first metal layer M1. As shown, at least some of the first routing lines m1_i may be electrically connected (e.g., via separate, respective first vias VI 1) to separate, respective contacts of the active contacts AC or gate contacts GC.

The specific line of the first metal layer M1 and the first via VI 1 thereunder may be formed through a separate process. For example, the specific line of the first metal layer M1 and the first via VI 1 thereunder may each be formed through a single damascene process. According to some example embodiments, sub-20 nm processes may be employed to fabricate semiconductor devices.

The second metal layer M2 may be disposed in the fourth interlayer dielectric layer 140. The second metal layer M2 may include a plurality of second routing lines m2_i. The second wiring lines m2_i of the second metal layer M2 may each have a line shape or a bar shape extending in the first direction D1. For example, the second wiring line m2_i may extend in parallel in the first direction D1.

The second metal layer M2 may further include a second via VI2 correspondingly disposed under the second routing line m2_i. The specific wires of the first metal layer M1 may be electrically connected to corresponding wires of the second metal layer M2 through the second via VI2. For example, the wiring lines of the second metal layer M2 and the second via VI2 thereunder may be simultaneously formed through a dual damascene process.

The first metal layer M1 and the second metal layer M2 may have wiring lines including the same or different conductive materials. For example, the wiring lines of the first metal layer M1 and the second metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt. Although not shown, other metal layers (e.g., M3, M4, M5, etc.) may be additionally stacked on the fourth interlayer dielectric layer 140. Each of the stacked metal layers may include wiring lines for wiring between the cells.

Referring to fig. 6A, the gate electrode GE and the first channel pattern CH1 on the first active pattern AP1 will be described in detail below.

Each of the first, second and third semiconductor patterns SP1, SP2 and SP3 of the first channel pattern CH1 may include channel recesses formed at lower and upper portions thereof. For example, the first semiconductor pattern SP1 may include a first channel recess RS1 on a lower portion thereof and a second channel recess RS2 on an upper portion thereof (e.g., may include one or more surfaces defining the first channel recess RS1 and the second channel recess RS 2). The second semiconductor pattern SP2 may include a third channel recess RS3 on a lower portion thereof and a fourth channel recess RS4 on an upper portion thereof (e.g., may include one or more surfaces defining the third channel recess RS3 and the fourth channel recess RS 4). The third semiconductor pattern SP3 may include a fifth channel recess RS5 on a lower portion thereof and a sixth channel recess RS6 on an upper portion thereof (e.g., may include one or more surfaces defining the fifth channel recess RS5 and the sixth channel recess RS 6). In some example embodiments of the inventive concepts, the first active pattern AP1 may include a body recess BRS on an upper portion thereof (e.g., may include one or more surfaces defining the body recess BRS). In some example embodiments, the above-described recesses may be understood as being defined by one or more surfaces of one or more inner electrodes adjacent to one or more semiconductor patterns described as including such recesses, wherein one or more surfaces of the one or more semiconductor patterns are described as including such recesses.

The channel recesses RS1 to RS6 may be made to impart dumbbell shapes to the first, second and third semiconductor patterns SP1, SP2 and SP3 of the first channel pattern CH 1. The elements ("structures") described herein having a "dumbbell shape" are understood to refer to structures having a concave top surface TOS and bottom surface BTS. For example, the second semiconductor pattern SP2 of the first channel pattern CH1 may include a central portion CTP and side portions EDP located on opposite sides of the central portion CTP. The central portion CTP may also be interposed between the second inner electrode PO2 and the third inner electrode PO 3. The side portion EDP may be interposed between the inner spacer ISP adjacent to the second inner electrode PO2 and the inner spacer ISP adjacent to the third inner electrode PO 3.

The center portion CTP may have a first thickness TK1 and the side portions EDP may have a second thickness TK2 greater than the first thickness TK1. The central portion CTP has such a thickness: is minimum (e.g., minimum value) at the center of the center portion CTP (e.g., horizontal center in the second direction D2), and gradually (e.g., gradually, continuously, etc.) increases in the direction from the center of the center portion CTP toward the side portion EDP (e.g., in the second direction D2). The minimum thickness at the center of the central portion CTP of the second semiconductor pattern SP2 may be referred to as a minimum thickness at the central portion CTP of the second semiconductor pattern SP2, and thus may also be a minimum thickness of the second semiconductor pattern SP2, and may be represented as a first thickness TK1. Accordingly, the first thickness TK1 may be defined to represent a minimum thickness of the central portion CTP, and may also be defined to represent a minimum thickness at the central portion CTP of the second semiconductor pattern SP 2. In some example embodiments of the inventive concepts, the ratio TK1/TK2 of the first thickness TK1 to the second thickness TK2 may be in the range of about 0.2 to about 0.8.

As described herein, the thickness of the structure may refer to the thickness of the structure in the third direction D3. The thickness at "the center portion of the given semiconductor pattern may refer to the thickness of the given semiconductor pattern in the third direction D3 at the center portion of the given semiconductor pattern, which may also refer to the thickness in the third direction D3 at the center in the second direction D2 of the center portion of the given semiconductor pattern. As shown in fig. 6A, the thickness at the center portion CTP of the semiconductor pattern (e.g., the first thickness TK 1) may be the minimum thickness of the center portion CTP, and thus the minimum thickness of the semiconductor pattern. As described herein, the thickness at which a portion of a structure "resides" may be interchangeably referred to as the "thickness" of that portion of the structure.

The first to sixth trench recesses RS1 to RS6 may have first to sixth recess depths DE1 to DE6, respectively. According to some example embodiments of the inventive concepts, the first to sixth recess depths DE1 to DE6 may be the same or different from each other (e.g., the same or different in size in the third direction D3). In the present specification, each of the recess depths DE1 to DE6 may be defined to represent a vertical (e.g., in the third direction D3) length from the side portion EDP to the center of the center portion CTP. Each of the recess depths DE1 to DE6 may be approximately (TK 2-TK 1)/2 or half of the difference between the first thickness TK1 and the second thickness TK 2.

The recess depths of the body recess BRS and the channel recesses RS1 to RS6 may be the same or different. For example, the body recess BRS may have a recess depth BDE that is substantially the same as the first recess depth DE1 of the first channel recess RS 1.

The first, second and third internal electrodes PO1, PO2 and PO3 on the first active pattern AP1 may each have an eye shape. For example, the first internal electrode PO1 may protrude at each of the bottom surface BTS and the top surface TOS thereof. The elements ("structures") described herein having an "eye shape" may be understood to refer to structures having a convex top surface TOS and bottom surface BTS. The first inner electrode PO1 may be flat at its side surface SIS. As described herein, the surfaces of the structure (e.g., the bottom surface BTS and the top surface TOS of the first inner electrode PO 1) may be understood as "convex", wherein the surfaces have a curvature such that the parallel/horizontal direction (e.g., in the second direction D2) central portion (also referred to herein as a horizontal central portion, a central portion, etc.) of the surfaces is the most distal protrusion of the surfaces and/or the structure in the vertical/vertical direction (e.g., in the third direction D3).

The first, second and third internal electrodes PO1, PO2 and PO3 on the first active pattern AP1 may have a size (or volume) gradually decreasing in a direction from the lower layer to the upper layer. In the inventive concept, the lower layer may be a level near the level of the top surface 100a of the substrate 100. The upper layer may be a level away from the level of the top surface 100a of the substrate 100. Elements described herein as being in the "same layer" may be at the same level in the third direction D3 relative to a reference location (e.g., the top surface of the substrate 100) and/or may at least partially overlap in the horizontal direction (e.g., the second direction D2). For example, the first active pattern AP1 and the corresponding first internal electrode PO1 on the second active pattern AP2, which are at least partially overlapped in the second direction D2, may be understood to be in the same layer.

The maximum width WI2 of the second internal electrode PO2 may be smaller than the maximum width WI 1 of the first internal electrode PO 1. The maximum width WI3 of the third internal electrode PO3 may be smaller than the maximum width WI2 of the second internal electrode PO 2. The maximum width WI3 of the third inner electrode PO3 may be greater than the maximum width WI4 of the outer gate electrode OGE. As described herein, the width of a structure may refer to the width of the structure in a horizontal direction (e.g., the second direction D2 and/or the first direction D1).

Each of the first, second and third internal electrodes PO1, PO2 and PO3 may have a maximum thickness TK3 in the third direction D3. The maximum thicknesses TK3 of the first, second and third internal electrodes PO1, PO2 and PO3 are the same or different from each other.

The first source/drain pattern SD1 may include first, second and third protruding portions PRP1, PRP2 and PRP3 protruding toward the first, second and third internal electrodes PO1, PO2 and PO3 of the gate electrode GE, respectively. The protruding lengths of the first protruding portion PRP1, the second protruding portion PRP2, and the third protruding portion PRP3 may gradually decrease in a direction from the lower layer to the upper layer. For example, the second protrusion length PRL2 of the second protrusion portion PRP2 may be smaller than the first protrusion length PRL1 of the first protrusion portion PRP 1. The third protrusion length PRL3 of the third protrusion portion PRP3 may be smaller than the second protrusion length PRL2 of the second protrusion portion PRP 2.

Each of the first, second and third semiconductor patterns SP1, SP2 and SP3 may each include a channel recess at an upper portion thereof and a channel recess at a lower portion thereof, which may result in an increase in an Effective Channel Length (ECL) according to some example embodiments of the inventive concept. Accordingly, the inventive concept may reduce or prevent leakage current and short channel effects, such as Drain Induced Barrier Lowering (DIBL). In the inventive concept, hot carrier effects may be reduced or prevented to increase reliability of the device.

Since the body recess BRS according to the inventive concept is formed at the upper portion of the first active pattern AP1, a three-dimensional structure may be imparted to a channel formed at the upper portion of the first active pattern AP 1. For example, an Effective Channel Length (ECL) of an upper portion of the first active pattern AP1 may be increased and a short channel effect may be reduced. In addition, leakage current occurring at the upper portion of the first active pattern AP1 may be reduced or prevented.

Referring to fig. 6B, the gate electrode GE and the second channel pattern CH2 on the second active pattern AP2 will be described in detail below.

Unlike the first channel pattern CH1, each of the first, second, and third semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2 may not include a channel recess. Unlike the first active pattern AP1, the second active pattern AP2 may not include a body recess at an upper portion thereof.

Since the second channel pattern CH2 does not include a channel recess, the first, second, and third semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2 may each have a rod shape. For example, the second semiconductor pattern SP2 of the second channel pattern CH2 may include a central portion CTP and side portions EDP located on opposite sides of the central portion CTP. The central portion CTP may be interposed between the second inner electrode PO2 and the third inner electrode PO 3. The side portion EDP may be interposed between the inner spacer ISP adjacent to the second inner electrode PO2 and the inner spacer ISP adjacent to the third inner electrode PO 3. The center portion CTP may have a fourth thickness TK4 and the side portions EDP may have a fifth thickness TK5 substantially the same as the fourth thickness TK 4. In some example embodiments of the inventive concepts, the ratio TK4/TK5 of the fourth thickness TK4 to the fifth thickness TK5 may be in the range of about 0.8 to about 1.0.

In some example embodiments, a thickness (e.g., second thickness TK 2) at the side portion EDP of the second semiconductor pattern SP2 of the first channel pattern CH1 may be the same as or substantially the same as a thickness (e.g., fifth thickness TK 5) at the side portion EDP of the second semiconductor pattern SP2 of the second channel pattern CH 2. To reiterate, in some example embodiments, the second thickness TK2 may be the same or substantially the same (e.g., the same or substantially the same in size) as the fifth thickness TK5.

In some example embodiments, a thickness (e.g., a first thickness TK 1), which may be a minimum thickness of the central portion CTP, at the central portion CTP of the second semiconductor pattern SP2 of the first channel pattern CH1 may be less than (e.g., less than) a thickness (e.g., a minimum thickness) thereof at the central portion CTP of the second semiconductor pattern SP2 of the second channel pattern CH2 (e.g., a fourth thickness TK 4). To reiterate, in some example embodiments, the first thickness TK1 may be less (e.g., smaller in size) than the fourth thickness TK4. As shown in fig. 6A and 6B, the minimum thickness of the center portion CPT of the second semiconductor pattern SP2 of the first channel pattern CH1 may be different (e.g., smaller) than the minimum thickness of the center portion CPT of the second semiconductor pattern SP2 of the second channel pattern CH 2.

The first, second and third internal electrodes PO1, PO2 and PO3 on the second active pattern AP2 may each have a rectangular shape. For example, the first inner electrode PO1 on the second active pattern AP2 may be flat (e.g., planar) or convex at each of the bottom surface BTS and the top surface TOS thereof. Referring again to fig. 6A, the bottom surface BTS and the top surface TOS of the first inner electrode PO1 on the first active pattern AP1 may be more protruded than the bottom surface BTS and the top surface TOS of the first inner electrode PO1 on the second active pattern AP2, respectively. The first internal electrode PO1 on the second active pattern AP2 may be flat on the side surface SIS thereof. In some example embodiments, the first inner electrode PO1 may be inclined at a side surface SIS thereof.

As described herein, the first surface may be more convex than the second surface, wherein the first surface has a convex curvature (e.g., a maximum convex curvature, such as at a horizontal center portion (which is also referred to herein interchangeably as a center portion), at a maximum vertical protrusion portion, etc.) that is greater than a convex curvature (e.g., a maximum convex curvature, such as at a horizontal center portion (which is also referred to herein interchangeably as a center portion), at a maximum vertical protrusion portion, etc.) of the second surface. Similarly, the first surface may be less convex than the second surface, wherein the first surface has a smaller convex curvature (e.g., a smaller maximum convex curvature, such as at a horizontal center portion (which is also referred to herein interchangeably as a center portion), at a maximum vertical protrusion portion, etc.) than a convex curvature of the second surface (e.g., a maximum convex curvature, such as at a horizontal center portion (which is also referred to herein interchangeably as a center portion), at a maximum vertical protrusion portion, etc.).

It will be appreciated that the magnitude of the curvature of the surface may correspond inversely to the radius of curvature of the surface. For example, the first surface may be more convex than the second surface based on the first surface having a radius of curvature (e.g., a minimum radius of curvature corresponding to a maximum convex curvature) that is less than a radius of curvature of the second surface (e.g., a minimum radius of curvature corresponding to a maximum convex curvature of the first surface).

Referring back to fig. 6A and 6B, based on the top surface TOS of the first internal electrode PO1 on the first active pattern AP1 having a greater curvature, a greater maximum curvature, a smaller minimum radius of curvature, etc. than the top surface TOS of the first internal electrode PO1 on the second active pattern AP2, the top surface TOS of the first internal electrode PO1 on the first active pattern AP1 may be more convex than the top surface TOS of the first internal electrode PO1 on the second active pattern AP 2. Similarly, still referring to fig. 6A and 6B, based on the bottom surface BTS of the first inner electrode PO1 on the first active pattern AP1 having a larger curvature, a larger maximum curvature, a smaller minimum radius of curvature, etc. than the bottom surface BTS of the first inner electrode PO1 on the second active pattern AP2, the bottom surface BTS of the first inner electrode PO1 on the first active pattern AP1 may be more convex than the bottom surface BTS of the first inner electrode PO1 on the second active pattern AP 2.

The sizes (or volumes) of the first, second, and third internal electrodes PO1, PO2, and PO3 on the second active pattern AP2 may gradually decrease in a direction from a lower layer (e.g., an internal electrode closer to the substrate 100 in the third direction D3) toward an upper layer (e.g., an internal electrode farther from the substrate 100 in the third direction D3). The maximum width WI6 of the second inner electrode PO2 may be less (e.g., smaller) than the maximum width WI5 of the first inner electrode PO 1. The maximum width WI7 of the third internal electrode PO3 may be smaller than the maximum width WI6 of the second internal electrode PO 2. The maximum width WI7 of the third inner electrode PO3 may be greater than the maximum width WI8 of the outer gate electrode OGE.

The dimensions (or volumes) of the first, second and third internal electrodes PO1, PO2 and PO3 on the second active pattern AP2 may be smaller than those of the first, second and third internal electrodes PO1, PO2 and PO3 on the first active pattern AP1, respectively. For example, the maximum width WI6 of the second internal electrode PO2 on the second active pattern AP2 may be smaller than the maximum width WI2 of the second internal electrode PO2 on the first active pattern AP 1. The maximum thickness TK6 of the second inner electrode PO2 on the second active pattern AP2 may be smaller than the maximum thickness TK3 of the second inner electrode PO2 on the first active pattern AP 1.

The second source/drain pattern SD2 may include first, second and third protruding portions PRP1, PRP2 and PRP3 protruding toward the first, second and third internal electrodes PO1, PO2 and PO3 of the gate electrode GE, respectively. The first, second and third protruding portions PRP1, PRP2 and PRP3 may have the same protruding length as each other or different protruding lengths from each other.

It may be desirable for the channel thickness of the NMOSFET to be less than the channel thickness of the PMOSFET in order to impart improved or optimal performance to the logic transistor of the single-height cell SHC depicted in fig. 4. The inventive concept can selectively adjust an NMOSFET to have a small channel thickness while allowing the PMOSFET to maintain its relatively large channel thickness. Accordingly, the electrical properties of the NMOSFET may be improved without degrading the performance of the PMOSFET, thereby improving the performance of devices (e.g., semiconductor devices) including the NMOSFET and the PMOSFET.

An NMOSFET is used as an example for the three-dimensional transistor discussed with reference to fig. 6A and a PMOSFET is used as an example for the three-dimensional transistor discussed with reference to fig. 6B, but the inventive concept is not so limited. In some example embodiments, the description of the three-dimensional transistor of fig. 6A may be applicable to PMOSFETs. In some example embodiments, the description of the three-dimensional transistor of fig. 6B may be applicable to an NMOSFET.

Fig. 7A, 7B, 8A, 8B, 9A, 9B, 9C, 10A, 10B, 10C, 11A, 11B, 11C, 12A, 12B, and 12C illustrate cross-sectional views showing a method of manufacturing a semiconductor device according to some example embodiments of the inventive concepts. In detail, fig. 7A, 8A, 9A, 10A, 11A and 12A are sectional views taken along the line A-A' of fig. 4. Fig. 9B, 10B, 11B and 12B are sectional views taken along line B-B' of fig. 4. Fig. 9C and 10C show cross-sectional views taken along line C-C' of fig. 4. Fig. 7B, 8B, 11C and 12C are sectional views taken along line D-D' of fig. 4.

Referring to fig. 7A and 7B, a substrate 100 including a first active region AR1 and a second active region AR2 may be provided. The active layer ACL and the sacrificial layer SAL may be alternately stacked on the substrate 100. The active layer ACL may include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and the sacrificial layer SAL may include the other of silicon (Si), germanium (Ge), and silicon germanium (SiGe).

The sacrificial layer SAL may include a material having etching selectivity with respect to the active layer ACL. For example, the sacrificial layer SAL may include silicon germanium (SiGe), and the active layer ACL may include silicon (Si). Each of the sacrificial layers SAL may have a germanium concentration of about 10at% (atomic%) to about 30 at%.

A mask pattern may be formed on each of the first active region AR1 and the second active region AR2 of the substrate 100. The mask pattern may have a line shape or a bar shape extending in the second direction D2.

A patterning process may be performed in which the mask pattern is used as an etching mask to form trenches TR defining the first and second active patterns AP1 and AP2. The first active pattern AP1 may be formed on the first active region AR 1. A second active pattern AP2 may be formed on the second active region AR 2.

A stack pattern STP may be formed on each of the first active pattern AP1 and the second active pattern AP2. The stack pattern STP may include active layers ACL and sacrificial layers SAL that are alternately stacked. During the patterning process, the stack pattern STP may be formed together with the first active pattern AP1 and the second active pattern AP2.

The device isolation layer ST may be formed to fill the trench TR. For example, a dielectric layer may be formed on the entire surface of the substrate 100 to cover the stack pattern STP and the first and second active patterns AP1 and AP2. The dielectric layer may be recessed until the stack pattern STP is exposed, and thus the device isolation layer ST may be formed.

The device isolation layer ST may include a dielectric material such as a silicon oxide layer. The stack pattern STP may be exposed from the device isolation layer ST. For example, the stack pattern STP may vertically protrude upward from the device isolation layer ST.

Referring to fig. 8A and 8B, a sacrificial pattern PP may be formed on the substrate 100 to extend across the stack pattern STP. Each of the sacrificial patterns PP may be formed to have a line shape or a bar shape extending in the first direction D1. The sacrificial patterns PP may be arranged at a first pitch in the second direction D2.

For example, the forming of the sacrificial pattern PP may include: forming a sacrificial layer on the entire surface of the substrate 100; forming a hard mask pattern MP on the sacrificial layer; and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer may comprise polysilicon.

A pair of gate spacers GS may be formed on opposite sidewalls of each of the sacrificial patterns PP. The forming of the gate spacer GS may include conformally forming a gate spacer layer on the entire surface of the substrate 100 and anisotropically etching the gate spacer layer. In some example embodiments of the inventive concepts, the gate spacer GS may be a multi-layer including at least two layers.

Referring to fig. 9A to 9C, a first recess RCS1 may be formed in the stack pattern STP on the first active pattern AP 1. The second recess RCS2 may be formed in the stack pattern STP on the second active pattern AP 2. During the formation of the first and second recesses RCS1 and RCS2, the device isolation layer ST may be further recessed on opposite sides of each of the first and second active patterns AP1 and AP2 (see fig. 9C).

For example, the hard mask pattern MP and the gate spacer GS may be used as an etching mask to etch the stack pattern STP on the first active pattern AP1, and thus the first recess RCS1 may be formed. The first recess RCS1 may be formed between a pair of sacrificial patterns PP. The width of the first recess RCS1 in the second direction D2 may decrease as the distance from the substrate 100 decreases.

The active layer ACL may be formed to sequentially stack the first to third semiconductor patterns SP1, SP2 and SP3 between adjacent first recesses RCS1. The first channel pattern CH1 may be composed of a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 between adjacent first recesses RCS1.

The first recess RCS1 may expose the sacrificial layer SAL. A selective etching process may be performed on the exposed sacrificial layer SAL. The etching process may include a wet etching process that selectively etches silicon germanium. In the etching process, each of the sacrificial layers SAL may be recessed to form the recessed region IDR. The recessed region IDR may enable the sacrificial layer SAL to have a recessed sidewall.

Still referring to fig. 9A to 9C, the second recesses RCS2 in the stack pattern STP on the second active pattern AP2 may be formed by a method similar to that for forming the first recesses RCS1. A selective etching process may be performed on the sacrificial layer SAL exposed by the second recess RCS2, thereby forming a recess region IDR in the second recess RCS2. The recessed region IDR may provide the second recess RCS2 with a corrugated inner sidewall. The second channel pattern CH2 may be composed of a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 between adjacent second recesses RCS2.

Referring to fig. 10A to 10C, a first source/drain pattern SD1 may be formed in the first recess RCS1 accordingly. For example, a first Selective Epitaxial Growth (SEG) process may be performed such that the inner sidewalls of the first recess RCS1 serve as a seed layer to form an epitaxial layer filling the first recess RCS 1. The epitaxial layer may be grown from the first, second and third semiconductor patterns SP1, SP2 and SP3 exposed by the first recess RCS1 as seeds, the sacrificial layer SAL and the first active pattern AP1 (or the upper portion of the substrate 100). For example, the first SEG process may comprise Chemical Vapor Deposition (CVD) or Molecular Beam Epitaxy (MBE).

In some example embodiments of the inventive concepts, the first source/drain pattern SD1 may include the same semiconductor element (e.g., si) as that of the substrate 100. In forming the first source/drain pattern SD1, an impurity (e.g., phosphorus, arsenic, or antimony) may be implanted in situ to enable the first source/drain pattern SD1 to have an n-type. In some example embodiments, after the first source/drain pattern SD1 is formed, impurities may be implanted into the first source/drain pattern SD1.

The second source/drain pattern SD2 may be formed in the second recess RCS2 accordingly. For example, the second SEG process may be performed such that the inner sidewall of the second recess RCS2 serves as a seed layer to form the second source/drain pattern SD2. The second source/drain pattern SD2 may be grown from a seed, or from the first, second and third semiconductor patterns SP1, SP2 and SP3 exposed by the second recess RCS2, the sacrificial layer SAL, and the second active pattern AP2 (or the upper portion of the substrate 100).

In some example embodiments of the inventive concepts, the second source/drain pattern SD2 may include a semiconductor element (e.g., siGe) having a lattice constant greater than that of the semiconductor element of the substrate 100. In forming the second source/drain pattern SD2, an impurity (e.g., boron, gallium, or indium) may be in-situ implanted to enable the second source/drain pattern SD2 to have a p-type. In some example embodiments, after the second source/drain pattern SD2 is formed, impurities may be implanted into the second source/drain pattern SD2.

Referring to fig. 11A to 11C, a first interlayer dielectric layer 110 may be formed to cover the first and second source/drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS. For example, the first interlayer dielectric layer 110 may include a silicon oxide layer.

The first interlayer dielectric layer 110 may be planarized until the top surface of the sacrificial pattern PP is exposed. The first interlayer dielectric layer 110 may be planarized using an etch back or Chemical Mechanical Polishing (CMP) process. The hard mask pattern MP may be entirely removed during the planarization process. As a result, the first interlayer dielectric layer 110 may have a top surface coplanar with the top surfaces of the sacrificial pattern PP and the gate spacer GS.

The exposed sacrificial pattern PP may be selectively removed. The removal of the sacrificial pattern PP may form an external region ORG exposing the first and second channel patterns CH1 and CH2 (see fig. 11C). The removal of the sacrificial pattern PP may include performing a wet etching process using an etchant that selectively etches polysilicon.

The sacrificial layer SAL exposed through the outer region ORG may be selectively removed to form the inner region IRG (see fig. 11C). For example, an etching process of selectively etching the sacrificial layer SAL may be performed such that only the sacrificial layer SAL is removed, leaving the first, second, and third semiconductor patterns SP1, SP2, and SP3. For silicon germanium having a relatively high germanium concentration, the etching process may have a high etch rate. For example, the etching process may have a high etch rate for silicon germanium having a germanium concentration greater than about 10 at%.

The etching process may remove the sacrificial layer SAL on the first active region AR1 and the second active region AR 2. The etching process may be a wet etching process. The etching material used for the etching process can rapidly etch the sacrificial layer SAL having a relatively high germanium concentration.

Referring back to fig. 11C, when the sacrificial layer SAL is selectively removed, only the first, second, and third semiconductor patterns SP1, SP2, and SP3 may remain on each of the first and second active patterns AP1 and AP 2. The removal of the sacrificial layer SAL may form a first internal region IRG1, a second internal region IRG2, and a third internal region IRG3.

For example, a first internal region IRG1 may be formed between the active pattern AP1 or AP2 and the first semiconductor pattern SP1, a second internal region IRG2 may be formed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third internal region IRG3 may be formed between the second semiconductor pattern SP2 and the third semiconductor pattern SP 3.

Referring back to fig. 11A and 11C, according to some example embodiments of the inventive concepts, there may be further vertical extensions of the first, second, and third internal regions IRG1, IRG2, and IRG3 on the first active pattern AP 1. Accordingly, each of the first, second, and third internal regions IRG1, IRG2, and IRG3 on the first active pattern AP1 may be given an eye shape (see fig. 11A). The expansion of the internal region IRG on the first active pattern AP1 may include recessing the first, second, and third semiconductor patterns SP1, SP2, and SP3 exposed by the internal region IRG. Referring to fig. 13A to 16B, a method of selectively expanding the internal region IRG on the first active pattern AP1 will be described in detail.

Fig. 13A, 14A, 15A and 16A illustrate enlarged views showing a method of forming the portion M depicted in fig. 11A according to some example embodiments of the inventive concepts. Fig. 13B, 14B, 15B, and 16B illustrate enlarged views showing a method of forming the portion N depicted in fig. 11B according to some example embodiments of the inventive concepts.

Referring to fig. 13A and 13B, the sacrificial pattern PP may be selectively removed to form an external region ORG. The external region ORG may expose the sacrificial layer SAL between the first source/drain patterns SD 1. The external region ORG may expose the sacrificial layer SAL between the second source/drain patterns SD 2. The sacrificial layer SAL exposed by the outer region ORG may be selectively removed. Thus, there may be a first, second and third internal regions IRG1, IRG2 and IRG3 stacked in order. Each of the first, second, and third internal regions IRG1, IRG2, and IRG3 may be an empty space. The first, second, and third internal regions IRG1, IRG2, and IRG3 may expose the first, second, and third semiconductor patterns SP1, SP2, and SP3.

The width of the internal region on the first active pattern AP1 in the second direction D2 may be greater than the width of the internal region IRG on the second active pattern AP2 in the second direction D2. For example, the third internal region IRG3 on the first active pattern AP1 may have a ninth width WI9, and the third internal region IRG3 on the second active pattern AP2 may have a tenth width WI 10 smaller than the ninth width WI 9. This is possible because the interval between the adjacent second source/drain structures SD2 is smaller than the interval between the adjacent first source/drain structures SD 1.

Referring to fig. 14A and 14B, a spacer layer SPL may be conformally formed in the first, second, and third internal regions IRG1, IRG2, and IRG 3. A spacer layer SPL may also be formed on the outer region ORG. The spacer layer SPL may be formed by using a deposition process such as Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). The spacer layer SPL may include at least one selected from a silicon nitride layer and a silicon oxynitride layer. The spacer layer SPL may be formed to have a thickness that does not completely fill the internal region IRG.

The size of the internal region IRG surrounded by the spacer layer SPL on the first active pattern AP1 may be greater than the size of the internal region IRG surrounded by the spacer layer SPL on the second active pattern AP 2. For example, the inner region IRG surrounded by the spacer layer SPL on the first active pattern AP1 may be given an eleventh width WI 11, and the inner region IRG surrounded by the spacer layer SPL on the second active pattern AP2 may be given a twelfth width WI 12 smaller than the eleventh width WI 11.

Referring to fig. 15A and 15B, a dry etching process may be performed on the spacer layer SPL. A dry etching process may be performed such that the spacer layer SPL is etched in a vertical direction parallel to the third direction D3. The dry etching process may cause the spacer layer SPL to have a reduced thickness in the third direction D3. However, the dry etching process does not cause a significant variation in the thickness of the spacer layer SPL in the second direction D2.

The etch rate ETR1 of the spacer layer SPL on the first active pattern AP1 in the vertical direction may be greater than the etch rate ETR2 of the spacer layer SPL on the second active pattern AP2 in the vertical direction. This is possible because the size of the internal region IRG surrounded by the spacer layer SPL on the first active pattern AP1 is larger than the size of the internal region IRG surrounded by the spacer layer SPL on the second active pattern AP2 (WI 11 > WI 12). Accordingly, the etching gas may be more easily introduced into the internal region IRG on the first active pattern AP1 than the internal region IRG on the second active pattern AP 2.

The difference between the etch rate ETR1 on the first active pattern AP1 and the etch rate ETR2 on the second active pattern AP2 may result in a thickness TK7 of the spacer layer SPL on the first active pattern AP1 in the vertical direction being smaller than a thickness TK8 of the spacer layer SPL on the second active pattern AP2 in the vertical direction.

Referring to fig. 16A and 16B, a wet etching process may be performed on the spacer layer SPL. The wet etching process may isotropically etch the spacer layer SPL. A wet etching process may be performed until the spacer layer SPL on the second channel pattern CH2 is removed.

As described above, since the thickness of the spacer layer SPL on the second channel pattern CH2 (see TK8 of fig. 15B) is greater than the thickness of the spacer layer SPL on the first channel pattern CH1 (see TK7 of fig. 15A), when the wet etching process is performed until the semiconductor patterns SP1 to SP3 of the second channel pattern CH2 are exposed, overetching may occur in the semiconductor patterns SP1 to SP3 of the first channel pattern CH 1.

For example, when the wet etching process completely removes the spacer layer SPL on the semiconductor patterns SP1 to SP3 of the first channel pattern CH1, the semiconductor patterns SP1 to SP3 of the first channel pattern CH1 may be oxidized. The oxides of the semiconductor patterns SP1 to SP3 may be removed. Accordingly, the first to sixth channel recesses RS1 to RS6 may be formed on the first to third semiconductor patterns SP1 to SP3 of the first channel pattern CH 1. An upper portion of the first active pattern AP1 exposed through the wet etching process may be oxidized and removed to form a body recess BRS.

When the semiconductor patterns SP1 to SP3 of the second channel pattern CH2 are exposed, the wet etching process may be terminated, and a channel recess may not be formed on the semiconductor patterns SP1 to SP3 of the second channel pattern CH 2. In some example embodiments, the second channel pattern CH2 may be provided thereon with a channel recess formed to have a recess depth smaller than the recess depths of the channel recesses RS1 to RS6 of the first channel pattern CH 1.

The dry etching process in fig. 15A and 15B described above may enable the spacer layer SPL to have a horizontal thickness that remains almost unchanged. Thus, even after the wet etching process, a portion of the spacer layer SPL may remain to form the inner spacer ISP. The inner spacer ISP may cover a surface of one of the source/drain patterns SD1 and SD2, and may also cover a side portion EDP of one of the semiconductor patterns SP1 to SP 3.

The channel recesses RS1 to RS6 may be made to impart dumbbell shapes to the first, second and third semiconductor patterns SP1, SP2 and SP3 of the first channel pattern CH 1. For example, the second semiconductor pattern SP2 of the first channel pattern CH1 may include a central portion CTP and side portions EDP located on opposite sides of the central portion CTP. The center portion CTP of the given semiconductor pattern may be interchangeably referred to as a horizontal center portion (e.g., a center portion in the second direction D2) of the given semiconductor pattern, and the side portions EDP of the given semiconductor pattern may be interchangeably referred to as horizontal edge portions (e.g., edge portions in the second direction D2) of the given semiconductor pattern such that the center portion CTP of the given semiconductor pattern is located between the side portions EDP of the given semiconductor pattern. In the wet etching process, the central portion CTP may be recessed to have a first thickness TK1. The side portions EDP may be protected by the inner spacers ISP and thus may remain with a second thickness TK2 that is greater than the first thickness TK1. In some example embodiments of the inventive concepts, the ratio TK1/TK2 of the first thickness TK1 to the second thickness TK2 may be in the range of about 0.2 to about 0.8.

The spacer layer SPL may protect the first, second, and third semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2 during the wet etching process. Accordingly, each of the first, second, and third semiconductor patterns SP1, SP2, and SP3 of the second channel pattern CH2 may remain bar-shaped. For example, the center portion CTP of the second semiconductor pattern SP2 of the second channel pattern CH2 may be given the fourth thickness TK4. The side portion EDP of the second semiconductor pattern SP2 of the second channel pattern CH2 may have a fifth thickness TK5 substantially the same as the fourth thickness TK4. In some example embodiments of the inventive concepts, the ratio TK4/TK5 of the fourth thickness TK4 to the fifth thickness TK5 may be in the range of about 0.8 to about 1.0.

According to some example embodiments of the inventive concepts, the formation of the spacer layer SPL, the dry etching process of the spacer layer SPL, and the wet etching process of the spacer layer SPL discussed above with reference to fig. 14A through 16B may be repeatedly performed. The formation of the spacer layer SPL, the dry etching process of the spacer layer SPL, and the wet etching process of the spacer layer SPL may constitute one cycle, and each time the cycle is performed, the channel recesses RS1 to RS6 may become deeper, and the inner spacers ISP may become thicker.

Referring again to fig. 11C, as described above with reference to fig. 16A and 16B, the semiconductor patterns SP1 to SP3 of the first channel pattern CH1 may have a thickness that becomes reduced during the wet etching process of the spacer layer SPL. However, the thicknesses of the semiconductor patterns SP1 to SP3 of the second channel pattern CH2 may not substantially change during the wet etching process of the spacer layer SPL. For example, the semiconductor patterns SP1 to SP3 of the first channel pattern CH1 may have a first thickness TK1, and the semiconductor patterns SP1 to SP3 of the second channel pattern CH2 may have a fourth thickness TK4 greater than the first thickness TK 1. The width CW1 of the semiconductor patterns SP1 to SP3 of the first channel pattern CH1 in the first direction D1 may be substantially the same as the width CW2 of the semiconductor patterns SP1 to SP3 of the second channel pattern CH2 in the first direction D1.

Referring to fig. 12A to 12C, a gate dielectric layer GI may be formed on the exposed first, second, and third semiconductor patterns SP1, SP2, and SP 3. The gate dielectric layer GI may be formed to surround each of the first, second, and third semiconductor patterns SP1, SP2, and SP 3. A gate dielectric layer GI may be formed in each of the first internal region IRG1, the second internal region IRG2, and the IRG 3. The gate dielectric layer GI may be formed in the external region ORG. The forming of the gate dielectric layer GI may include sequentially forming a silicon oxide layer and a high-k dielectric layer.

The gate electrode GE may be formed on the gate dielectric layer GI. The gate electrode GE may include first, second, and third internal electrodes PO1, PO2, and PO3 formed in the first, second, and third internal regions IRG1, IRG2, and IRG3, respectively, and may further include an outer gate electrode OGE formed in the outer region ORG.

On the first active pattern AP1, the body recess BRS and the channel recesses RS1 to RS6 may form the internal electrode IGE adjacent to the channel to have a three-dimensional gate structure. Accordingly, the gate electrode GE according to the inventive concept may increase an Effective Channel Length (ECL) and reduce or prevent problems caused by short channel effects.

The gate electrode GE may be recessed to have a top surface lower than the top surface of the gate spacer GS. The gate capping pattern GP may be formed on the recessed gate electrode GE. The gate capping pattern GP may have a top surface coplanar with a top surface of the gate spacer GS.

Referring back to fig. 5A through 5D, a second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 120 may include a silicon oxide layer. The active contact AC may be formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110 to be electrically connected with the first source/drain pattern SD1 and the second source/drain pattern SD 2. The gate contact GC may be formed to penetrate the second interlayer dielectric layer 120 and the gate capping pattern GP to be electrically connected with the gate electrode GE.

The forming of each of the active contact AC and the gate contact GC may include forming a barrier pattern BM and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be conformally formed to include a metal layer and a metal nitride layer. The conductive pattern FM may include a metal having low resistance.

The separation structure DB may be formed on the first and second boundaries BD1 and BD2 of the single-height unit SHC, respectively. The separation structure DB may extend from the second interlayer dielectric layer 120 through the gate electrode GE into the active pattern AP1 or AP2. The separation structure DB may include a dielectric material such as a silicon oxide layer or a silicon nitride layer.

A third interlayer dielectric layer 130 may be formed on the active contact AC and the gate contact GC. The first metal layer M1 may be formed in the third interlayer dielectric layer 130. A fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130. The second metal layer M2 may be formed in the fourth interlayer dielectric layer 140.

In the following embodiments, detailed descriptions of technical features repeated from those discussed with reference to fig. 1 to 6B will be omitted, and differences thereof will be discussed in detail.

Fig. 17 illustrates a cross-sectional view taken along line D-D' of fig. 4, showing a semiconductor device according to some example embodiments of the inventive concepts. Fig. 18 illustrates a plan view taken along line P-P' of fig. 17 according to some example embodiments of the inventive concepts.

Referring to fig. 17, a width CW1 of the first channel pattern CH1 in the first direction D1 may be smaller than a width CW2 of the second channel pattern CH2 in the first direction D1. The thickness TK1 of the nanoplatelets of the first channel pattern CH1 may be smaller than the thickness TK4 of the nanoplatelets of the second channel pattern CH 2.

The first active pattern AP1 may have a discontinuously varying width at an upper portion thereof. Accordingly, an upper portion of the first active pattern AP1 may include a first step structure STE1. The device isolation layer ST between the first active pattern AP1 and the second active pattern AP2 may have a top surface whose height (or level) discontinuously varies. Accordingly, the second step structure STE2 may be included at a top surface of the device isolation layer ST between the first active pattern AP1 and the second active pattern AP 2. For example, as at least shown in fig. 17, a top surface (e.g., a top surface 100a and/or a bottom surface 100b closer to the substrate 100 in the third direction D3) of the device isolation layer ST under the gate electrode GE includes a step structure (e.g., a first step structure STE1 and/or a second step structure), wherein a level of the top surface of the device isolation layer ST in a vertical direction (e.g., the third direction D3) discontinuously changes in a horizontal direction (e.g., the first direction D1).

Fig. 18 depicts a planar shape of the second semiconductor pattern SP2 as a nano-sheet of the first channel pattern CH1 by way of a representative example. The second semiconductor pattern SP2 may include a seventh channel recess RS7 at each of opposite sides thereof. The gate dielectric layer GI and the outer gate electrode OGE can be disposed in the seventh channel recess RS7.

The seventh channel recess RS7 may make the second semiconductor pattern SP2 have a dumbbell shape when viewed in a plan view. For example, the second semiconductor pattern SP2 may include a central portion CTP and side portions EDP on opposite sides of the central portion CTP. The center portion CTP may be interposed between the outer gate electrodes OGE, wherein a vertical distance between an upper surface of the center portion CTP and an upper surface of the side portion EDP is a difference DE7. The side portion EDP may be interposed between the gate spacers GS.

The width CW3 of the side portion EDP in the first direction D1 may be greater than the width CW1 of the center portion CTP in the first direction D1. The difference between widths CW1 and CW3 may be twice the size of difference distance DE7. In some example embodiments of the inventive concepts, the ratio CW1/CW3 of the width CW1 of the central portion CTP to the width CW3 of the side portions EDP may be in the range of about 0.2 to about 0.8.

Fig. 19, 20, and 21 illustrate cross-sectional views showing methods of manufacturing the semiconductor device depicted in fig. 17 and 18, according to some example embodiments of the inventive concepts. In detail, fig. 19 to 21 are sectional views taken along the line D-D' of fig. 4.

Referring to fig. 19, the resulting structure discussed above with reference to fig. 10A to 10C may undergo a process of selectively removing the sacrificial pattern PP and the sacrificial layer SAL. Then, a first mask layer MSL may be formed on the first and second channel patterns CH1 and CH 2.

Referring to fig. 20, a second mask layer PTL may be formed on the first mask layer MSL to selectively cover only the second active area AR2. The second mask layer PTL may expose the first active area AR1.

The second mask layer PTL may be used as an etch mask to selectively remove the exposed first mask layer MSL. Accordingly, the first mask layer MSL may be entirely removed from the first active region AR1. The upper portion of the device isolation layer ST may be over-etched and removed from the first active region AR1 while selectively removing the first mask layer MSL. Accordingly, the device isolation layer ST may have a second step structure STE2 formed on a top surface thereof. The second step structure STE2 may be formed at a boundary of the first active region AR1 and the second active region AR2.

Referring to fig. 21, the second mask layer PTL may be selectively removed. For example, an ashing process may be performed to remove the second mask layer PTL. The exposed upper portions of the first channel pattern CH1 and the first active pattern AP1 may be partially removed while the second mask layer PTL is removed. For example, there may be a loss of exposed semiconductor (e.g., si) during the ashing process. However, when the second mask layer PTL is removed, the first mask layer MSL may protect the second active pattern AP2 and the second channel pattern CH2.

The exposed upper portion of the first active pattern AP1 may be removed to form a first stepped structure STE1 on the upper portion of the first active pattern AP 1. The exposed first channel pattern CH1 may be partially removed. Accordingly, the width CW1 of the nanoplatelets of the first channel pattern CH1 may be smaller than the width CW2 of the nanoplatelets of the second channel pattern CH2. The thickness TK1 of the nanoplatelets of the first channel pattern CH1 may be smaller than the thickness TK4 of the nanoplatelets of the second channel pattern CH2.

The remaining first mask layer MSL may be entirely selectively removed. The subsequent process may be substantially the same as the process discussed above with reference to fig. 12A-12C.

Referring to fig. 22, the recess depths of the first to sixth channel recesses RS1 to RS6 may gradually decrease in a direction from the lower layer to the upper layer. The recess widths of the first to sixth channel recesses RS1 to RS6 in the second direction D2 gradually decrease in the direction from the lower layer to the upper layer.

For example, the second recess depth DE2 of the second channel recess RS2 may be smaller than the first recess depth DE1 of the first channel recess RS 1. The third recess depth DE3 of the third channel recess RS3 may be smaller than the second recess depth DE2 of the second channel recess RS 2. The fourth recess depth DE4 of the fourth channel recess RS4 may be smaller than the third recess depth DE3 of the third channel recess RS 3. The fifth recess depth DE5 of the fifth channel recess RS5 may be smaller than the fourth recess depth DE4 of the fourth channel recess RS 4. The sixth recess depth DE6 of the sixth channel recess RS6 may be less than the fifth recess depth DE5 of the fifth channel recess RS 5.

The second recess width RWI2 of the second channel recess RS2 can be less than the first recess width RWI 1 of the first channel recess RS 1. The third recess width RWI3 of the third channel recess RS3 can be less than the second recess width RWI2 of the second channel recess RS 2. The fourth recess width RWI4 of the fourth channel recess RS4 can be less than the third recess width RWI3 of the third channel recess RS 3. The fifth recess width RWI5 of the fifth channel recess RS5 can be less than the fourth recess width RWI4 of the fourth channel recess RS 4. The sixth recess width RWI6 of the sixth channel recess RS6 can be less than the fifth recess width RWI of the fifth channel recess RS 5.

The body recess BRS may have a recess width that is greater than the recess widths of the channel recesses RS1 to RS6. The body recess BRS may have a recess depth that is greater than the recess depths of the channel recesses RS1 to RS6. For example, the body recess BRS may have a recess depth BDE that is greater than the first recess depth DE1 of the first channel recess RS 1. The body recess BRS may have a recess width BWI that is greater than the first recess width RWI 1 of the first channel recess RS 1.

The widths of the central portions CTP of the first, second and third semiconductor patterns SP1, SP2 and SP3 may gradually increase in a direction from the lower layer to the upper layer. For example, the thickness TK1 of the second semiconductor pattern SP2 may be greater than the thickness TK9 of the first semiconductor pattern SP 1. The thickness TK10 of the third semiconductor pattern SP3 may be greater than the thickness TK1 of the second semiconductor pattern SP 2.

As described above with reference to fig. 15A and 16A, an increase in the size of the internal region IRG may cause an increase in the etching rate of the spacer layer SPL. Thus, an increase in the size of the internal region IRG may cause an increase in the amount of overetch. The overetch may form the body recess BRS and the channel recesses RS1 to RS6 on the first channel pattern CH 1. Accordingly, the channel recess may be formed larger at the lower layer in which the internal region IRG has a large size than at the upper layer in which the internal region IRG has a small size.

Referring to fig. 23, the recess depths of the first to sixth channel recesses RS1 to RS6 may gradually increase in a direction from the lower layer to the upper layer, unlike that described with reference to fig. 22.

For example, the second recess depth DE2 of the second channel recess RS2 may be greater than the first recess depth DE1 of the first channel recess RS 1. The third recess depth DE3 of the third channel recess RS3 may be greater than the second recess depth DE2 of the second channel recess RS 2. The fourth recess depth DE4 of the fourth channel recess RS4 may be greater than the third recess depth DE3 of the third channel recess RS 3. The fifth recess depth DE5 of the fifth channel recess RS5 may be greater than the fourth recess depth DE4 of the fourth channel recess RS 4. The sixth recess depth DE6 of the sixth channel recess RS6 may be greater than the fifth recess depth DE5 of the fifth channel recess RS 5.

The body recess BRS may have a recess depth that is less than the recess depths of the channel recesses RS1 to RS 6. For example, the body recess BRS may have a recess depth BDE that is less than the first recess depth DE1 of the first channel recess RS 1.

The widths of the central portions CTP of the first, second and third semiconductor patterns SP1, SP2 and SP3 may gradually decrease in a direction from the lower layer to the upper layer. For example, the thickness TK1 of the second semiconductor pattern SP2 may be smaller than the thickness TK9 of the first semiconductor pattern SP 1. The thickness TK10 of the third semiconductor pattern SP3 may be smaller than the thickness TK1 of the second semiconductor pattern SP 2.

The dry etching process and the wet etching process of the spacer layer SPL discussed above with reference to fig. 15A and 16A may each have a greater etch rate at the upper layer than at the lower layer. When the etching recipe is adjusted to cause an increase in the etching rate difference according to the layer (or the height from the substrate 100), as shown in fig. 23, a larger channel recess may be formed at the upper layer than at the lower layer.

Referring to fig. 24, the body recess BRS may be omitted from an upper portion of the first active pattern AP 1. For example, the first active pattern AP1 between adjacent first source/drain patterns SD1 may have a flat top surface. The first internal electrode PO1 may have a convex top surface TOS and a flat bottom surface BTS. Since the body recess BRS is omitted, the size (or volume) of the first internal electrode PO1 of the gate electrode GE may be smaller than the size (or volume) of the second internal electrode PO2 of the gate electrode GE. The body recess BRS may be omitted from an upper portion of the second active pattern AP 2.

The semiconductor layer SMCL may be disposed on the top surface of the first active pattern AP 1. The semiconductor layer SMCL may be an epitaxial layer grown from the top surface of the first active pattern AP 1. The semiconductor layer SMCL may include one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, when the semiconductor layer SMCL includes silicon (Si), a distinct boundary may not be provided between the semiconductor layer SMCL and the first active pattern AP 1. The semiconductor layer SMCL may be used to reduce or prevent formation of body recesses.

Fig. 25 illustrates a cross-sectional view taken along line A-A' of fig. 4, showing a semiconductor device according to some example embodiments of the inventive concepts. Referring to fig. 25, the first channel pattern CH1 may include first to fourth semiconductor patterns SP1 to SP4 stacked in order. For example, the first channel pattern CH1 may include four nano-sheets connecting a pair of first source/drain patterns SD1 to each other.

A three-dimensional semiconductor device according to some example embodiments of the inventive concepts may include MBCFET or GAAFET in which N nano-sheets are stacked. N may be an integer equal to or greater than 2. For example, a transistor according to the inventive concept may include two, three, four, five, or more than five nanoplatelets.

The gate electrode GE may include first to fourth electrodes PO1 to PO4 disposed under the first to fourth semiconductor patterns SP1 to SP4, respectively (e.g., the first to fourth electrodes PO1 to PO4 are closer to the top and/or bottom surfaces 100a and 100b of the substrate 100 than the first to fourth semiconductor patterns SP1 to SP4, respectively). The gate electrode GE may further include an outer gate electrode OGE on the uppermost semiconductor pattern or the fourth semiconductor pattern SP4. The first to fourth electrodes PO1 to PO4 may be gradually reduced in size (or volume) in a direction from the lower layer to the upper layer.

Fig. 26A and 26B illustrate enlarged views showing a portion M of fig. 5A and a portion N of fig. 5B, respectively, according to some example embodiments of the inventive concepts. Referring to fig. 26A and 26B, each of the first, second, and third internal electrodes PO1, PO2, and PO3 on the first active pattern AP1 may each have a lateral surface SIS protruding toward the first source/drain pattern SD 1. The first, second and third internal electrodes PO1, PO2 and PO3 on the second active pattern AP2 may each have a lateral surface SIS protruding toward the second source/drain pattern SD 2.

The inner spacer ISP interposed between the second inner electrode PO2 and the source/drain pattern SD1 or SD2 may have an hourglass shape. The thickness of the inner spacer ISP in the second direction D2 may decrease and then increase in a direction from the first semiconductor pattern SP1 toward the second semiconductor pattern SP 2.

The inner spacer ISP on the first active pattern AP1 may have an eleventh thickness TK11 at its center, and the inner spacer ISP on the second active pattern AP2 may have a twelfth thickness TK12 at its center. The eleventh thickness TK11 and the twelfth thickness TK12 may be different from each other.

In some example embodiments of the inventive concepts, the eleventh thickness TK11 may be less than the twelfth thickness TK12. For example, the lateral surfaces SIS of the internal electrodes PO1 to PO3 on the first active pattern AP1 may protrude horizontally more than the lateral surfaces SIS of the internal electrodes PO1 to PO3 on the second active pattern AP 2.

Fig. 27A and 27B illustrate enlarged views showing a portion M of fig. 5A and a portion N of fig. 5B, respectively, according to some example embodiments of the inventive concepts. Referring to fig. 27A and 27B, the first, second and third internal electrodes PO1, PO2 and PO3 on the first active pattern AP1 may have a lateral surface SIS recessed in a direction away from the first source/drain pattern SD 1. Each of the first, second, and third internal electrodes PO1, PO2, and PO3 on the second active pattern AP2 may have a lateral surface SIS recessed in a direction away from the second source/drain pattern SD 2.

The inner spacer ISP interposed between the second inner electrode PO2 and the source/drain pattern SD1 or SD2 may have a half-moon shape or a crescent shape.

The inner spacer ISP on the first active pattern AP1 may have a thirteenth thickness TK13 at its center, and the inner spacer ISP on the second active pattern AP2 may have a fourteenth thickness TK14 at its center. The thirteenth thickness TK13 and the fourteenth thickness TK14 may be different from each other.

In some example embodiments of the inventive concepts, thirteenth thickness TK13 may be greater than fourteenth thickness TK14. For example, the lateral surfaces SIS of the internal electrodes PO1 to PO3 on the first active pattern AP1 may be recessed more horizontally than the lateral surfaces SIS of the internal electrodes PO1 to PO3 on the second active pattern AP 2.

In the three-dimensional field effect transistor according to the inventive concept, since the nano-sheet of the NMOSFET includes a channel recess, an Effective Channel Length (ECL) may be increased. Accordingly, the inventive concept may reduce or prevent short channel effects and improve electrical properties of the device.

The inventive concept can selectively tune an NMOSFET to have a small channel thickness while allowing the PMOSFET to maintain its relatively large channel thickness. Accordingly, the electrical properties of the NMOSFET may be improved without degrading the performance of the PMOSFET, thereby improving the performance of the semiconductor device including the NMOSFET and the PMOSFET.

Although some example embodiments of the present inventive concept have been discussed with reference to the accompanying drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the inventive concept. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made thereto without departing from the scope and spirit of the present inventive concept.

Claims

1. A semiconductor device, comprising:

a substrate including an N-type metal oxide semiconductor field effect transistor region and a P-type metal oxide semiconductor field effect transistor region opposite to each other;

A first channel pattern on the N-type metal oxide semiconductor field effect transistor region and a second channel pattern on the P-type metal oxide semiconductor field effect transistor region, each of the first and second channel patterns including a plurality of semiconductor patterns spaced apart from each other and vertically stacked;

a first source/drain pattern on the N-type metal oxide semiconductor field effect transistor region and a second source/drain pattern on the P-type metal oxide semiconductor field effect transistor region, the first source/drain pattern being connected to the first channel pattern and the second source/drain pattern being connected to the second channel pattern; and

a gate electrode on the first channel pattern and the second channel pattern,

wherein the gate electrode includes:

a first internal electrode located between adjacent ones of the plurality of semiconductor patterns of the first channel pattern, an

A second internal electrode located between adjacent ones of the plurality of semiconductor patterns of the second channel pattern, and

wherein the top surface of the first inner electrode is more convex than the top surface of the second inner electrode.

2. The semiconductor device according to claim 1, wherein the first internal electrode and the second internal electrode are located in the same layer.

3. The semiconductor device according to claim 1, wherein a bottom surface of the first inner electrode is more convex than a bottom surface of the second inner electrode.

4. The semiconductor device according to claim 1, wherein a width of the first internal electrode is larger than a width of the second internal electrode.

5. The semiconductor device of claim 1, wherein,

the plurality of semiconductor patterns of the first channel pattern include a first semiconductor pattern adjacent to a top surface of the first internal electrode,

the plurality of semiconductor patterns of the second channel pattern include a second semiconductor pattern adjacent to the top surface of the second internal electrode, and

a thickness at a central portion of the first semiconductor pattern is smaller than a thickness at a central portion of the second semiconductor pattern.

6. The semiconductor device according to claim 5, wherein a ratio of a thickness at a central portion of the first semiconductor pattern to a thickness at a side portion of the first semiconductor pattern is in a range of 0.2 to 0.8.

7. The semiconductor device according to claim 5, wherein a ratio of a thickness at a center portion of the second semiconductor pattern to a thickness at a side portion of the second semiconductor pattern is in a range of 0.8 to 1.0.

8. The semiconductor device according to claim 5, wherein a thickness at a side portion of the first semiconductor pattern is the same as a thickness at a side portion of the second semiconductor pattern.

9. The semiconductor device of claim 5, wherein,

the first inner electrode has an eye shape, and

the first semiconductor pattern has a dumbbell shape.

10. The semiconductor device according to claim 1, further comprising:

a device isolation layer filling a trench between the N-type metal oxide semiconductor field effect transistor region and the P-type metal oxide semiconductor field effect transistor region,

wherein a top surface of the device isolation layer under the gate electrode includes a stepped structure, wherein a level of the top surface of the device isolation layer in a vertical direction discontinuously changes in a horizontal direction.

11. A semiconductor device, comprising:

a substrate including an active pattern;

a channel pattern on the active pattern, the channel pattern including a plurality of semiconductor patterns spaced apart from each other and vertically stacked;

source/drain electrode pattern, it connects said multiple semiconductor pattern each other; and

a gate electrode on the plurality of semiconductor patterns,

Wherein the gate electrode includes a first internal electrode and a second internal electrode adjacent to each other,

wherein the plurality of semiconductor patterns includes a first semiconductor pattern between the first and second internal electrodes,

wherein the first semiconductor pattern includes:

a central portion located between the convex top surface of the first inner electrode and the convex bottom surface of the second inner electrode, an

A side portion connected to the source/drain pattern,

wherein the thickness of the central portion has a minimum value at the center of the central portion of the first semiconductor pattern and gradually increases in a direction from the center of the central portion of the first semiconductor pattern toward the side portion of the first semiconductor pattern, the minimum value of the thickness of the central portion of the first semiconductor pattern being the minimum thickness of the central portion of the first semiconductor pattern, and

wherein a ratio of the minimum thickness of the center portion of the first semiconductor pattern to a thickness of the side portion of the first semiconductor pattern is in a range of 0.2 to 0.8.

12. The semiconductor device of claim 11, wherein,

The raised top surface of the first inner electrode defines a first channel recess on the bottom surface of the first semiconductor pattern,

the convex bottom surface of the second inner electrode defines a second channel recess on the top surface of the first semiconductor pattern, and

the recess depth of the first channel recess is different from the recess depth of the second channel recess.

13. The semiconductor device of claim 11, wherein,

each of the first and second inner electrodes has an eye shape, and

the first semiconductor pattern has a dumbbell shape.

14. The semiconductor device of claim 11, wherein,

the gate electrode further includes a third internal electrode on the second internal electrode,

the plurality of semiconductor patterns further includes a second semiconductor pattern located between the second internal electrode and the third internal electrode, and

a minimum thickness of a central portion of the second semiconductor pattern is different from a minimum thickness of a central portion of the first semiconductor pattern.

15. The semiconductor device according to claim 14, wherein a thickness of a side portion of the second semiconductor pattern is the same as a thickness of a side portion of the first semiconductor pattern.

16. A semiconductor device, comprising:

a device isolation layer filling a trench between the N-type metal oxide semiconductor field effect transistor region and the P-type metal oxide semiconductor field effect transistor region;

a first source/drain pattern on the N-type metal oxide semiconductor field effect transistor region and a second source/drain pattern on the P-type metal oxide semiconductor field effect transistor region, the first source/drain pattern being connected to the first channel pattern and the second source/drain pattern being connected to the second channel pattern;

a gate electrode on the first channel pattern and the second channel pattern, the gate electrode including a first internal electrode between adjacent semiconductor patterns of the plurality of semiconductor patterns of the first channel pattern and a second internal electrode between adjacent semiconductor patterns of the plurality of semiconductor patterns of the second channel pattern;

A gate dielectric layer surrounding each of the first and second internal electrodes;

a gate spacer on a sidewall of the gate electrode;

a gate capping pattern on a top surface of the gate electrode;

an interlayer dielectric layer on the gate capping pattern;

an active contact penetrating the interlayer dielectric layer to be electrically connected with one of the first source/drain pattern and the second source/drain pattern;

a metal-semiconductor compound layer between the active contact and one of the first and second source/drain patterns;

a gate contact penetrating the interlayer dielectric layer and the gate capping pattern to be electrically connected with the gate electrode;

a first metal layer on the interlayer dielectric layer, the first metal layer including power lines and first routing lines electrically connected to separate respective contacts of the active contacts or the gate contacts; and

a second metal layer on the first metal layer,

wherein the second metal layer includes a second wiring line electrically connected to the first metal layer,

Wherein the first channel pattern includes a first semiconductor pattern adjacent to a convex top surface of the first internal electrode,

wherein the second channel pattern includes a second semiconductor pattern adjacent to a top surface of the second internal electrode,

wherein the maximum thickness of the first inner electrode is greater than the maximum thickness of the second inner electrode, and

wherein the minimum thickness of the first semiconductor pattern is smaller than the minimum thickness of the second semiconductor pattern.

17. The semiconductor device of claim 16, wherein,

the first semiconductor pattern includes a side portion connected to the first source/drain pattern, and

a ratio of a minimum thickness of the first semiconductor pattern to a thickness of a side portion of the first semiconductor pattern is in a range of 0.2 to 0.8.

18. The semiconductor device of claim 16, wherein,

the second semiconductor pattern includes a side portion connected to the second source/drain pattern, and

a ratio of a minimum thickness of the second semiconductor pattern to a thickness of a side portion of the second semiconductor pattern is in a range of 0.8 to 1.0.

19. The semiconductor device of claim 16, wherein,

The first semiconductor pattern includes a first side portion connected to the first source/drain pattern,

the second semiconductor pattern includes a second side portion connected to the second source/drain pattern, and

the thickness of the first side portion is the same as the thickness of the second side portion.

20. The semiconductor device of claim 16, wherein a convex top surface of the first inner electrode is more convex than a top surface of the second inner electrode.