CN117590635A

CN117590635A - Array substrate, manufacturing method and embedded touch display panel

Info

Publication number: CN117590635A
Application number: CN202311843915.4A
Authority: CN
Inventors: 王新刚; 楚方方
Original assignee: InfoVision Optoelectronics Kunshan Co Ltd
Current assignee: InfoVision Optoelectronics Kunshan Co Ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-02-23

Abstract

The invention discloses an array substrate, a manufacturing method and an embedded touch display panel, wherein pixel electrodes are electrically connected with corresponding scanning lines and data lines through first thin film transistors, all public electrode blocks are electrically connected with each other through a plurality of second thin film transistors, each public electrode block is electrically connected with a corresponding touch wiring, and the second thin film transistors are controlled through control lines, so that in a display time period, all public electrode blocks can be electrically connected together through the control lines to ensure that the voltages of the public electrode blocks at different positions are the same, and the problem of uneven display is avoided; and the control line comprises a first section of control line which is arranged on the same layer as the scanning line and a second section of control line which is arranged on the same layer as the data line, and the grid electrode, the active layer, the source electrode and the drain electrode of the first thin film transistor and the second thin film transistor are respectively positioned on the same layer, so that the structure and the manufacturing process of the array substrate are simplified, and the manufacturing cost is reduced.

Description

Array substrate, manufacturing method and embedded touch display panel

Technical Field

The invention relates to the technical field of displays, in particular to an array substrate, a manufacturing method and an embedded touch display panel.

Background

The liquid crystal display panel has the advantages of good image quality, small volume, light weight, low driving voltage, low power consumption, no radiation and relatively low manufacturing cost, and is dominant in the field of flat panel display. With rapid development of display technology, touch display panels have been widely accepted and used by people, such as smart phones and tablet computers. The touch display panel combines the touch panel and the liquid crystal display panel into a whole by adopting an embedded touch technology, and the function of the touch panel is embedded into the liquid crystal display panel, so that the liquid crystal display panel has the functions of displaying and sensing touch input.

According to the different arrangement modes of the touch sensing layer In the display panel, the touch display panel is divided into structures such as an externally-hung (Addon Mode), an embedded (In-cell) and an externally-embedded (On-cell). The embedded touch screen integrates the touch function in the display screen, so that the thickness of the whole display can be effectively reduced, the production process is simplified, the product is lighter and thinner, the production cost is lower, and the embedded touch screen is popular.

Currently, for in-cell touch screens, the touch screen structure is usually directly disposed on an array substrate, and some structural components for transmitting display signals are mainly multiplexed into touch electrodes in the array substrate, and it is quite common to multiplex a common electrode block into touch electrodes. The array substrate is not only required to be provided with scanning lines and data lines, but also required to be provided with touch control wiring, and then common signals and touch control signals are transmitted to the common electrode block through the touch control wiring. Because the plurality of public electrode blocks are mutually independent and distributed at intervals, the voltages of the public electrode blocks at different positions in the display time are different, so that the formed electric fields between the different public electrode blocks and the pixel electrodes are different, the brightness of the corresponding areas of the different public electrode blocks is slightly different, further, the electrode blocks Mura (uneven display) are generated, and the abnormality is particularly prominent for products with larger touch delay. In addition, the structure of the array substrate of the existing embedded touch screen is complex, the manufacturing process times are more, and the manufacturing cost is higher.

Disclosure of Invention

In order to overcome the defects and shortcomings in the prior art, the invention aims to provide an array substrate, a manufacturing method and an embedded touch display panel, so as to solve the problems that the brightness of corresponding areas of different common electrode blocks on the array substrate in the prior art is uneven and the manufacturing process is complex.

The aim of the invention is achieved by the following technical scheme:

the invention provides an array substrate, comprising:

a substrate;

the first metal layer comprises a scanning line, a first grid electrode, a first section of control line and a second grid electrode, wherein the first grid electrode is in conductive connection with the scanning line, the second grid electrode is in conductive connection with the first section of control line, and the first section of control line is disconnected in a region crossing the scanning line;

the first insulating layer is arranged above the first metal layer and covers the scanning line, the first grid electrode, the first section control line and the second grid electrode;

the semiconductor layer is arranged above the first insulating layer and comprises a first active layer corresponding to the first grid electrode and a second active layer corresponding to the second grid electrode;

the second metal layer comprises a data line, a first source electrode, a first drain electrode, a touch running line, a second section control line, a second source electrode and a second drain electrode, wherein the data line is in conductive connection with the first source electrode, the first source electrode is in conductive connection with the first drain electrode through the first active layer, the second source electrode is in conductive connection with the second drain electrode through the second active layer, the second section control line spans the scanning line and is used for conducting connection of two disconnected adjacent sections of the first section control line to form a control line, the first grid electrode, the first active layer, the first source electrode and the first drain electrode jointly form a first thin film transistor, the first thin film transistor is controlled through the scanning line, the second grid electrode, the second active layer, the second source electrode and the second drain electrode jointly form a second thin film transistor, and the second thin film transistor is controlled through the control line and the data running line are mutually arranged in parallel;

The first transparent conductive layer is arranged above the second metal layer and comprises a plurality of pixel electrodes, and the pixel electrodes are electrically connected with the corresponding scanning lines and the data lines through the first thin film transistors;

the second transparent conductive layer is arranged above the second metal layer and is mutually insulated and spaced from the first transparent conductive layer, the second transparent conductive layer comprises a plurality of public electrode blocks, each public electrode block is electrically connected with the corresponding touch wiring, all public electrode blocks are mutually electrically connected through a plurality of second thin film transistors, and a second source electrode and a second drain electrode of each second thin film transistor are respectively connected with two adjacent public electrode blocks.

Further, the array substrate includes:

the second insulating layer is arranged above the second metal layer and covers the first active layer, the second active layer, the data line, the first source electrode, the first drain electrode, the touch trace, the second section control line, the second source electrode and the second drain electrode;

the first transparent conducting layer and the second transparent conducting layer are both arranged above the second insulating layer;

And a third insulating layer disposed between the first transparent conductive layer and the second transparent conductive layer, the first transparent conductive layer and the second transparent conductive layer being insulated from each other and spaced apart by the third insulating layer.

Further, the first transparent conductive layer is arranged below the second transparent conductive layer, the first transparent conductive layer further comprises a bridging electrode, and the first section of control line and the second section of control line are mutually and electrically connected through the bridging electrode;

or, the second transparent conductive layer is arranged below the first transparent conductive layer, the second transparent conductive layer further comprises a bridging electrode, and the first section of control line and the second section of control line are mutually and conductively connected through the bridging electrode.

Further, each of the control lines controls a plurality of the second thin film transistors;

the adjacent four public electrode blocks are electrically connected with each other through four second thin film transistors; or the adjacent four public electrode blocks are electrically connected with each other through the three second thin film transistors.

Further, the plurality of second thin film transistors correspond to the same first section control line, and the plurality of second thin film transistors corresponding to the same first section control line are connected in a conductive manner;

Or, the projection of the second active layer on the substrate is positioned in the first section control line area, and the area corresponding to the first section control line and the second active layer is used as the second grid electrode.

The application also provides an embedded touch display panel, which comprises an array substrate, a color film substrate arranged opposite to the array substrate, and a liquid crystal layer arranged between the array substrate and the color film substrate, wherein the array substrate is the array substrate.

The application also provides a manufacturing method of the array substrate, which comprises the following steps:

providing a substrate;

forming a first metal layer above the substrate, etching the first metal layer, and forming a patterned scanning line, a first grid, a first section of control line and a second grid, wherein the first grid is in conductive connection with the scanning line, the second grid is in conductive connection with the first section of control line, and the first section of control line is disconnected in a region crossing the scanning line;

forming a first insulating layer over the first metal layer to cover the scan lines, the gate electrodes, the first segment control lines, and the second gate electrodes;

Forming a semiconductor layer above the first insulating layer, etching the semiconductor layer, and forming a patterned first active layer and a patterned second active layer, wherein the first active layer corresponds to the first grid electrode, and the second active layer corresponds to the second grid electrode;

forming a second metal layer above the first insulating layer, etching the second metal layer, forming a patterned data line, a first source electrode, a first drain electrode, a touch trace, a second section control line, a second source electrode and a second drain electrode on the second metal layer, wherein the data line is electrically connected with the first source electrode, the first source electrode is electrically connected with the first drain electrode through the first active layer, the second source electrode is electrically connected with the second drain electrode through the second active layer, the second section control line spans the scanning line and electrically connects two disconnected adjacent sections of the first section control line to form a control line, the first gate electrode, the first active layer, the first source electrode and the first drain electrode jointly form a first thin film transistor, the first thin film transistor is controlled through the scanning line, the second gate electrode, the second active layer, the second source electrode and the second drain electrode jointly form a second thin film transistor, and the second thin film transistor are mutually aligned through the scanning line and the second control line;

Forming a first transparent conductive layer above the second metal layer, etching the first transparent conductive layer, wherein the first transparent conductive layer forms a plurality of patterned pixel electrodes, and the pixel electrodes are electrically connected with the corresponding scanning lines and the data lines through the first thin film transistors;

forming a second transparent conductive layer which is mutually insulated and spaced from the first transparent conductive layer above the second metal layer, etching the second transparent conductive layer, forming a plurality of patterned public electrode blocks on the second transparent conductive layer, wherein each public electrode block is electrically connected with a corresponding touch trace, all public electrode blocks are mutually electrically connected through a plurality of second thin film transistors, and each second thin film transistor is connected with two adjacent public electrode blocks.

Further, the method comprises the steps of:

forming a second insulating layer covering the first active layer, the second active layer, the data line, the first source electrode, the first drain electrode, the touch trace, the second segment control line, the second source electrode, and the second drain electrode over the second metal layer;

Further, the first transparent conductive layer is arranged below the second transparent conductive layer, the first transparent conductive layer also forms a patterned bridging electrode, and the first section control line and the second section control line are mutually and conductively connected through the bridging electrode;

or, the second transparent conductive layer is arranged below the first transparent conductive layer, the second transparent conductive layer also forms a patterned bridging electrode, and the first section control line and the second section control line are mutually and conductively connected through the bridging electrode.

the adjacent four public electrode blocks are electrically connected with each other through four second thin film transistors; or the adjacent four public electrode blocks are electrically connected with each other through three second thin film transistors;

The second thin film transistors correspond to the same first section control line, and the second thin film transistors corresponding to the same first section control line are connected in a conductive mode.

The invention has the beneficial effects that: on the array substrate, the pixel electrodes are electrically connected with corresponding scanning lines and data lines through first thin film transistors, all public electrode blocks are electrically connected with each other through a plurality of second thin film transistors, each public electrode block is electrically connected with a corresponding touch running line, and the second thin film transistors are controlled through control lines, so that in a display time period, all public electrode blocks can be electrically connected together through the control lines for controlling the second thin film transistors, the same voltage of the public electrode blocks at different positions is ensured, the problem of uneven display is avoided, and in a touch time period, all public electrode blocks can be mutually disconnected through the control lines for controlling the second thin film transistors, so that the pixel electrodes are used as touch electrodes, and the touch function is not affected; and the control line comprises a first section of control line which is arranged on the same layer as the scanning line and a second section of control line which is arranged on the same layer as the data line, and the grid electrode, the active layer, the source electrode and the drain electrode of the first thin film transistor and the second thin film transistor can be respectively positioned on the same layer through arranging the first section of control line and the scanning line on the same layer, so that the structure and the manufacturing process of the array substrate are simplified, and the thickness and the manufacturing cost of the array substrate are reduced.

Drawings

FIG. 1 is a schematic plan view of a common electrode according to a first embodiment of the present invention;

FIG. 2 is a schematic plan view of four common electrode blocks according to a first embodiment of the present invention;

FIG. 3 is a second schematic plan view of four common electrode blocks according to the first embodiment of the present invention;

FIG. 4 is a third schematic plan view of four common electrode blocks according to the first embodiment of the present invention;

FIG. 5 is a schematic plan view of four common electrode blocks according to a first embodiment of the present invention;

FIG. 6 is a schematic plan view of an array substrate according to a first embodiment of the present invention;

FIG. 7 is a schematic view of an enlarged planar structure of an array substrate according to a first embodiment of the present invention;

FIG. 8 is a schematic plan view of a common electrode block, control lines and touch traces according to an embodiment of the invention;

FIG. 9 is a schematic cross-sectional view of an array substrate along the A-A direction in FIG. 7 according to a first embodiment of the present invention;

FIG. 10 is a schematic cross-sectional view of an array substrate along the direction B-B in FIG. 7 according to the first embodiment of the present invention;

FIG. 11 is a schematic diagram of a driving waveform of an array substrate according to a first embodiment of the present invention;

fig. 12-1 to 16-3 are schematic structural views of a method for manufacturing an array substrate according to a first embodiment of the invention;

FIG. 17 is a schematic diagram of an enlarged planar structure of an array substrate according to a second embodiment of the present invention;

FIG. 18 is a schematic cross-sectional view of an array substrate along the direction C-C in FIG. 17 according to a second embodiment of the present invention;

FIG. 19 is a schematic view showing the structure of the display device in the dark state according to the present invention;

fig. 20 is a schematic view of the structure of the display device in the bright state according to the present invention.

Detailed Description

In order to further describe the technical means and effects adopted for achieving the preset aim of the present invention, the following detailed description is given of the specific implementation, structure, characteristics and effects of the array substrate and manufacturing method, embedded touch display panel according to the present invention with reference to the accompanying drawings and the preferred embodiments, wherein:

example one

Fig. 1 is a schematic plan view of a common electrode according to a first embodiment of the present invention. Fig. 2 is a schematic plan view of four common electrode blocks according to a first embodiment of the present invention. Fig. 3 is a second schematic plan view of four common electrode blocks according to the first embodiment of the present invention. Fig. 4 is a third schematic plan view of four common electrode blocks according to the first embodiment of the present invention. Fig. 5 is a schematic plan view of four common electrode blocks in the first embodiment of the present invention. Fig. 6 is a schematic plan view of an array substrate according to a first embodiment of the invention. Fig. 7 is a schematic plan view of an enlarged structure of an array substrate according to a first embodiment of the present invention. Fig. 8 is a schematic plan view of a common electrode block, a control line and a touch trace according to an embodiment of the invention. FIG. 9 is a schematic cross-sectional view of an array substrate along A-A in FIG. 7 according to a first embodiment of the present invention. FIG. 10 is a schematic cross-sectional view of an array substrate along the direction B-B in FIG. 7 according to the first embodiment of the present invention.

As shown in fig. 1 to 10, an array substrate according to a first embodiment of the present invention includes:

the substrate 10, the substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, and the substrate 10 may also be a flexible substrate, with suitable materials for the flexible substrate including, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or combinations thereof.

The first metal layer 11 is disposed above the substrate 10, the first metal layer 11 includes a scan line 111, a first gate 112, a first section of control line 113, and a second gate 114, the first gate 112 is electrically connected to the scan line 111, the second gate 114 is electrically connected to the first section of control line 113, the first section of control line 113 is disconnected in a region intersecting with the scan line 111, the first section of control line 113 is perpendicular to the extending direction of the scan line 111, and a certain distance is provided between the first section of control line 113 and the scan line 111 to prevent the first section of control line 113 from shorting with the scan line 111. In this embodiment, the first gate 112 is a branch electrode protruding from the scan line 111, and the second gate 114 is a part of the first control line 113, i.e. a part of the first control line 113 is used as the second gate 114, so as to avoid affecting the aperture ratio of the pixel. Of course, the first gate electrode 112 may be a part of the scan line 111, and a part of the scan line 111 may be the first gate electrode 112, thereby increasing the aperture ratio of the pixel. The first metal layer 11 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.

The first insulating layer 101 is disposed above the first metal layer 11, and the first insulating layer 101 covers the scan line 111, the first gate 112, the first segment control line 113, and the second gate 114. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

The semiconductor layer 12 is disposed over the first insulating layer 101, and the semiconductor layer 12 includes a first active layer 121 corresponding to the first gate electrode 112 and a second active layer 122 corresponding to the second gate electrode 114. The projection of the second active layer 122 on the substrate 10 is located in the area of the first section control line 113, and the area of the first section control line 113 corresponding to the second active layer 122 is used as the second gate 114, so that the influence on the aperture ratio of the pixel is avoided. The material of the semiconductor layer 12 is amorphous silicon (a-Si) and doped amorphous silicon.

The second metal layer 13 is disposed on the first insulating layer 101, and the second metal layer 13 includes a data line 131, a first source 132, a first drain 133, a touch trace 134, a second segment control line 135, a second source 136, and a second drain 137. The data line 131 is electrically connected to the first source electrode 132, and the first source electrode 132 is electrically connected to the first drain electrode 133 through the first active layer 121. The second source electrode 136 and the second drain electrode 137 are electrically connected through the second active layer 122. The second segment control lines 135 cross the scan lines 111 and electrically connect the disconnected adjacent two first segment control lines 113 to form the control lines 1, and the plurality of first segment control lines 113 and the plurality of second segment control lines 135 are alternately arranged along the direction of the control lines 1. The first gate electrode 112, the first active layer 121, the first source electrode 132, and the first drain electrode 133 collectively form a first thin film transistor 2, and the first thin film transistor 2 is controlled by the scan line 111. The second gate electrode 114, the second active layer 122, the second source electrode 136, and the second drain electrode 137 together form a second thin film transistor 3, and the second thin film transistor 3 is controlled by the control line 1. The touch trace 134, the data line 131 and the control line 1 are arranged in parallel. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.

The control line 1 includes a first section of control line 113 disposed on the same layer as the scan line 111 and a second section of control line 135 disposed on the same layer as the data line 131, and the first section of control line 113 of the control line 1 is disposed on the same layer as the scan line 111 to ensure that the first gate 112 of the first thin film transistor 2 and the second gate 114 of the second thin film transistor 3 are disposed on the same layer and are etched by the first metal layer 11, the first active layer 121 of the first thin film transistor 2 and the second active layer 122 of the second thin film transistor 3 are disposed on the same layer and are etched by the semiconductor layer 12, the first source 132 of the first thin film transistor 2, the first drain 133 and the second source 136 of the second thin film transistor 3 are disposed on the same layer and are etched by the second metal layer 13, so as to simplify the structure and manufacturing process of the array substrate, and reduce the thickness and manufacturing cost of the array substrate.

The first transparent conductive layer 14 disposed above the second metal layer 13, where the first transparent conductive layer 14 includes a plurality of pixel electrodes 141, the pixel electrodes 141 are electrically connected to the first drain electrodes 133 of the first thin film transistors 2, and the pixel electrodes 141 are electrically connected to the corresponding scan lines 111 and the data lines 131 through the first thin film transistors 2. The material of the first transparent conductive layer 14 is Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or the like.

The second transparent conductive layer 15 is disposed above the second metal layer 13 and is insulated from the first transparent conductive layer 14, and the second transparent conductive layer 15 includes a plurality of common electrode blocks 151, and each common electrode block 151 is electrically connected to the corresponding touch trace 134, so that a touch signal is applied to the common electrode block 151 in a touch time period, and a touch function is realized. All the public electrode blocks 151 are electrically connected with each other through a plurality of second thin film transistors 3, and the second source 136 and the second drain 137 of each second thin film transistor 3 are respectively connected with two adjacent public electrode blocks 151, so that in the display time period, the second thin film transistors 3 can be controlled by the control line 1 to electrically connect all the public electrode blocks 151 together, the same voltage of the public electrode blocks 151 at different positions is ensured, and the problem of uneven display is avoided; in the touch time period, the control line 1 can control the second thin film transistor 3 to disconnect all the common electrode blocks 151 from each other, so that the common electrode blocks are used as touch electrodes, and a touch function is realized. The material of the second transparent conductive layer 15 is Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or the like.

As shown in fig. 7 and 8, the common electrode block 151 at the upper left corner and the common electrode block 151 at the lower left corner are electrically connected at the left side by the second thin film transistor 3, which is not shown in the drawings, and the connection structure may refer to the connection manner of the common electrode block 151 at the upper right corner and the common electrode block 151 at the lower right corner in the drawings.

As shown in fig. 9 and 10, in the present embodiment, the array substrate further includes a second insulating layer 102 disposed above the second metal layer 13, and the first transparent conductive layer 14 and the second transparent conductive layer 15 are disposed above the second insulating layer 102. The second insulating layer 102 covers the first active layer 121, the second active layer 122, the data line 131, the first source electrode 132, the first drain electrode 133, the touch trace 134, the second segment control line 135, the second source electrode 136, and the second drain electrode 137. The second insulating layer 102 may be a flat layer, and the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. Of course, in other embodiments, the second insulating layer 102 may not be provided, and the first transparent conductive layer 14 may be directly covered on the second metal layer 13, so that the pixel electrode 141 is directly in conductive contact with the first drain electrode 133 of the first thin film transistor 2, one end of the bridge electrode 142 is directly in conductive contact with the second section control line 135, and the other end of the bridge electrode 142 is electrically connected with the first section control line 113 through a contact hole on the first insulating layer 101, so as to further simplify the structure and manufacturing process, and reduce the thickness and manufacturing cost of the array substrate.

In this embodiment, the first transparent conductive layer 14 is disposed below the second transparent conductive layer 15, that is, the pixel electrode 141 is disposed below the common electrode block 151, the pixel electrode 141 is a block electrode corresponding to the pixel unit SP (fig. 6), the common electrode block 151 is a comb-shaped electrode with slits in a region corresponding to the pixel unit SP, and each common electrode block 151 may cover a plurality of pixel units SP. The first transparent conductive layer 14 further includes a bridging electrode 142, and the first segment control line 113 and the second segment control line 135 are electrically connected to each other through the bridging electrode 142.

Of course, in other embodiments, the second transparent conductive layer 15 may be disposed below the first transparent conductive layer 14, that is, the common electrode block 151 is disposed below the pixel electrode 141, and the pixel electrode 141 is a comb-shaped electrode having slits corresponding to the pixel units SP (fig. 6). The second transparent conductive layer 15 further includes a bridging electrode 142, and the first segment control line 113 and the second segment control line 135 are electrically connected to each other through the bridging electrode 142. Alternatively, in another embodiment, the first transparent conductive layer 14 and the second transparent conductive layer 15 are both provided with bridging electrodes 142, and the adjacent first segment control lines 113 and second segment control lines 135 are electrically connected to each other through the two layers of bridging electrodes 142, so as to reduce the resistance of the bridging electrodes 142, so as to increase the conductivity of the control lines 1. Still alternatively, in another embodiment, the bridging electrode 142 does not need to be disposed on the first transparent conductive layer 14 and/or the second transparent conductive layer 15, and the first insulating layer 101 is first perforated in the area corresponding to the first segment control line 113, and the second segment control line 135 is directly connected to the first segment control line 113 through the perforation, but a mask process step of individually perforating the first insulating layer 101 is added.

In this embodiment, the second insulating layer 102 is provided with a first contact hole TH1 (fig. 14-2) in a region corresponding to the first drain electrode 133, and the pixel electrode 141 is electrically connected to the first drain electrode 133 of the first thin film transistor 2 through the first contact hole TH 1; the second insulating layer 102 is provided with a second contact hole TH2 (fig. 14-3) at an end region corresponding to the second segment control line 135, and the first insulating layer 101 and the second insulating layer 102 are provided with a third contact hole TH3 (fig. 14-3) at an end region corresponding to the first segment control line 113, and each bridge electrode 142 is electrically connected to the first segment control line 113 and the second segment control line 135 through the second contact hole TH2 and the third contact hole TH3, respectively.

Further, the array substrate further includes a third insulating layer 103 disposed between the first transparent conductive layer 14 and the second transparent conductive layer 15, and the first transparent conductive layer 14 and the second transparent conductive layer 15 are insulated from each other and spaced apart by the third insulating layer 103. The material of the third insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both. The second insulating layer 102 and the third insulating layer 103 are provided with fourth contact holes TH4 (fig. 15-2) in the area corresponding to the touch trace 134, and the second insulating layer 102 and the third insulating layer 103 are respectively provided with fifth contact holes TH5 and sixth contact holes TH6 (fig. 15-3) in the area corresponding to the second source 136 and the second drain 137, each common electrode block 151 is electrically connected with the corresponding touch trace 134 through the fourth contact holes TH4, and two adjacent common electrode blocks 151 are electrically connected with the second source 136 and the second drain 137 of the corresponding same second thin film transistor 3 through the fifth contact holes TH5 and the sixth contact holes TH6, respectively, so that each second thin film transistor 3 is connected with two adjacent common electrode blocks 151.

As shown in fig. 8 and 10, the second transparent conductive layer 15 further includes a conductive portion 152 electrically connected to the common electrode block 151, and since some common electrode blocks 151 need to be connected to the plurality of second thin film transistors 3, the common electrode block 151 may be electrically connected to the corresponding plurality of second thin film transistors 3 through the plurality of conductive portions 152.

Further, as shown in fig. 1, 7 and 8, each control line 1 controls a plurality of second thin film transistors 3, i.e., the plurality of second thin film transistors 3 share one control line 1, so that the number of control lines 1 can be reduced. As shown in fig. 1 and 2, the adjacent four common electrode blocks 151 are electrically connected to each other through the four second thin film transistors 3, so that the conductivity between the adjacent four common electrode blocks 151 is better during the display period. Of course, as shown in fig. 3 to 5, four adjacent common electrode blocks 151 may be electrically connected to each other through three second thin film transistors 3, so as to reduce the number of the second thin film transistors 3.

Fig. 11 is a schematic diagram of driving waveforms of an array substrate according to a first embodiment of the present invention. As shown in fig. 11, in the display period, a high-level signal (for example, 15V) is applied to all control lines 1, the second thin film transistor 3 is controlled by the control lines 1 to electrically connect all the common electrode blocks 151 together, a 0V common voltage signal is applied to all the touch-control wirings 134, and the common electrode blocks 151 are used as integral common electrodes, so that the voltages of the common electrode blocks 151 at different positions are the same, and the problem of uneven display is avoided; the plurality of scan lines 111 sequentially apply a high-level signal (e.g., 15V) to sequentially scan the plurality of rows of pixel units SP, and gray-scale voltages (e.g., 0-5V) are applied to the data lines 131 to form different horizontal electric fields between the pixel electrodes 141 and the common electrode block 151 to display different pictures. In the touch time period, a low-level signal (for example, 0V) is applied to all control lines 1, the control lines 1 control the second thin film transistors 3 to disconnect all the common electrode blocks 151 from each other, and a touch signal is applied to all the touch wires 134, so that the common electrode blocks 151 are used as touch electrodes, and a touch function is realized; no voltage is applied to both the scan line 111 and the data line 131. Each frame time can be provided with a plurality of display time periods and a plurality of touch time periods, each frame time is overlapped by patterns displayed in the plurality of display time periods, and touch signals are refreshed for a plurality of times in each frame time, so that the touch effect is improved. In each frame time, a blank time period is further provided, and in the blank time period, no voltage is applied to the control line 1, the touch control wiring 134, the scanning line 111 and the data line 131, so that a reset effect is achieved, and interference between touch control and displayed pictures in two adjacent pin time is avoided.

Fig. 12-1 to 16-3 are schematic structural views of a method for manufacturing an array substrate according to a first embodiment of the invention.

Wherein, fig. 12-1, fig. 13-1, fig. 14-1, fig. 15-1, fig. 16-1 are schematic plan view of the array substrate, fig. 12-2, fig. 13-2, fig. 14-2, fig. 15-2, fig. 16-2 are schematic cross-sectional views of the array substrate along the direction A-A in fig. 7, and fig. 12-3, fig. 13-3, fig. 14-3, fig. 15-3, fig. 16-3 are schematic cross-sectional views of the array substrate along the direction B-B in fig. 7. As shown in fig. 12-1 to 16-3, a method for manufacturing an array substrate is also provided in this embodiment, where the method is used to manufacture the array substrate as described above. The manufacturing method comprises the following steps:

as shown in fig. 12-1 to 12-3, a substrate 10 is provided. The substrate 10 may be made of glass, quartz, silicon, acrylic or polycarbonate, etc., and the substrate 10 may also be a flexible substrate, with suitable materials for the flexible substrate including, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinylchloride (PVC), polyethylene terephthalate (PET), or combinations thereof.

A first metal layer 11 is formed over the substrate 10, the first metal layer 11 being provided directly on the upper surface of the substrate 10. The first metal layer 11 is etched by using a first masking process, the first metal layer 11 forms a patterned scan line 111, a first gate 112, a first section of control line 113 and a second gate 114, the first gate 112 is electrically connected to the scan line 111, the second gate 114 is electrically connected to the first section of control line 113, the first section of control line 113 is disconnected in a region crossing the scan line 111, the first section of control line 113 is perpendicular to the extending direction of the scan line 111, and a certain distance is provided between the first section of control line 113 and the scan line 111 to prevent the first section of control line 113 from shorting with the scan line 111. In this embodiment, the first gate 112 is a branch electrode protruding from the scan line 111, and the second gate 114 is a part of the first control line 113, i.e. a part of the first control line 113 is used as the second gate 114, so as to avoid affecting the aperture ratio of the pixel. Of course, the first gate electrode 112 may be a part of the scan line 111, and a part of the scan line 111 may be the first gate electrode 112, thereby increasing the aperture ratio of the pixel. The first metal layer 11 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.

A first insulating layer 101 is formed over the first metal layer 11 to cover the scan lines 111, the gate electrodes 112, the first segment control lines 113, and the second gate electrodes 114, the first insulating layer 101 being directly provided on the upper surfaces of the substrate 10 and the first metal layer 11. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

As shown in fig. 13-1 to 13-3, a semiconductor layer 12 is formed over the first insulating layer 101, the semiconductor layer 12 is etched using a second masking process, the semiconductor layer 12 is formed with a first active layer 121 and a second active layer 122 patterned, the first active layer 121 corresponds to the first gate electrode 112, and the second active layer 122 corresponds to the second gate electrode 114. The projection of the second active layer 122 on the substrate 10 is located in the area of the first section control line 113, and the area of the first section control line 113 corresponding to the second active layer 122 is used as the second gate 114, so that the influence on the aperture ratio of the pixel is avoided. The material of the semiconductor layer 12 is amorphous silicon (a-Si) and doped amorphous silicon.

As shown in fig. 14-1 to 14-3, a second metal layer 13 is formed over the first insulating layer 101, and the second metal layer 13 is etched by a third masking process, where the second metal layer 13 forms a patterned data line 131, a first source 132, a first drain 133, a touch trace 134, a second segment control line 135, a second source 136, and a second drain 137. The data line 131 is electrically connected to the first source electrode 132, and the first source electrode 132 is electrically connected to the first drain electrode 133 through the first active layer 121. The second source electrode 136 and the second drain electrode 137 are electrically connected through the second active layer 122. The second segment control lines 135 cross the scan lines 111 and electrically connect the disconnected adjacent two first segment control lines 113 to form the control lines 1, and the plurality of first segment control lines 113 and the plurality of second segment control lines 135 are alternately arranged along the direction of the control lines 1. The first gate electrode 112, the first active layer 121, the first source electrode 132, and the first drain electrode 133 collectively form a first thin film transistor 2, and the first thin film transistor 2 is controlled by the scan line 111. The second gate electrode 114, the second active layer 122, the second source electrode 136, and the second drain electrode 137 together form a second thin film transistor 3, and the second thin film transistor 3 is controlled by the control line 1. The touch trace 134, the data line 131 and the control line 1 are arranged in parallel. The second metal layer 13 may be made of a metal such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or the like, or a combination of the above metals such as Al/Mo, cu/Mo, or the like.

In this embodiment, the second insulating layer 102 is formed above the second metal layer 13, and the second insulating layer 102 covers the first active layer 121, the second active layer 122, the data line 131, the first source 132, the first drain 133, the touch trace 134, the second segment control line 135, the second source 136 and the second drain 137. Etching the second insulating layer 102 by using a fourth masking process, wherein the second insulating layer 102 is provided with a first contact hole TH1 (fig. 14-2) in a region corresponding to the first drain electrode 133; the second insulating layer 102 is provided with a second contact hole TH2 (fig. 14-3) at an end region corresponding to the second-stage control line 135, and the first insulating layer 101 and the second insulating layer 102 are provided with a third contact hole TH3 (fig. 14-3) at an end region corresponding to the first-stage control line 113. The process step of forming the first contact holes TH1 in the region of the first drain electrode 133 by using the second insulating layer 102, and simultaneously forming the second contact holes TH2 in the end region of the second insulating layer 102 corresponding to the second segment control line 135, and forming the third contact holes TH3 in the end regions of the first insulating layer 101 and the second insulating layer 102 corresponding to the first segment control line 113, thereby eliminating the need to individually etch the first insulating layer 101 and reducing a masking process. The second insulating layer 102 may be a flat layer, and the material of the second insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

As shown in fig. 15-1 to 15-3, a first transparent conductive layer 14 is formed over the second insulating layer 102, the first transparent conductive layer 14 is etched by a fifth masking process, the first transparent conductive layer 14 is formed with a plurality of patterned pixel electrodes 141, the pixel electrodes 141 are electrically connected to the first drain electrodes 133 of the first thin film transistors 2, and the pixel electrodes 141 are electrically connected to the corresponding scan lines 111 and data lines 131 through the first thin film transistors 2. The pixel electrode 141 is electrically connected to the first drain electrode 133 of the first thin film transistor 2 through the first contact hole TH 1. The material of the first transparent conductive layer 14 is Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or the like.

In this embodiment, the first transparent conductive layer 14 further includes a bridging electrode 142, and the first segment control line 113 and the second segment control line 135 are electrically connected to each other through the bridging electrode 142. Wherein each bridge electrode 142 is electrically connected to the first segment control line 113 and the second segment control line 135 through the second contact hole TH2 and the third contact hole TH3, respectively. Of course, in other embodiments, the second insulating layer 102 may not be provided, and the first transparent conductive layer 14 may be directly covered on the second metal layer 13, so that the pixel electrode 141 is directly in conductive contact with the first drain electrode 133 of the first thin film transistor 2, one end of the bridge electrode 142 is directly in conductive contact with the second section control line 135, and the other end of the bridge electrode 142 is electrically connected with the first section control line 113 through a contact hole on the first insulating layer 101, so as to further simplify the structure and manufacturing process, and reduce the thickness and manufacturing cost of the array substrate.

A third insulating layer 103 is formed over the first transparent conductive layer 14, the third insulating layer 103 covering the pixel electrode 141 and the bridge electrode 142. The second insulating layer 102 and the third insulating layer 103 are etched simultaneously by using a sixth masking process, the second insulating layer 102 and the third insulating layer 103 are provided with fourth contact holes TH4 (fig. 15-2) in regions corresponding to the touch traces 134, and the second insulating layer 102 and the third insulating layer 103 are provided with fifth contact holes TH5 and sixth contact holes TH6 (fig. 15-3) in regions corresponding to the second source electrodes 136 and the second drain electrodes 137, respectively. The material of the third insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

As shown in fig. 16-1 to 16-3, a second transparent conductive layer 15 is formed above the second metal layer 13 and is insulated from the first transparent conductive layer 14, the second transparent conductive layer 15 is etched by a seventh masking process, the second transparent conductive layer 15 forms a plurality of patterned common electrode blocks 151, and each common electrode block 151 is electrically connected with a corresponding touch trace 134, so that a touch signal is applied to the common electrode block 151 in a touch time period, and a touch function is realized. All the common electrode blocks 151 are electrically connected to each other through a plurality of second thin film transistors 3, and each second thin film transistor 3 is connected to two adjacent common electrode blocks 151. Each common electrode block 151 is electrically connected to the corresponding touch trace 134 through a fourth contact hole TH4, and two adjacent common electrode blocks 151 are electrically connected to the corresponding second source 136 and second drain 137 of the same second thin film transistor 3 through a fifth contact hole TH5 and a sixth contact hole TH6, respectively, so that each second thin film transistor 3 is connected to two adjacent common electrode blocks 151. Therefore, in the display time period, the second thin film transistor 3 can be controlled by the control line 1 to electrically connect all the common electrode blocks 151 together, so that the common electrode blocks 151 at different positions are ensured to have the same voltage, and the problem of uneven display is avoided; in the touch time period, the control line 1 can control the second thin film transistor 3 to disconnect all the common electrode blocks 151 from each other, so that the common electrode blocks are used as touch electrodes, and a touch function is realized. The material of the second transparent conductive layer 15 is Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or the like.

In this embodiment, the first transparent conductive layer 14 is disposed below the second transparent conductive layer 15, that is, the pixel electrode 141 is disposed below the common electrode block 151, the pixel electrode 141 is a block electrode corresponding to the pixel unit SP (fig. 6), the common electrode block 151 is a comb-shaped electrode with slits in a region corresponding to the pixel unit SP, and each common electrode block 151 may cover a plurality of pixel units SP.

Further, the second transparent conductive layer 15 further includes a conductive portion 152 electrically connected to the common electrode block 151, and since some common electrode blocks 151 need to be connected to the plurality of second thin film transistors 3, the common electrode block 151 may be electrically connected to the corresponding plurality of second thin film transistors 3 through the plurality of conductive portions 152.

Example two

Fig. 17 is a schematic plan view of an enlarged structure of an array substrate according to a second embodiment of the present invention. Fig. 18 is a schematic cross-sectional view of the array substrate along the direction C-C in fig. 17 in the second embodiment of the present invention. As shown in fig. 17 and 18, the array substrate and the manufacturing method provided in the second embodiment of the present invention are substantially the same as those in the first embodiment (fig. 3 to 5), except that in the present embodiment:

The plurality of second thin film transistors 3 correspond to the same first section of control line 113, and the plurality of second thin film transistors 3 corresponding to the same first section of control line 113 are connected in a conductive manner. By arranging the plurality of second thin film transistors 3 in the area corresponding to part of the first-stage control lines 113, the plurality of second thin film transistors 3 corresponding to the same first-stage control line 113 are connected in series, so that the area corresponding to the same first-stage control line 113 can electrically connect more than three common electrode blocks 151 together.

As shown in fig. 17 and 18, the two second thin film transistors 3 correspond to the same first stage control line 113, and one of the second source 136 and the second drain 137 of the two second thin film transistors 3 corresponding to the same first stage control line 113 is electrically connected so that the two second thin film transistors 3 have three contact points to be connected to the three common electrode blocks 151, respectively, whereby the conductive portion 152 of a part of the common electrode blocks 151 can be shortened, so that the conductivity between the adjacent four common electrode blocks 151 is better. Of course, in other embodiments, three second thin film transistors 3 may correspond to the same first segment control line 113, so that the area corresponding to the same first segment control line 113 has four contact points to connect to the four common electrode blocks 151 respectively.

Those skilled in the art will understand that the other structures and working principles of the present embodiment are the same as those of the first embodiment, and will not be described herein.

Fig. 19 is a schematic cross-sectional structure of the display device in the dark state in the present invention. Fig. 20 is a schematic cross-sectional view of the display device of the present invention in a bright state. As shown in fig. 19 and 20, the present application further provides an in-cell touch display panel, which includes the array substrate as described above. The display panel comprises a color film substrate 20 arranged opposite to the array substrate and a liquid crystal layer 30 arranged between the array substrate and the color film substrate 20, wherein an upper polaroid 41 is arranged on the color film substrate 20, a lower polaroid 42 is arranged on the array substrate, and the light transmission axis of the upper polaroid 41 is mutually perpendicular to the light transmission axis of the lower polaroid 42. The liquid crystal molecules in the liquid crystal layer 30 are positive liquid crystal molecules (liquid crystal molecules with positive dielectric anisotropy), and in the initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the color film substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules close to the array substrate. It is understood that the array substrate and the color film substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, so as to align the positive liquid crystal molecules in the liquid crystal layer 30.

In this embodiment, the color film substrate 20 is provided with a black matrix 21 and a color resist layer 22, the black matrix 21 corresponds to the scan lines 111, the control lines 1, the data lines 131, the touch traces 134, the first thin film transistor 2, the second thin film transistor 3 and the peripheral non-display area, and the black matrix 21 separates the color resist layers 22. The color resist layer 22 includes red (R), green (G), and blue (B) color resist materials, and corresponds to the sub-pixels forming the three colors red (R), green (G), and blue (B).

As shown in fig. 19 and 20, the present invention further provides a display device, including the in-cell touch display panel and the backlight module 50, wherein the backlight module 50 is located below the in-cell touch display panel for providing a backlight source for the display panel.

The backlight module 50 includes a backlight source 51 and a peep-proof layer 52, and the peep-proof layer 52 is used for reducing the range of the light emitting angle. A brightness enhancement film 53 is further disposed between the backlight source 51 and the peep-proof layer 52, and the brightness enhancement film 53 increases the brightness of the backlight module 50. The peep-proof layer 52 is a micro shutter structure, which can block light with a larger incident angle, so that light with a smaller incident angle passes through the shutter structure, and the angle range of the light passing through the peep-proof layer 52 is reduced. The peep-proof layer 52 includes a plurality of parallel light-resisting walls and light holes between two adjacent light-resisting walls, and two sides of the light-resisting walls are provided with light-absorbing materials. Of course, the backlight 51 may be a light-collecting type backlight, so that the peep-proof layer 52 is not required, but the light-collecting type backlight is more expensive than the conventional backlight.

The backlight module 50 may be a side-in type backlight module or a direct type backlight module. Preferably, the backlight module 50 adopts a collimated backlight (CBL, collimated backlight) mode, which can collect light to ensure display effect.

In this document, terms such as up, down, left, right, front, rear, etc. are defined by the positions of the structures in the drawings and the positions of the structures with respect to each other, for the sake of clarity and convenience in expressing the technical solution. It should be understood that the use of such orientation terms should not limit the scope of the protection sought herein. It should also be understood that the terms "first" and "second," etc., as used herein, are used merely for distinguishing between names and not for limiting the number and order.

The present invention is not limited to the preferred embodiments, but is capable of modification and variation in detail, and other modifications and variations can be made by those skilled in the art without departing from the scope of the present invention.

Claims

1. An array substrate, characterized by comprising:

a substrate (10);

a first metal layer (11) arranged above the substrate (10), wherein the first metal layer (11) comprises a scanning line (111), a first grid electrode (112), a first section control line (113) and a second grid electrode (114), the first grid electrode (112) is electrically connected with the scanning line (111), the second grid electrode (114) is electrically connected with the first section control line (113), and the first section control line (113) is disconnected in a region which is mutually intersected with the scanning line (111);

a first insulating layer (101) disposed above the first metal layer (11), the first insulating layer (101) covering the scan line (111), the first gate (112), the first segment control line (113), and the second gate (114);

a semiconductor layer (12) provided above the first insulating layer (101), the semiconductor layer (12) including a first active layer (121) corresponding to the first gate electrode (112) and a second active layer (122) corresponding to the second gate electrode (114);

a second metal layer (13) disposed above the first insulating layer (101), the second metal layer (13) including a data line (131), a first source (132), a first drain (133), a touch trace (134), a second segment control line (135), a second source (136) and a second drain (137), the data line (131) being electrically connected to the first source (132), the first source (132) being electrically connected to the first drain (133) through the first active layer (121), the second source (136) being electrically connected to the second drain (137) through the second active layer (122), the second segment control line (135) crossing the scan line (111) and electrically connecting two adjacent segments of the first segment control line (113) being disconnected to form a control line (1), the first gate (112), the first active layer (121), the first source (132) and the first drain (133) being electrically connected to each other through the first active layer (121), the second source (136) and the second drain (137) being electrically connected to each other through the second active layer (122), the second gate (135) being electrically connected to each other through the second active layer (122), the second thin film transistor (3) is controlled by the control line (1), and the touch trace (134), the data line (131) and the control line (1) are arranged in parallel;

The first transparent conductive layer (14) is arranged above the second metal layer (13), the first transparent conductive layer (14) comprises a plurality of pixel electrodes (141), and the pixel electrodes (141) are electrically connected with the corresponding scanning lines (111) and the data lines (131) through the first thin film transistors (2);

the second transparent conductive layer (15) is arranged above the second metal layer (13) and is mutually insulated and spaced from the first transparent conductive layer (14), the second transparent conductive layer (15) comprises a plurality of common electrode blocks (151), each common electrode block (151) is electrically connected with a corresponding touch wiring (134), all the common electrode blocks (151) are mutually electrically connected through a plurality of second thin film transistors (3), and a second source electrode (136) and a second drain electrode (137) of each second thin film transistor (3) are respectively connected with two adjacent common electrode blocks (151).

2. The array substrate of claim 1, wherein the array substrate comprises:

the second insulating layer (102) is arranged above the second metal layer (13), and the second insulating layer (102) covers the first active layer (121), the second active layer (122), the data line (131), the first source electrode (132), the first drain electrode (133), the touch control wiring (134), the second section control line (135), the second source electrode (136) and the second drain electrode (137);

The first transparent conductive layer (14) and the second transparent conductive layer (15) are both arranged above the second insulating layer (102);

and a third insulating layer (103) disposed between the first transparent conductive layer (14) and the second transparent conductive layer (15), the first transparent conductive layer (14) and the second transparent conductive layer (15) being insulated and spaced apart from each other by the third insulating layer (103).

3. The array substrate according to claim 1, wherein the first transparent conductive layer (14) is disposed below the second transparent conductive layer (15), the first transparent conductive layer (14) further comprises a bridge electrode (142), and the first section control line (113) and the second section control line (135) are electrically connected to each other through the bridge electrode (142);

or, the second transparent conductive layer (15) is disposed below the first transparent conductive layer (14), the second transparent conductive layer (15) further includes a bridging electrode (142), and the first section control line (113) and the second section control line (135) are electrically connected to each other through the bridging electrode (142).

4. The array substrate according to claim 1, wherein each of the control lines (1) controls a plurality of the second thin film transistors (3);

Adjacent four common electrode blocks (151) are electrically connected with each other through four second thin film transistors (3); or the adjacent four common electrode blocks (151) are electrically connected with each other through the three second thin film transistors (3).

5. The array substrate according to claim 1, wherein a plurality of the second thin film transistors (3) correspond to the same first segment control line (113), and a plurality of the second thin film transistors (3) corresponding to the same first segment control line (113) are electrically connected to each other;

or, the projection of the second active layer (122) on the substrate (10) is located in the area of the first section control line (113), and the area of the first section control line (113) corresponding to the second active layer (122) is used as the second grid electrode (114).

6. An embedded touch display panel, comprising an array substrate, a color film substrate (20) arranged opposite to the array substrate, and a liquid crystal layer (30) arranged between the array substrate and the color film substrate (20), wherein the array substrate is an array substrate according to any one of claims 1-5.

7. The manufacturing method of the array substrate is characterized by comprising the following steps of:

Providing a substrate (10);

forming a first metal layer (11) above the substrate (10), etching the first metal layer (11), forming a patterned scanning line (111), a first grid electrode (112), a first section control line (113) and a second grid electrode (114) on the first metal layer (11), wherein the first grid electrode (112) is electrically connected with the scanning line (111), the second grid electrode (114) is electrically connected with the first section control line (113), and the first section control line (113) is disconnected in a region which is mutually intersected with the scanning line (111);

forming a first insulating layer (101) covering the scanning line (111), the gate electrode (112), the first segment control line (113), and the second gate electrode (114) over the first metal layer (11);

forming a semiconductor layer (12) above the first insulating layer (101), etching the semiconductor layer (12), forming a patterned first active layer (121) and a patterned second active layer (122) on the semiconductor layer (12), wherein the first active layer (121) corresponds to the first gate (112), and the second active layer (122) corresponds to the second gate (114);

forming a second metal layer (13) above the first insulating layer (101), etching the second metal layer (13), forming a patterned data line (131), a first source electrode (132), a first drain electrode (133), a touch trace (134), a second control line (135), a second source electrode (136) and a second drain electrode (137) on the second metal layer (13), wherein the data line (131) is electrically connected with the first source electrode (132), the first source electrode (132) is electrically connected with the first drain electrode (133) through the first active layer (121), the second source electrode (136) is electrically connected with the second drain electrode (137) through the second active layer (122), the second control line (135) spans the scanning line (111) and electrically connects two disconnected adjacent first control lines (113) to form a control line (1), the first gate electrode (112), the first active layer (121), the first source electrode (132) and the second source electrode (132) are electrically connected with the second drain electrode (137) through the second active layer (122), the first gate electrode (114), the first gate electrode (2) is formed by a thin film (2), and the second gate electrode (122) is formed by the thin film (2) The second source electrode (136) and the second drain electrode (137) together form a second thin film transistor (3), the second thin film transistor (3) is controlled by the control line (1), and the touch trace (134), the data line (131) and the control line (1) are arranged in parallel;

Forming a first transparent conductive layer (14) above the second metal layer (13), etching the first transparent conductive layer (14), forming a plurality of patterned pixel electrodes (141) on the first transparent conductive layer (14), wherein the pixel electrodes (141) are electrically connected with the corresponding scanning lines (111) and the data lines (131) through the first thin film transistors (2);

and forming a second transparent conductive layer (15) which is mutually insulated and spaced from the first transparent conductive layer (14) above the second metal layer (13), etching the second transparent conductive layer (15), forming a plurality of patterned public electrode blocks (151) on the second transparent conductive layer (15), wherein each public electrode block (151) is electrically connected with a corresponding touch wire (134), all the public electrode blocks (151) are mutually electrically connected through a plurality of second thin film transistors (3), and each second thin film transistor (3) is connected with two adjacent public electrode blocks (151).

8. The method for manufacturing an array substrate according to claim 7, comprising:

forming a second insulating layer (102) covering the first active layer (121), the second active layer (122), the data line (131), the first source electrode (132), the first drain electrode (133), the touch trace (134), the second segment control line (135), the second source electrode (136) and the second drain electrode (137) over the second metal layer (13);

9. The method for manufacturing an array substrate according to claim 7, wherein the first transparent conductive layer (14) is disposed below the second transparent conductive layer (15), the first transparent conductive layer (14) further forms a patterned bridging electrode (142), and the first section control line (113) and the second section control line (135) are electrically connected to each other through the bridging electrode (142);

or, the second transparent conductive layer (15) is disposed below the first transparent conductive layer (14), the second transparent conductive layer (15) further forms a patterned bridging electrode (142), and the first section control line (113) and the second section control line (135) are electrically connected with each other through the bridging electrode (142).

10. The method for manufacturing the array substrate according to claim 7, wherein each control line (1) controls a plurality of the second thin film transistors (3);

Adjacent four common electrode blocks (151) are electrically connected with each other through four second thin film transistors (3); or the adjacent four common electrode blocks (151) are electrically connected with each other through three second thin film transistors (3);

the second thin film transistors (3) correspond to the same first section control line (113), and the second thin film transistors (3) corresponding to the same first section control line (113) are connected in a conductive mode.