CN117579049A - Power-on reset circuit - Google Patents
Power-on reset circuit Download PDFInfo
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- CN117579049A CN117579049A CN202311551004.4A CN202311551004A CN117579049A CN 117579049 A CN117579049 A CN 117579049A CN 202311551004 A CN202311551004 A CN 202311551004A CN 117579049 A CN117579049 A CN 117579049A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention provides a power-on reset circuit, which comprises a voltage sampling module, an inversion module and an output pull-up module, wherein the sampling voltage input by the inversion module is obtained by sampling the power supply voltage by the voltage sampling module in a resistance way, is always synchronous with the power supply voltage, is not sampled by charging a large capacitor, does not need to match the capacitance value of the large capacitor with the turning point of a reset signal and the power-on waveform of the power supply voltage, can effectively avoid the condition that the turning point of the reset signal fluctuates along with the change of the power-on waveform of the power supply voltage, and reduces the design difficulty, the volume and the power consumption of the power-on reset circuit; the temperature coefficient of the output sampling signal is zero through the cooperation of the temperature coefficients among the sampling resistors in the voltage sampling module, and the output reset signal and the turning point of the reset signal do not drift along with the temperature by combining the pull-down resistor outputting the zero temperature coefficient in the pull-up module, so that the temperature stability of the reset signal is improved.
Description
Technical Field
The invention relates to the technical field of wireless communication, in particular to a power-on reset circuit.
Background
The power-on reset circuit is used for detecting a power supply voltage and outputting a reset signal, and is widely applied to various electronic circuits. The conventional power-on reset circuit realizes the delay output of the reset signal in a mode of charging the large capacitor by small current, and has great difference in delay time of the reset signal of the conventional power-on reset circuit under different temperatures, power supply voltages and power supply voltage power waveforms, so that the power supply voltage cannot be accurately detected and the reset signal cannot be accurately output.
Therefore, a power-on reset technical scheme is needed that the output reset signal is hardly affected by the power-on waveform of the temperature and the power supply voltage.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a power-on reset circuit, which is used for solving the problem that the conventional power-on reset circuit cannot accurately detect the power supply voltage and the output reset signal is greatly affected by the temperature and the power-on waveform of the power supply voltage.
In order to achieve the above object and other related objects, the present invention provides the following technical solutions.
A power-on reset circuit, comprising:
the voltage sampling module is connected with a power supply voltage, and is started when the power supply voltage is greater than or equal to a first threshold value, and resistance sampling is carried out on the power supply voltage to obtain a sampling signal;
the positive power supply is connected with the power supply voltage, the negative power supply is connected with the ground, the input end of the negative power supply is connected with the sampling signal, and the sampling signal is subjected to inversion processing to obtain a control signal;
the positive power supply is connected with the power supply voltage, the negative power supply is connected with the control signal, and the output reset signal is subjected to pull-up processing under the control of the control signal;
when the power supply voltage is powered on, the power supply voltage gradually increases from zero, when the power supply voltage is smaller than a second threshold value, the sampling signal does not reach the turnover threshold value, the reset signal is pulled down to the ground potential, when the power supply voltage is larger than or equal to the second threshold value, the sampling signal reaches the turnover threshold value, the control signal turns over, so that the reset signal is pulled up to the power supply voltage from the ground potential, and the second threshold value is larger than the first threshold value.
Optionally, when the power supply voltage is smaller than the first threshold value, the voltage sampling module is kept off, the sampling signal is zero, the control signal is the power supply voltage, and the reset signal is pulled down to the ground potential.
Optionally, when the power supply voltage is greater than or equal to the first threshold and less than the second threshold, the voltage sampling module starts, the sampling signal gradually increases from zero, but the sampling signal does not reach the inversion threshold, the control signal is still the power supply voltage, and the reset signal is pulled down to the ground potential.
Optionally, when the power supply voltage is greater than or equal to the second threshold, the voltage sampling module starts, the sampling signal increases to the inversion threshold, and the control signal is inverted from the power supply voltage to the ground potential, so that the reset signal is pulled up from the ground potential to the power supply voltage.
Optionally, the voltage sampling module includes a first PMOS tube, a second PMOS tube, n diodes, a first resistor and a second resistor, where a source electrode of the first PMOS tube is connected to the power supply voltage, a gate electrode of the first PMOS tube is connected to a drain electrode of the first PMOS tube, a drain electrode of the first PMOS tube is connected to an anode of a first diode, a cathode of an ith diode is connected to an anode of an (i+1) th diode, a cathode of the nth diode is connected to ground after being connected to the first resistor in series, a source electrode of the second PMOS tube is connected to the power supply voltage, a gate electrode of the second PMOS tube is connected to a drain electrode of the first PMOS tube, a drain electrode of the second PMOS tube is connected to ground after being connected to the second resistor in series, and a drain electrode of the second PMOS tube outputs the sampling signal; wherein n is an integer equal to or greater than 1, and i is an integer from 1 to n-1.
Optionally, the inverting module includes a third PMOS transistor and a first NMOS transistor, where a source of the third PMOS transistor is connected to the power supply voltage, a gate of the third PMOS transistor is connected to the sampling signal, a drain of the third PMOS transistor is connected to a drain of the first NMOS transistor, a gate of the first NMOS transistor is connected to a gate of the third PMOS transistor, a source of the first NMOS transistor is grounded, and a drain of the first NMOS transistor outputs the control signal.
Optionally, the output pull-up module includes a fourth PMOS transistor and a third resistor, where a source of the fourth PMOS transistor is connected to the power supply voltage, a gate of the fourth PMOS transistor is connected to the control signal, a drain of the fourth PMOS transistor is connected to the ground after passing through the third resistor in series, and a drain of the fourth PMOS transistor outputs the reset signal.
Optionally, the first resistor is a positive temperature coefficient resistor, the second resistor is a negative temperature coefficient resistor, and the temperature coefficient of the first resistor is matched with the temperature coefficient of the second resistor, so that the temperature coefficient of the sampling signal is zero; the third resistor is a zero temperature coefficient resistor.
Optionally, the value of the second threshold is related to the value of the first threshold, the resistance of the first resistor, the resistance of the second resistor, and the value of the flip threshold.
Optionally, the power-on reset circuit further includes:
and when the sampling signal reaches the turnover threshold value, the control signal is turned over to the ground potential by the power voltage, and the positive feedback module is started to pull up the sampling signal to the power voltage.
Optionally, the positive feedback module includes a fifth PMOS transistor, a source electrode of the fifth PMOS transistor is connected to the power supply voltage, a gate electrode of the fifth PMOS transistor is connected to the control signal, and a drain electrode of the fifth PMOS transistor is connected to the sampling signal.
As described above, the power-on reset circuit of the present invention has at least the following advantages:
the power-on reset circuit is designed by combining the voltage sampling module, the inverting module and the output pull-up module, zero is gradually increased when the power supply voltage is powered on, the voltage sampling module is started when the power supply voltage is larger than or equal to a first threshold value, resistance sampling is carried out on the power supply voltage to obtain a sampling signal, when the power supply voltage is smaller than a second threshold value, the sampling signal does not reach the inversion threshold value, the reset signal is pulled down to the ground potential, when the power supply voltage is larger than or equal to the second threshold value, the sampling signal reaches the inversion threshold value, the control signal is inverted, the reset signal is pulled up to the power supply voltage by the ground potential, the sampling voltage is completely determined by resistance sampling, the sampling voltage is always synchronous with the power supply voltage, the second threshold value for determining inversion of the reset signal is fixed, namely the inversion point of the finally output reset signal is fixed.
Drawings
Fig. 1 shows a circuit diagram of a conventional power-on reset circuit.
FIG. 2 is a circuit diagram of a power-on reset circuit according to the present invention.
FIG. 3 shows the reset signal V at-40℃for the power-on reset circuit of the present invention REST Simulation test curves as a function of supply voltage VCC.
FIG. 4 shows a reset signal V at +25deg.C for a power-on reset circuit according to the present invention REST Simulation test curves as a function of supply voltage VCC.
FIG. 5 shows a reset signal V at +85℃fora power-on reset circuit according to the present invention REST Simulation test curves as a function of supply voltage VCC.
Fig. 6 shows a simulation test curve of the quiescent current of the power-on reset circuit according to the present invention as a function of the supply voltage VCC in the range of 2V to 5V.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 6. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex. The structures, proportions, sizes, etc. shown in the drawings attached hereto are for illustration purposes only and are not intended to limit the scope of the invention, which is defined by the claims, but rather by the claims.
As described in the foregoing background art, the inventors have studied and found that, as shown in fig. 1, the conventional power-on reset circuit realizes the delayed output of the reset signal by charging the large capacitor with a small current, and under the power-on waveforms of different temperatures, power voltages and power voltages, the delay time of the reset signal of the conventional power-on reset circuit has a very large difference, so that it is impossible to accurately detect the power voltage and accurately output the reset signal.
In detail, as shown in FIG. 1, the conventional power-on reset circuit comprises PMOS transistors PM1 to PM4 and NMOS transistor NM1NM2, resistance R01 and electric capacity C1, PMOS pipe PM1 and resistance R01 constitute the current source, produce a low current, simultaneously, PMOS pipe PM1 and PMOS pipe PM2 constitute the current mirror, and the electric current of the branch road that PMOS pipe PM2 is located copies PMOS pipe PM1, charges electric capacity C1, and power supply voltage VCC begins to rise from 0V, and the sampling voltage at node a also rises along with electric capacity C1's charging. When the sampling voltage at the node a reaches the threshold voltage of the first inverter (the first inverter is composed of the PMOS pipe PM3 and the NMOS pipe NM1, and the second inverter is composed of the PMOS pipe PM4 and the NMOS pipe NM 2) in the later cascade, the output voltage of the first inverter composed of the PMOS pipe PM3 and the NMOS pipe NM1 is turned over, and the output voltage of the second inverter composed of the PMOS pipe PM4 and the NMOS pipe NM2 is turned over, namely the reset signal V REST Is pulled up from ground to the supply voltage VCC.
The first inverter formed by the PMOS transistor PM3 and the NMOS transistor NM1 can normally operate at 0.6V or more, and the digital baseband circuit needs to be 1.2V or more. The time for the power supply voltage VCC to rise from 0V to the normal operating voltage is typically on the order of μs to ms. Therefore, in order to make the power supply voltage VCC reach 1.2V or higher and then the power-on reset circuit outputs the reset signal Vrest, the capacitance of the capacitor C1 needs to take a large value, so that the sampling voltage at the node a slowly rises, the time reaches ms level, and the sampling voltage at the node a is charged to the threshold voltage at which the first inverter is turned over after waiting for the power supply voltage VCC to reach 1.2V or higher.
However, the conventional power-on reset circuit as shown in fig. 1 has at least several drawbacks:
1) The capacitance value of the capacitor C1 is larger, so that the area or the volume of the whole power-on reset circuit is larger;
2) In some cases, the power-up time of the power supply voltage VCC may be tens of milliseconds or longer, at this time, the sampling voltage at the node a will always follow the power supply voltage VCC, and when the power supply voltage VCC is 0.6V, the first inverter will start to operate, flip, and output the reset signal V REST In this case, reset signal V REST The lower turning point of the power-on reset circuit can cause the rear baseband circuit to be unable to reset, so that the conventional power-on reset circuit is sensitive to the power-on waveform of the power supply voltage VCC, and the conventional power-on reset circuit can not work normally when the power-on waveform of the power supply voltage VCC is too slow;
3) The rising time of the sampling voltage at the node a in the conventional power-on reset circuit is determined by the current of the branch where the PMOS tube PM1 is located, and under different temperatures, the current of the branch where the PMOS tube PM1 is located changes greatly, so that the rising time of the sampling voltage at the node a changes greatly, the rising waveform of the power supply voltage VCC is basically unchanged along with the temperature, and the delay of the sampling voltage at the node a under different temperatures is different, so that the reset signal V output by the conventional power-on reset circuit under different temperatures can be caused REST Different.
Based on the above, the invention provides a power-on reset technical scheme: the power-on reset circuit is designed by combining the voltage sampling module, the inverting module and the output pull-up module, the sampling voltage input by the inverting module is obtained by carrying out resistance sampling on the power supply voltage by the voltage sampling module, the sampling voltage is completely determined by resistance sampling, and is always synchronous with the power supply voltage, so that the mode of sampling by charging a large capacitor in the traditional scheme is not needed, the capacitance value of the large capacitor is not needed to be matched with the turning point of a reset signal and the power-on waveform of the power supply voltage, the condition that the turning point of the reset signal fluctuates along with the change of the power-on waveform of the power supply voltage is avoided, and the design difficulty, the volume and the power consumption of the power-on reset circuit are reduced; the temperature coefficients of different branch sampling resistors in the voltage sampling module are matched so that the temperature coefficient of an output sampling signal is zero, and the output reset signal and the turning point of the reset signal do not drift along with the temperature by combining with a pull-down resistor outputting the zero temperature coefficient in the pull-up module; meanwhile, a positive feedback module is introduced between the input end and the output end of the inverting module, and the inverting state of the inverting module is maintained and locked through the positive feedback module, so that the stability of the inverting state of the inverting module is improved.
As shown in fig. 2, the present invention provides a power-on reset circuit, which includes:
the voltage sampling module is used for sampling the voltage,the power supply voltage VCC is connected, when the power supply voltage VCC is larger than or equal to a first threshold value, the power supply voltage VCC is started, and resistance sampling is carried out on the power supply voltage VCC to obtain a sampling signal V S ；
The positive power supply is connected with the power supply voltage VCC, the negative power supply is connected with the GND, and the input end of the negative power supply is connected with the sampling signal V S For the sampling signal V S Performing inversion processing to obtain control signal V C ；
The output pull-up module has positive power supply connected to the power supply voltage VCC, negative power supply connected to GND, and input connected to control signal V C In the control signal V C Under control of (a) the output reset signal V REST Carrying out pull-up treatment;
wherein the power supply voltage VCC is gradually increased from zero when the power supply voltage VCC is powered on, and the sampling signal V when the power supply voltage VCC is smaller than the second threshold value S The inversion threshold is not reached, the reset signal V REST Pulled down to ground potential by ground GND, when the supply voltage VCC is greater than or equal to the second threshold value, the signal V is sampled S Reaching the threshold value of turning over, the control signal V C Flip occurs such that the reset signal V REST The ground potential is pulled up to the supply voltage VCC, and the second threshold is greater than the first threshold.
In detail, as shown in fig. 2, the voltage sampling module includes a first PMOS transistor P1, a second PMOS transistor P2, n diodes D1-Dn, a first resistor R1 and a second resistor R2, the source of the first PMOS transistor P1 is connected to a power supply voltage VCC, the gate of the first PMOS transistor P1 is connected to the drain of the first PMOS transistor P1, the drain of the first PMOS transistor P1 is connected to the anode of the first diode D1, the cathode of the ith diode Di is connected to the anode of the (i+1) th diode di+1, the cathode of the nth diode Dn is connected to the ground GND after being connected to the first resistor R1 in series, the source of the second PMOS transistor P2 is connected to the power supply voltage VCC, the gate of the second PMOS transistor P2 is connected to the drain of the first PMOS transistor P1 in series, the drain of the second PMOS transistor P2 is connected to the ground GND after being connected to the second resistor R2 in series, and the drain of the second PMOS transistor P2 outputs a sampling signal V S The method comprises the steps of carrying out a first treatment on the surface of the Wherein n is an integer equal to or greater than 1, and i is an integer from 1 to n-1.
More specifically, as shown in FIG. 2, the first PMOS transistor P1, the n diodes D1-Dn and the first resistor R1 form a voltage detection branch circuit, and the first PMThreshold voltage V of OS tube P1 GS(th) Threshold voltage V with n diodes D1-Dn th When the power supply voltage VCC is greater than or equal to the first threshold, the voltage detection branch is turned on, the remaining part of the power supply voltage VCC minus the first threshold is applied to both ends of the first resistor R1, and a current is generated in the first resistor R1 through voltage-current conversion of the first resistor R1, and the current is also a current flowing through the voltage detection branch. When the voltage detection branch is turned on, the second PMOS transistor P2 is turned on, the current mirror formed by the first PMOS transistor P1 and the second PMOS transistor P2 is turned on, the second PMOS transistor P2 copies the current on the voltage detection branch to obtain a copy current, and the copy current is subjected to current-voltage conversion through the second resistor R2 to obtain a sampling signal V at the drain (or node a) of the second PMOS transistor P2 S Sampling signal V S Starting from 0V.
The diodes D1 to Dn are in a series structure, the first threshold value can be flexibly adjusted by adjusting the number of the series diodes, namely, the starting voltage of the voltage detection branch or the voltage sampling module can be flexibly adjusted by adjusting the number of the series diodes, and at least one diode is arranged in the voltage detection branch.
It should be noted that, only when the power supply voltage VCC is greater than or equal to the first threshold, the voltage detection branch or the voltage sampling module may be started to perform resistance sampling on the power supply voltage VCC to obtain the sampling signal V S The method comprises the steps of carrying out a first treatment on the surface of the When the power supply voltage VCC is smaller than the first threshold value, the voltage detection branch or the voltage sampling module is closed to sample the signal V S Is pulled down to ground potential (0V) by the second resistor R2 by ground GND.
In detail, as shown in fig. 2, the inverting module includes a third PMOS transistor P3 and a first NMOS transistor N1, the source of the third PMOS transistor P3 is connected to the power supply voltage VCC, and the gate of the third PMOS transistor P3 is connected to the sampling signal V S The drain electrode of the third PMOS tube P3 is connected with the drain electrode of the first NMOS tube N1, the grid electrode of the first NMOS tube N1 is connected with the grid electrode of the third PMOS tube P3, the source electrode of the first NMOS tube N1 is grounded GND, and the drain electrode of the first NMOS tube N1 outputs a control signal V C 。
In more detail, as shown in FIG. 2The third PMOS transistor P3 and the first NMOS transistor N1 form a CMOS inverter, and the signal V is sampled S When the threshold value is smaller than the inversion threshold value, the third PMOS tube P3 is turned on, the first NMOS tube N1 is turned off, and the signal V is controlled C Is pulled up to the supply voltage VCC; when sampling signal V S When the threshold value is greater than or equal to the turnover threshold value, the third PMOS tube P3 is turned off, the first NMOS tube N1 is turned on, and the signal V is controlled C Is pulled down to ground potential by ground GND.
In detail, as shown in fig. 2, the output pull-up module includes a fourth PMOS transistor P4 and a third resistor R3, the source of the fourth PMOS transistor P4 is connected to the power supply voltage VCC, and the gate of the fourth PMOS transistor P4 is connected to the control signal V C The drain electrode of the fourth PMOS tube P4 is grounded GND after passing through the third resistor R3 connected in series, and the drain electrode of the fourth PMOS tube P4 outputs a reset signal V REST 。
In more detail, as shown in FIG. 2, when the control signal V C When the power supply voltage VCC is applied, the fourth PMOS transistor P4 is turned off and the reset signal V REST Pulled down to ground potential (0V) by ground GND through third resistor R3; when the control signal V C When the potential is ground, the fourth PMOS tube P4 is turned on, and the reset signal V REST Is pulled up to the supply voltage VCC.
In detail, as shown in fig. 2, the power-on reset circuit further includes:
the positive feedback module is connected with the control signal V at the input end C The output end is connected with the sampling signal V S According to the control signal V C For the sampling signal V S Perform feedback maintenance when sampling signal V S When the threshold value is smaller than the turnover threshold value, the control signal V C For the supply voltage VCC, the positive feedback module remains off, when the sampling signal V S When the overturn threshold is reached, the control signal V C The power supply voltage VCC is turned to the ground potential, the positive feedback module is started to sample the signal V S Up to the supply voltage VCC.
In more detail, as shown in FIG. 2, the positive feedback module includes a fifth PMOS transistor P5, the source of the fifth PMOS transistor P5 is connected to the power supply voltage VCC, and the gate of the fifth PMOS transistor P5 is connected to the control signal V C (or node b), the drain electrode of the fifth PMOS tube is connected with the sampling signal V S 。
At the same time, it is emphasized thatThe first resistor R1 is a positive temperature coefficient resistor, the second resistor R2 is a negative temperature coefficient resistor, and the temperature coefficient of the first resistor R1 is matched with the temperature coefficient of the second resistor R2 so as to enable the sampling signal V S The temperature coefficient of (2) is zero; the third resistor R3 is a zero temperature coefficient resistor.
In more detail, the power-on reset circuit as shown in fig. 2 operates as follows:
1) When the power supply voltage VCC is smaller than a first threshold value, the voltage sampling module is kept closed, and the signal V is sampled S By pulling down the second resistor R2 to ground potential (or zero), the control signal V is subjected to inversion processing by the inversion module C Is pulled up to the power supply voltage VCC, outputs the pull-up closing of the pull-up module and the reset signal V REST Pulled down to ground potential by ground GND through third resistor R3;
2) The power supply voltage VCC is continuously increased, and when the power supply voltage VCC is larger than or equal to a first threshold value and smaller than a second threshold value, the voltage sampling module is started to sample the signal V S Gradually increasing from zero, but sampling signal V S The output of the inverting module is not inverted before reaching the inversion threshold, the control signal V C Still being the power supply voltage VCC, the pull-up of the output pull-up module is still closed, the reset signal V REST Or is pulled down to ground potential by the third resistor R3;
3) The power supply voltage VCC is continuously increased, when the power supply voltage VCC is larger than or equal to a second threshold value, the voltage sampling module is started to sample the signal V S The output of the inverting module is inverted when the output is increased to the inversion threshold value, and the control signal V C The power supply voltage VCC is turned to the ground potential, and the pull-up of the pull-up module is outputted to turn on, so that the reset signal V REST Pulled up from ground to supply voltage VCC;
4) When sampling signal V S When the output of the inverting module is inverted when the inversion threshold is increased, the control signal V C The power supply voltage VCC is turned to the ground potential, the positive feedback module is started to sample the signal V S Pull up to the supply voltage VCC, i.e. when the supply voltage VCC is greater than or equal to the second threshold valueAfter that, through the feedback action of the positive feedback module, the signal V is sampled S Is pulled up to the power supply voltage VCC, no longer changes along with the change of the power supply voltage VCC, maintains and locks the turnover state of the reverse phase module through the positive feedback module, and strictly maintains and locks the reset signal V REST Based on the topology design of the circuit, the value of the second threshold is related to the value of the first threshold, the resistance of the first resistor R1, the resistance of the second resistor R2 and the value of the flip-flop threshold (related to the CMOS inverter formed by the third PMOS transistor P3 and the first NMOS transistor N1), and the value of the second threshold can be flexibly adjusted by adjusting the value of the first threshold, the resistance of the first resistor R1, the resistance of the second resistor R2 and the value of the flip-flop threshold, so that the output reset signal V REST The turning point of the digital baseband circuit can meet different reset requirements of a plurality of different digital baseband circuits of a later stage;
5) When the voltage sampling module is started, the threshold voltage V of the silicon-based PMOS tube is inside the voltage sampling module GS(th) And threshold voltage V of silicon-based diode th All are negative temperature coefficients, and when the temperature rises, the threshold voltage V of the silicon-based PMOS tube GS(th) And threshold voltage V of silicon-based diode th The first threshold value is reduced, the power supply voltage VCC is hardly changed along with the temperature, so that the voltage at two ends of the first resistor R1 is increased, but the first resistor R1 is a positive temperature coefficient resistor, the resistance value of the first resistor R1 is increased along with the temperature increase, and the increasing trend of the flowing current of the first resistor R1 caused by the temperature increase can be restrained through the increased resistance value of the first resistor R1; the replica current still tends to increase, and at the same time, the second resistor R2 is a negative temperature coefficient resistor whose resistance decreases with increasing temperature, so that the voltage across the second resistor R2 (i.e. the sampling signal V) can be suppressed by the decreasing resistance of the second resistor R2 S ) Similar analysis at temperature decrease, by the temperature coefficient of the first resistor R1 and the temperature coefficient of the second resistor R2 being matched, the signal V is sampled S To make a compensating adjustment of the temperature coefficient of the sampled signal V S Is almost zero, so that the reset signal V REST The turning point of (2) does not drift with temperature;
6) When the output pull-up module is pulled up, the threshold voltage V of the silicon-based PMOS tube is ignored in the output pull-up module GS(th) The threshold voltage V of the silicon-based PMOS tube is calculated by the negative temperature coefficient of GS(th) The power supply voltage VCC is almost unchanged with temperature, while the third resistor R3 is a zero temperature coefficient resistor with a resistance value unchanged with temperature, which makes the reset signal V after being turned over REST Hardly changes due to temperature drift, and strictly follows the power supply voltage VCC.
In an alternative embodiment of the present invention, a temperature simulation experiment is performed on a power-on reset circuit as shown in FIG. 2 to obtain a reset signal V at a temperature of-40 DEG C REST The change curve with the power supply voltage VCC is shown in FIG. 3, and the reset signal V at +25deg.C is obtained REST The change curve with the power supply voltage VCC is shown in FIG. 4, and the reset signal V at +85 ℃ is obtained REST The variation curve with the power supply voltage VCC is shown in FIG. 5, wherein the abscissa of the curve is the power supply voltage VCC and the ordinate of the curve is the output reset signal V REST . As can be seen from fig. 3 to 5, the reset signal V is outputted when the power supply voltage VCC is higher than 1.6V (i.e., the second threshold value is 1.6V) at-40 ℃, +25℃and +85℃ REST The reset signal V outputted by the power-on reset circuit is turned over and is changed from low level (0V) to high level (power supply voltage VCC) REST And the inversion point thereof does not vary with temperature. Therefore, the power-on reset circuit provided by the invention has good temperature stability.
In another alternative embodiment of the present invention, a power consumption simulation experiment is performed on the power-on reset circuit shown in fig. 2, so as to obtain a variation curve of the static working current along with the power supply voltage VCC as shown in fig. 6, wherein the abscissa of the curve is the power supply voltage VCC, and the ordinate of the curve is the static working current. As can be seen from fig. 6, when the power supply voltage VCC is in the range of 2V to 5V, the static operating current of the power-on reset circuit is always below 0.8 μa, and the static operating current is small, which makes the static power consumption of the power-on reset circuit lower.
The simulation experiment results show that: the invention proposesThe power-on reset circuit has an output reset signal V REST The temperature is not changed, and the power consumption is low. In addition, the large capacitor is not adopted any more, so that the power-on reset circuit has the characteristic of small area, and the power-on reset circuit has a reset signal V based on the flexible and adjustable value of the first threshold value, the resistance value of the first resistor R1, the resistance value of the second resistor R2 and the value of the turnover threshold value REST Is flexible and adjustable. Therefore, the power-on reset circuit provided by the invention can be widely applied to various electronic circuits.
In summary, in the power-on reset circuit provided by the invention, the voltage sampling module, the inverting module and the output pull-up module are combined to design the power-on reset circuit, the sampling voltage input by the inverting module is obtained by carrying out resistance sampling on the power supply voltage by the voltage sampling module, and the sampling voltage is completely determined by resistance sampling, so that the sampling voltage is always synchronous with the power supply voltage, a mode of sampling by charging a large capacitor in a traditional scheme is not needed, the capacitance value of the large capacitor is not matched with the turning point of a reset signal and the power-on waveform of the power supply voltage, the condition that the turning point of the reset signal fluctuates along with the change of the power-on waveform of the power supply voltage can be effectively avoided, and the design difficulty, the volume and the power consumption of the power-on reset circuit are reduced; the temperature coefficients of different branch sampling resistors in the voltage sampling module are matched so that the temperature coefficient of an output sampling signal is zero, and the output reset signal and the turning point of the reset signal do not drift along with the temperature by combining with a pull-down resistor of the zero temperature coefficient in the output pull-up module, so that the temperature stability of the output reset signal and the turning point of the reset signal is improved; meanwhile, a positive feedback module is introduced between the input end and the output end of the inverting module, and the inverting state of the inverting module is maintained and locked through the positive feedback module, so that the locked reset signal can be strictly maintained to be the power supply voltage, and the output reset signal and the power supply voltage stability of the inversion point of the reset signal are improved.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (11)
1. A power-on reset circuit, comprising:
the voltage sampling module is connected with a power supply voltage, and is started when the power supply voltage is greater than or equal to a first threshold value, and resistance sampling is carried out on the power supply voltage to obtain a sampling signal;
the positive power supply is connected with the power supply voltage, the negative power supply is connected with the ground, the input end of the negative power supply is connected with the sampling signal, and the sampling signal is subjected to inversion processing to obtain a control signal;
the positive power supply is connected with the power supply voltage, the negative power supply is connected with the control signal, and the output reset signal is subjected to pull-up processing under the control of the control signal;
when the power supply voltage is powered on, the power supply voltage gradually increases from zero, when the power supply voltage is smaller than a second threshold value, the sampling signal does not reach the turnover threshold value, the reset signal is pulled down to the ground potential, when the power supply voltage is larger than or equal to the second threshold value, the sampling signal reaches the turnover threshold value, the control signal turns over, so that the reset signal is pulled up to the power supply voltage from the ground potential, and the second threshold value is larger than the first threshold value.
2. The power-on reset circuit of claim 1 wherein the voltage sampling module remains off when the supply voltage is less than the first threshold, the sampling signal is zero, the control signal is the supply voltage, and the reset signal is pulled down to ground.
3. The power-on reset circuit of claim 2 wherein the voltage sampling module is enabled when the supply voltage is greater than or equal to the first threshold and less than the second threshold, the sampling signal gradually increases from zero but the sampling signal does not reach the flip threshold, the control signal remains the supply voltage, and the reset signal is pulled down to ground potential.
4. A power-on reset circuit as claimed in claim 3, wherein the voltage sampling module is enabled when the supply voltage is greater than or equal to the second threshold, the sampling signal increases to the toggling threshold, the control signal toggles from the supply voltage to ground, such that the reset signal is pulled up from ground to the supply voltage.
5. The power-on reset circuit of claim 1, wherein the voltage sampling module comprises a first PMOS tube, a second PMOS tube, n diodes, a first resistor and a second resistor, wherein the source electrode of the first PMOS tube is connected with the power supply voltage, the gate electrode of the first PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the first PMOS tube is connected with the anode of the first diode, the cathode of the ith diode is connected with the anode of the (i+1) th diode, the cathode of the nth diode is connected with the power supply voltage after being connected with the first resistor in series, the source electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube is connected with the drain electrode of the first PMOS tube in series and then is grounded, and the drain electrode of the second PMOS tube outputs the sampling signal; wherein n is an integer equal to or greater than 1, and i is an integer from 1 to n-1.
6. The power-on reset circuit of claim 5, wherein the inverting module comprises a third PMOS and a first NMOS, wherein a source of the third PMOS is connected to the power supply voltage, a gate of the third PMOS is connected to the sampling signal, a drain of the third PMOS is connected to a drain of the first NMOS, a gate of the first NMOS is connected to a gate of the third PMOS, a source of the first NMOS is grounded, and a drain of the first NMOS outputs the control signal.
7. The power-on reset circuit of claim 6, wherein the output pull-up module comprises a fourth PMOS transistor and a third resistor, a source of the fourth PMOS transistor is connected to the power supply voltage, a gate of the fourth PMOS transistor is connected to the control signal, a drain of the fourth PMOS transistor is connected to the third resistor in series and then to the ground, and a drain of the fourth PMOS transistor outputs the reset signal.
8. The power-on reset circuit of claim 7, wherein the first resistor is a positive temperature coefficient resistor, the second resistor is a negative temperature coefficient resistor, and the temperature coefficient of the first resistor cooperates with the temperature coefficient of the second resistor to zero the temperature coefficient of the sampling signal; the third resistor is a zero temperature coefficient resistor.
9. The power-on reset circuit of claim 7, wherein the value of the second threshold is related to the value of the first threshold, the resistance of the first resistor, the resistance of the second resistor, and the value of the flip threshold.
10. The power-on reset circuit of claim 1, further comprising:
and when the sampling signal reaches the turnover threshold value, the control signal is turned over to the ground potential by the power voltage, and the positive feedback module is started to pull up the sampling signal to the power voltage.
11. The power-on reset circuit of claim 10, wherein the positive feedback module comprises a fifth PMOS transistor, a source of the fifth PMOS transistor is connected to the power supply voltage, a gate of the fifth PMOS transistor is connected to the control signal, and a drain of the fifth PMOS transistor is connected to the sampling signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311551004.4A CN117579049A (en) | 2023-11-20 | 2023-11-20 | Power-on reset circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311551004.4A CN117579049A (en) | 2023-11-20 | 2023-11-20 | Power-on reset circuit |
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| CN117579049A true CN117579049A (en) | 2024-02-20 |
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| CN202311551004.4A Pending CN117579049A (en) | 2023-11-20 | 2023-11-20 | Power-on reset circuit |
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| CN (1) | CN117579049A (en) |
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