CN117579015A - Wafer-level packaging method of BAW filter - Google Patents
Wafer-level packaging method of BAW filter Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 47
- 239000010703 silicon Substances 0.000 claims abstract description 47
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 39
- 229910052802 copper Inorganic materials 0.000 claims abstract description 39
- 239000010949 copper Substances 0.000 claims abstract description 39
- 238000009713 electroplating Methods 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 11
- 238000005476 soldering Methods 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 43
- 238000000137 annealing Methods 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 8
- 230000001681 protective effect Effects 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000011161 development Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 238000005498 polishing Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 claims description 4
- 238000004021 metal welding Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000010354 integration Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
- H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
- H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
- H03H9/56—Monolithic crystal filters
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/46—Filters
- H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material
- H03H9/58—Multiple crystal filters
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- Physics & Mathematics (AREA)
- Acoustics & Sound (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Abstract
The application discloses a BAW filter wafer level packaging method, which comprises the following steps: bonding the first surface of the first BAW wafer and the first surface of the second BAW wafer, performing wafer-level bonding, etching the first surface of the BAW wafer after wafer-level bonding to form a silicon through hole, exposing a metal bonding pad after wafer-level bonding, depositing a metal seed layer in a non-silicon through hole area of the first surface of the BAW wafer, electroplating copper in the silicon through hole, and electroplating bumps on the formed copper surface to form the BAW filter of wafer-level packaging; and (5) performing reflow soldering in the bump electroplating process. The first BAW wafer serving as the sending end and the second BAW wafer serving as the receiving end are bonded together to realize three-dimensional stacking, so that occupied area is directly reduced by half, chip integration and use are facilitated, and chip miniaturization and light weight are realized.
Description
Technical Field
The application relates to the technical field of semiconductor packaging, in particular to a wafer-level method of a BAW filter.
Background
With the development of semiconductor technology, the requirements of the current electronic device on miniaturization and light weight are continuously improved, for example, taking a radio frequency module of a 5G mobile phone as an example, the radio frequency module generally adopts a quad-filter, that is, four BAW filters are combined and share the same node, so that two frequency bands can be received simultaneously.
The four BAW filters in the quadruplex are divided into two groups, wherein the two BAW filters in each group are respectively used as a receiving end and a transmitting end, and each group of filters is used for simultaneously filtering radio frequency signals of a receiving channel and a transmitting channel.
However, the quad-filter needs to use four filters, which results in a large area of the chip package, and is unfavorable for integration and use.
Disclosure of Invention
Based on the above problems, the application provides a wafer-level method of a BAW filter, which solves the problem that integration and use are not facilitated due to the large area of chip packaging.
The embodiment of the application discloses the following technical scheme:
the embodiment of the application provides a BAW filter wafer packaging method, which comprises the following steps:
providing a first BAW wafer and a second BAW wafer; the wafer size of the first BAW wafer is the same as the wafer size of the second BAW wafer; the first metal welding pad is arranged on the first surface of the first BAW wafer and the second metal welding pad is arranged on the first surface of the second BAW wafer correspondingly;
bonding the first surface of the first BAW wafer and the first surface of the second BAW wafer at a wafer level after bonding; the second surface of the first BAW wafer is used as the first surface of the wafer-level bonded BAW wafer; the second surface of the second BAW wafer acts as the second surface of the BAW wafer;
etching the first surface of the BAW wafer to form a through silicon via; the through silicon vias expose the wafer-level bonded metal pads;
depositing a metal seed layer in a non-through silicon via area of the first surface of the BAW wafer, and electroplating copper in the through silicon via to form a copper surface; the copper surface corresponds to the through silicon via;
electroplating bumps on the surface of the copper to form a BAW filter of the wafer level package; and the process of electroplating the convex points is performed with reflow soldering.
Optionally, the pre-etching step further comprises thinning the first surface of the BAW wafer; the etching is dry etching.
Optionally, the etching process includes:
exposing the region of the through silicon via through exposure and development;
performing dry etching on the area of the first surface of the BAW wafer;
and after removing the photoresist, forming the through silicon via.
Optionally, annealing the BAW wafer after the wafer level bonding; the annealing temperature is 300 ℃, and the annealing time is 1 hour.
Optionally, the metal seed layer includes a titanium layer and a copper layer that are sequentially stacked.
Optionally, the bump includes a copper layer, a nickel layer, and a tin-silver layer sequentially disposed.
Optionally, after the copper electroplating is completed, the first surface of the BAW wafer is subjected to chemical mechanical polishing.
Optionally, the electroplating bump is preceded by depositing the metal seed layer on the first surface of the BAW wafer.
Optionally, the electroplating bump includes:
photoetching the metal seed layer to form a patterned surface; the patterned surface comprises a pattern corresponding to the through silicon via and a pattern corresponding to a non-through silicon via region;
electroplating the region of the pattern corresponding to the through silicon via to obtain a bump corresponding to the through silicon via; and removing the metal seed layer except the convex points after the convex points are electroplated.
Optionally, after the copper surface is plated with the bump, the method further comprises:
attaching a protective film on the first surface of the BAW wafer;
thinning the second surface of the BAW wafer;
attaching a UV film on the thinned second surface, and removing the protective film on the first surface;
and cutting the BAW wafer.
Compared with the prior art, the application has the following beneficial effects:
according to the wafer-level packaging method of the BAW filter, after the first surface of the first BAW wafer and the first surface of the second BAW wafer are attached, wafer-level bonding is carried out, the first surface of the BAW wafer after wafer-level bonding is etched to form a silicon through hole, a metal bonding pad after wafer-level bonding is exposed, after a metal seed layer is deposited in a non-silicon through hole area of the first surface of the BAW wafer, copper is electroplated in the silicon through hole, and then bumps are electroplated on the formed copper surface to form the BAW filter of the wafer-level package; and (5) performing reflow soldering in the bump electroplating process. The first BAW wafer serving as the sending end and the second BAW wafer serving as the receiving end are bonded together to realize three-dimensional stacking, so that occupied area is directly reduced by half, chip integration and use are facilitated, and chip miniaturization and light weight are realized.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive faculty for a person skilled in the art.
FIG. 1 is a schematic diagram of a quad-pod provided in the related art;
fig. 2 is a schematic flow chart of a wafer level packaging method of a BAW filter according to an embodiment of the present application;
fig. 3 is a schematic diagram of a first BAW wafer and a second BAW wafer according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a wafer level bonding process according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of a BAW wafer including through silicon vias according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a BAW wafer after copper plating according to an embodiment of the present application;
FIG. 7a is a schematic diagram of a wafer level package BAW filter and quad filter according to the related art;
fig. 7b is a schematic diagram of a wafer level package BAW filter and a quad-filter according to an embodiment of the present application;
fig. 8a is a schematic diagram of a BAW wafer with a deposited metal seed layer according to an embodiment of the present application;
FIG. 8b is a schematic diagram of a lithographically patterned BAW wafer according to an embodiment of the present application;
fig. 8c is a schematic diagram of a BAW wafer with electroplated bumps according to an embodiment of the present application;
fig. 8d is a schematic diagram of a reflow soldering BAW wafer according to an embodiment of the present application.
Wherein a is a first BAW wafer, b is a second BAW wafer, 1 is a first metal bonding pad, 2 is a second metal bonding pad, 3 is a wafer-level bonded BAW wafer, 4 is a wafer-level bonded metal bonding pad, 5 is a first working area, 6 is a second working area, 7 is a through silicon via, 8 is copper plated in the through silicon via, 9 is a copper layer in a bump, 10 is a nickel layer in the bump, 11 is a tin-silver layer in the bump, 12 is a titanium seed layer, 13 is a copper seed layer, and G is a photoresist layer.
Detailed Description
As described above, in the research on wafer packaging, it is found that with the development of semiconductor technology, the requirements of the current electronic device on miniaturization and light weight are continuously increasing, for example, taking a radio frequency module of a 5G mobile phone as an example, the radio frequency module generally adopts a quad-coder, that is, four BAW filters are combined and share a same node, so that two frequency bands can be received simultaneously.
Referring to fig. 1, which shows a schematic diagram of a quad-filter provided by the related art, fig. 1 shows a top view of the quad-filter, where the quad-filter includes four BAW filters, respectively B1, B2, B3, and B4, TX represents a transmitting end, RX represents a receiving end, where B1 and B2 are a group, B3 and B4 are a group, B1 and B3 are transmitting ends, B2 and B4 are receiving ends, and two filters of each group are used to filter radio frequency signals of a receiving channel and a transmitting channel at the same time.
However, since the quad-filter needs to use four filters and the four filters need to be tiled on the chip, the area of the chip package is large, which is not beneficial to integration and use.
In order to solve the above problems, embodiments of the present application provide a BAW filter wafer level packaging method. The method comprises the following steps: bonding the first surface of the first BAW wafer and the first surface of the second BAW wafer, performing wafer-level bonding, etching the first surface of the BAW wafer after wafer-level bonding to form a silicon through hole, exposing a metal bonding pad after wafer-level bonding, depositing a metal seed layer in a non-silicon through hole area of the first surface of the BAW wafer, electroplating copper in the silicon through hole, and electroplating bumps on the formed copper surface to form the BAW filter of wafer-level packaging; and (5) performing reflow soldering in the bump electroplating process.
Therefore, the first BAW wafer serving as the sending end and the second BAW wafer serving as the receiving end are bonded together to realize three-dimensional stacking, so that occupied area is directly reduced by half, chip integration and use are facilitated, and chip miniaturization and light weight are realized.
In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the examples herein, all materials are commercially available products well known to those skilled in the art unless otherwise specified.
Referring to fig. 2, the flow chart of a BAW filter wafer level packaging method provided in the embodiment of the present application, with reference to fig. 2, the BAW filter wafer level packaging method provided in the embodiment of the present application may include:
s201: a first BAW wafer and a second BAW wafer are provided.
Wherein the wafer size of the first BAW wafer is the same as the wafer size of the second BAW wafer; the first metal bonding pad arranged on the first surface of the first BAW wafer corresponds to the second metal bonding pad arranged on the first surface of the second BAW wafer.
BAW (Bulk Acoustic Wave ) filters are filters based on the piezoelectric effect, and are commonly used in the wireless communication, radio frequency and microwave fields.
The first BAW wafer is used as a BAW filter of a transmitting end, and the second BAW wafer is used as a BAW filter of a receiving end. In a quad-or diplexer in general, both the transmit and receive ends, including BAW filters, are required.
Diplexers are commonly used in Frequency Division Duplex (FDD) radio applications, where one filter is a transmit filter and the other is a receive filter. The design of the diplexer ensures that the pass band of each filter is not loaded by the other filter.
The quad is composed of four filters sharing a node. Similar to a diplexer, its passband loading and isolation targets are consistent. The design of the quad-filter is more complex because the requirements of the four filters must be met simultaneously and the stringent crossover isolation specifications are met.
It should be understood that in the embodiment of the present application, the size of the first BAW wafer needs to be the same as the size of the second BAW wafer, and the size may be 6 inches, 8 inches, or 12 inches. The dimensions of the first BAW wafer and the second BAW wafer in the embodiments of the present application are not limited in particular, and may be those well known to those skilled in the art.
Referring to fig. 3, a first BAW wafer (a in fig. 3) provided in the embodiment of the present application includes a first metal bonding pad (1 in fig. 3), a second BAW wafer (b in fig. 3) includes a second metal bonding pad (2 in fig. 3), the thicknesses of the first metal bonding pad and the second metal bonding pad are preferably 1-2 μm, and may also be 1.5-2 μm, where the functions of the first metal bonding pad and the second metal bonding pad are all electrically interconnected with the outside. The material of the first metal pad and the second metal pad is preferably gold.
As shown in fig. 3, the first BAW wafer further includes a first working area (e.g., 5 in fig. 3), where an area on the first surface of the first BAW wafer corresponding to the first working area in the vertical direction is different from an area on the first surface of the first BAW wafer corresponding to the first metal pad, that is, the area on the first surface of the first BAW wafer corresponding to the first working area is not overlapped with the area on the first surface of the first BAW wafer corresponding to the first metal pad. The second BAW wafer and the first BAW wafer have the same second working area (e.g. 6 in fig. 3), and the specific description of the second BAW wafer can be referred to the description of the first BAW wafer, which is not repeated here.
S202: and bonding the first surface of the first BAW wafer and the first surface of the second BAW wafer at a wafer level after bonding.
Wherein the second surface of the first BAW wafer is used as the first surface of the wafer-level bonded BAW wafer; the second surface of the second BAW wafer acts as the second surface of the BAW wafer.
It should be understood that the wafer-level bonding is performed between the first metal pad and the second metal pad, so as to obtain the metal pad of the BAW wafer, that is, the metal pad after wafer-level bonding.
It should be understood that, in the embodiment of the present application, the first BAW wafer and the second BAW wafer are provided with four metal pads, that is, the 4 first metal pads of the first BAW wafer and the 4 second metal pads of the second BAW wafer are bonded together by gold and gold, or copper and copper through wafer-level bonding, so as to obtain a wafer-level bonded BAW wafer, as shown in fig. 4, which illustrates a wafer-level bonding process of the first BAW wafer and the second BAW wafer, where (a) in fig. 4 is the first BAW wafer, (b) in fig. 4 is the first metal pad, (b) in fig. 4 is the second BAW wafer, (2) in fig. 4 is the second metal pad, (3) in fig. 4 is the wafer-level bonded BAW wafer, and (4) in fig. 4 is the wafer-level bonded metal pad.
In some possible implementations, annealing the BAW wafer may also be included after the wafer level bonding; the annealing temperature is 300 ℃, and the annealing time is 1 hour. Through annealing at 300 ℃ for 1 hour, the bonding force between metals can be improved, the stress between metals can be eliminated, and the stability and reliability of the wafer-level bonded BAW wafer are ensured.
S203: and etching the first surface of the BAW wafer to form a through silicon via.
The through silicon vias expose the metal pads after wafer level bonding.
In some possible implementations, the etching of the BAW wafer is a dry etching, which may be:
step 1: and thinning the first surface of the BAW wafer. As an example, the first surface of the BAW wafer (corresponding to the second surface of the first BAW wafer when wafer level bonding is not performed) may be thinned to 100 μm (corresponding to the thinning of the first BAW wafer to 100 μm).
It should be understood that the thinning process is not limited in any way, and can be implemented by using a related art thinning technique, such as using a grinder to thin a BAW wafer.
The thinning of the first surface of the BAW wafer in the embodiment of the present application means thinning the first BAW wafer before wafer-level bonding, so that the first BAW wafer reaches a required thickness.
Step 2: and exposing the region of the through silicon via through exposure and development.
Step 3: and carrying out dry etching on the area of the first surface of the BAW wafer.
Step 4: and after removing the photoresist, forming the through silicon via.
The processes of exposure development, dry etching and photoresist removal described in the embodiments of the present application are not particularly limited, and processes well known to those skilled in the art may be adopted.
As shown in fig. 5, fig. 5 shows a BAW wafer with through silicon vias (e.g., 7 in fig. 5) formed by steps 1-5 described above.
S204: after depositing a metal seed layer in the non-through silicon via region of the first surface of the BAW wafer, electroplating copper in the through silicon via to form a copper surface.
Wherein the copper surface corresponds to the through silicon via. Fig. 6 is a schematic diagram of a BAW wafer after copper electroplating according to an embodiment of the present application.
As one possible implementation, the first surface of the BAW wafer is subjected to chemical mechanical polishing after the electroplated copper is completed.
As a possible implementation manner, the metal seed layer may include a titanium layer and a copper layer which are sequentially stacked.
S205: electroplating salient points on the first copper surface and the second copper surface respectively to form a BAW filter of the wafer level package; and the process of electroplating the convex points is performed with reflow soldering.
Referring to fig. 7a and 7B, fig. 7a illustrates a wafer-level packaged BAW filter of the related art (e.g., a of fig. 7 a), and a top view of a quad-pod (e.g., B of fig. 7 a) and a side view of the quad-pod (e.g., C of fig. 7 a); fig. 7b shows a top view of a wafer level packaged BAW filter (e.g., D in fig. 7 b) and a quad-pod (e.g., E in fig. 7 b) and a test pattern of a quad-pod (e.g., F in fig. 7 b) according to an embodiment of the present application.
As shown in fig. 7a and fig. 7b, compared with the BAW filter provided in the prior art, the embodiment of the application realizes three-dimensional stacking by bonding the first BAW wafer serving as the transmitting end and the second BAW wafer serving as the receiving end together, so that the occupied area is directly reduced by half, the chip is convenient to integrate and use, and the chip is miniaturized and light.
In some possible implementation manners, the process of electroplating bump and reflow soldering provided in the embodiments of the present application may be:
step one: the metal seed layer is deposited on the first surface of the BAW wafer, see in particular fig. 8a.
That is, a titanium seed layer and a copper seed layer are sequentially deposited on a first surface of the BAW wafer.
Step two: coating a layer of photoresist on the upper layer of the metal seed layer, and carrying out photoetching on the metal seed layer to form a patterned surface; the patterned surface includes a pattern corresponding to the through silicon via and a pattern corresponding to a non-through silicon via region, see fig. 8b.
That is, the through-silicon via region is exposed by the photolithography process, which facilitates subsequent electroplating of the bump.
Step three: electroplating the region of the pattern corresponding to the through silicon via to obtain the bump corresponding to the through silicon via, as shown in fig. 8 c. The bump may include a copper layer, a nickel layer, and a tin-silver layer, which are sequentially disposed.
Step four: and after the electroplating convex points are finished, carrying out reflow soldering on the electroplating convex points, and removing the metal seed layers except the convex points.
In some possible embodiments, after the copper surface is bumped, the method further includes:
step A: and attaching a protective film on the first surface of the BAW wafer.
Before the BAW wafer is thinned, a layer of protective film is adhered to the first surface of the BAW wafer (namely one surface of the electroplating salient points), and the protective film is used for fixing chips on the first surface of the BAW wafer, so that a lapping machine can conveniently grind the chips on the second surface of the BAW wafer.
The thickness of the second surface of the BAW wafer before polishing (i.e., the second BAW wafer before wafer level bonding) is typically around 700 μm, and after polishing, the thickness of the second surface of the BAW wafer becomes 200 μm or may be as much as 120 μm, which is determined according to the user's requirements.
And (B) step (B): and thinning the second surface of the BAW wafer.
It should be understood that in the embodiments of the present application, thinning the second BAW wafer may be understood as thinning the second BAW wafer before wafer level bonding is performed to bring the second BAW wafer to a desired thickness.
Step C: and sticking a UV film on the thinned second surface, and removing the protective film on the first surface.
Before dicing, the second surface of the BAW wafer is stuck with a UV film, the UV film has the function of adhering the chip on the film and showing a dicing channel, so that the integrity of the crystal grain in the dicing process can be maintained, the breakage generated in the dicing process can be reduced, the accurate dicing can be ensured, and the situation that the crystal grain is displaced and falls off in the normal conveying process can be ensured.
Step D: and cutting the BAW wafer.
The dicing process provided in the embodiments of the present application may refer to a dicing process of a related art, and will not be specifically described herein.
The "first" and "second" in the names of "first", "second" (where present) and the like in the embodiments of the present application are used for name identification only, and do not represent the first and second in sequence.
The foregoing is merely one specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A BAW filter wafer packaging method, the method comprising:
providing a first BAW wafer and a second BAW wafer; the wafer size of the first BAW wafer is the same as the wafer size of the second BAW wafer; the first metal welding pad is arranged on the first surface of the first BAW wafer and the second metal welding pad is arranged on the first surface of the second BAW wafer correspondingly;
bonding the first surface of the first BAW wafer and the first surface of the second BAW wafer at a wafer level after bonding; the second surface of the first BAW wafer is used as the first surface of the wafer-level bonded BAW wafer; the second surface of the second BAW wafer acts as the second surface of the BAW wafer;
etching the first surface of the BAW wafer to form a through silicon via; the through silicon vias expose the wafer-level bonded metal pads;
depositing a metal seed layer in a non-through silicon via area of the first surface of the BAW wafer, and electroplating copper in the through silicon via to form a copper surface; the copper surface corresponds to the through silicon via;
electroplating bumps on the surface of the copper to form a BAW filter of the wafer level package; and the process of electroplating the convex points is performed with reflow soldering.
2. The method of claim 1, wherein the pre-etch further comprises thinning the first surface of the BAW wafer; the etching is dry etching.
3. The method of claim 2, wherein the etching comprises:
exposing the region of the through silicon via through exposure and development;
performing dry etching on the area of the first surface of the BAW wafer;
and after removing the photoresist, forming the through silicon via.
4. The method of claim 1, further comprising annealing the BAW wafer after the wafer level bonding; the annealing temperature is 300 ℃, and the annealing time is 1 hour.
5. The method of claim 1, wherein the metal seed layer comprises a titanium layer and a copper layer disposed in sequence.
6. The method of claim 1, wherein the bump comprises a copper layer, a nickel layer, and a tin-silver layer disposed in that order.
7. The method of claim 1, wherein after the electroplated copper is completed, the first surface of the BAW wafer is subjected to chemical mechanical polishing.
8. The method of claim 7, further comprising depositing the metal seed layer on the first surface of the BAW wafer prior to electroplating the bump.
9. The method of claim 8, wherein the electroplating bump comprises:
photoetching the metal seed layer to form a patterned surface; the patterned surface comprises a pattern corresponding to the through silicon via and a pattern corresponding to a non-through silicon via region;
electroplating the region of the pattern corresponding to the through silicon via to obtain a bump corresponding to the through silicon via; and removing the metal seed layer except the convex points after the convex points are electroplated.
10. The method of claim 1, further comprising, after electroplating the bumps on the copper surface:
attaching a protective film on the first surface of the BAW wafer;
thinning the second surface of the BAW wafer;
attaching a UV film on the thinned second surface, and removing the protective film on the first surface;
and cutting the BAW wafer.
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| US20180183406A1 (en) * | 2016-12-23 | 2018-06-28 | Avago Technologies General Ip (Singapore) Pte. Ltd | Packaged resonator with polymeric air cavity package |
| CN115473508A (en) * | 2022-07-20 | 2022-12-13 | 厦门云天半导体科技有限公司 | Packaging structure and packaging method of filter chip |
| CN116053287A (en) * | 2023-01-10 | 2023-05-02 | 山东云海国创云计算装备产业创新中心有限公司 | Wafer-level infrared focal plane array preparation method and infrared focal plane array |
| CN117013974A (en) * | 2023-10-08 | 2023-11-07 | 深圳新声半导体有限公司 | Wafer-level packaging method of BAW filter |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20180183406A1 (en) * | 2016-12-23 | 2018-06-28 | Avago Technologies General Ip (Singapore) Pte. Ltd | Packaged resonator with polymeric air cavity package |
| CN115473508A (en) * | 2022-07-20 | 2022-12-13 | 厦门云天半导体科技有限公司 | Packaging structure and packaging method of filter chip |
| CN116053287A (en) * | 2023-01-10 | 2023-05-02 | 山东云海国创云计算装备产业创新中心有限公司 | Wafer-level infrared focal plane array preparation method and infrared focal plane array |
| CN117013974A (en) * | 2023-10-08 | 2023-11-07 | 深圳新声半导体有限公司 | Wafer-level packaging method of BAW filter |
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