CN117577658A - Method for manufacturing semiconductor structure and structure thereof - Google Patents
Method for manufacturing semiconductor structure and structure thereof Download PDFInfo
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- CN117577658A CN117577658A CN202410052033.4A CN202410052033A CN117577658A CN 117577658 A CN117577658 A CN 117577658A CN 202410052033 A CN202410052033 A CN 202410052033A CN 117577658 A CN117577658 A CN 117577658A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims description 31
- 238000002955 isolation Methods 0.000 claims abstract description 233
- 239000010410 layer Substances 0.000 claims abstract description 192
- 239000000758 substrate Substances 0.000 claims abstract description 131
- 239000002346 layers by function Substances 0.000 claims abstract description 101
- 239000011241 protective layer Substances 0.000 claims abstract description 62
- 239000000463 material Substances 0.000 claims abstract description 55
- 239000002131 composite material Substances 0.000 claims abstract description 28
- 238000000151 deposition Methods 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 10
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 10
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 15
- 239000007789 gas Substances 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- 208000033999 Device damage Diseases 0.000 description 5
- 238000003384 imaging method Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 206010034972 Photosensitivity reaction Diseases 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000036211 photosensitivity Effects 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- AXQKVSDUCKWEKE-UHFFFAOYSA-N [C].[Ge].[Si] Chemical compound [C].[Ge].[Si] AXQKVSDUCKWEKE-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- LIKFHECYJZWXFJ-UHFFFAOYSA-N dimethyldichlorosilane Chemical compound C[Si](C)(Cl)Cl LIKFHECYJZWXFJ-UHFFFAOYSA-N 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- FAIAAWCVCHQXDN-UHFFFAOYSA-N phosphorus trichloride Chemical compound ClP(Cl)Cl FAIAAWCVCHQXDN-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- CZDYPVPMEAXLPK-UHFFFAOYSA-N tetramethylsilane Chemical compound C[Si](C)(C)C CZDYPVPMEAXLPK-UHFFFAOYSA-N 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1462—Coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14685—Process for coatings or optical elements
Abstract
The application relates to a manufacturing method of a semiconductor structure and the structure thereof, comprising the following steps: providing a substrate, wherein a plurality of shallow trench isolation structures are formed in the substrate at intervals, and the top surfaces of the shallow trench isolation structures are flush with the first surface of the substrate; forming a protective layer on the second surface of the substrate; forming a plurality of isolation structures corresponding to the shallow trench isolation structures in the substrate and the protection layer; the isolation structure protrudes out of the protective layer, part of the isolation structure protruding out of the protective layer is a composite grid, and part of the isolation structure positioned in the protective layer and the substrate is a deep groove isolation structure; removing the protection layer and part of the substrate to expose the deep trench isolation structures; forming a plurality of functional layers on the substrate between the deep trench isolation structures, wherein the materials of the plurality of functional layers are different; wherein, the composite grille protrudes outside the multi-layer functional layer. The manufacturing method of forming the isolation structure, then etching the substrate back and depositing the functional layers in sequence to form the photosensitive area is adopted, so that the photosensitive performance of the image sensor is improved.
Description
Technical Field
The present disclosure relates to integrated circuit technology, and more particularly, to a method for fabricating a semiconductor structure and a structure thereof.
Background
Complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) image sensors are used to sense radiation of light, and CMOS image sensors can utilize photodiodes (also referred to as photosensitive regions) and transistor arrays in a substrate to absorb radiation impinging on the substrate and convert the sensed radiation into electrical signals.
The backside illuminated (Back Side illumination, BSI) image sensor is a type of image sensor, and under low light conditions, the BSI image sensor has better performance than the front side illuminated image sensor, however, the existing manufacturing method of the BSI image sensor results in insufficient photosensitive performance of the image sensor, so how to improve the photosensitive performance of the BSI image sensor is one of the technical problems to be solved urgently at present.
Disclosure of Invention
Based on this, it is necessary to provide a method for manufacturing a semiconductor structure and a structure thereof for solving the problem of insufficient photosensitivity of the BSI image sensor in the prior art.
In order to achieve the above object, in one aspect, the present application provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein a plurality of shallow trench isolation structures are formed in the substrate at intervals, and the top surfaces of the shallow trench isolation structures are flush with the first surface of the substrate; forming a protective layer on the second surface of the substrate; forming a plurality of isolation structures corresponding to the shallow trench isolation structures in the substrate and the protection layer; the isolation structure protrudes out of the protective layer, part of the isolation structure protruding out of the protective layer is a composite grid, and part of the isolation structure positioned in the protective layer and the substrate is a deep groove isolation structure; removing the protection layer and part of the substrate to expose the deep trench isolation structures; forming a plurality of functional layers on the substrate between the deep trench isolation structures, wherein the materials of the functional layers are different; wherein, the composite grille protrudes outside the multi-layer functional layer.
In one embodiment, forming a plurality of isolation structures corresponding to the shallow trench isolation structures in the substrate and the protection layer includes: forming a plurality of deep trenches corresponding to the shallow trench isolation structures in the substrate and the protective layer; sequentially forming a plurality of isolation sublayers on the deep trenches and the protective layer; and removing part of the plurality of isolation sublayers on the protective layer to form an isolation structure protruding out of the protective layer.
In one embodiment, removing portions of the plurality of isolation sublayers on the protective layer comprises: removing part of the plurality of isolation sublayers on the protective layer by adopting photoetching and dry etching processes to form an isolation structure protruding outwards from the protective layer; the part of the isolation structure protruding out of the protection layer is trapezoid in shape of a preset section.
In one embodiment, a plurality of isolation sub-layers are sequentially formed on the deep trench and the protection layer, including: forming a first sub-isolation layer on the groove wall, the groove bottom and the protection layer of the deep groove respectively; forming a second sub-isolation layer on the deep trench and the first sub-isolation layer respectively; forming a third sub-isolation layer on the deep trench and the second sub-isolation layer respectively; the second sub isolation layer is positioned between the first sub isolation layer and the third sub isolation layer in the deep groove, and the third sub isolation layer is positioned in the middle area of the deep groove.
In one embodiment, the first sub-isolation layer comprises a silicon dioxide layer, the second sub-isolation layer comprises a hafnium dioxide layer, and the third sub-isolation layer comprises a titanium nitride layer.
In one embodiment, forming a multi-layer functional layer on the substrate between the deep trench isolation structures comprises: depositing a first material on the surface of one side of the substrate, which is away from the shallow trench isolation structure, to form a first functional layer; depositing a second material on the first functional layer to form a second functional layer; depositing a third material on the second functional layer to form a third functional layer to form a plurality of functional layers; wherein the first material, the second material, and the third material are different and each include one of the group VA elements.
In one embodiment, the first material comprises silicon phosphide, the second material comprises silicon arsenide, and the third material comprises silicon antimonide.
In one embodiment, the method for manufacturing a semiconductor structure further includes: and forming optical filters on the multi-layer functional layers between the composite grids.
In a second aspect, the present application further provides a semiconductor structure, including: a substrate, an isolation structure and a multi-layer functional layer; wherein, a plurality of shallow trench isolation structures are formed in the substrate at intervals, and the top surfaces of the shallow trench isolation structures are flush with the first surface of the substrate; the isolation structure is arranged in the substrate and the multilayer functional layer and corresponds to the shallow trench isolation structure, the isolation structure protrudes out of the multilayer functional layer, part of the isolation structure protruding out of the multilayer functional layer is a composite grating, and part of the isolation structure in the multilayer functional layer and the substrate is a deep trench isolation structure; the multi-layer functional layers are positioned on the substrate between the deep trench isolation structures, and the materials of the functional layers are different.
In one embodiment, the isolation structure includes a plurality of isolation sublayers, wherein a portion of the isolation structure protruding beyond the multilayer functional layer has a trapezoid shape in a predetermined cross section.
The manufacturing method of the semiconductor structure and the structure thereof have the following unexpected beneficial effects:
the manufacturing method of the semiconductor structure comprises the steps of firstly providing a substrate, forming shallow trench isolation structures which are arranged at intervals in the substrate, enabling the top surface of the shallow trench isolation structures to be flush with the first surface of the substrate, isolating a plurality of active areas in the substrate by the shallow trench isolation structures, forming a protective layer on the second surface of the substrate, protecting the substrate from damage, forming a plurality of isolation structures corresponding to the shallow trench isolation structures in the substrate and the protective layer, wherein the isolation structures comprise composite grids protruding out of the protective layer and deep trench isolation structures located in the protective layer and the substrate, the deep trench isolation structures can avoid electrical crosstalk between devices, the composite grids can avoid interference between light waves, then removing the protective layer and part of the substrate to expose the deep trench isolation structures, forming a plurality of functional layers on the substrate between the deep trench isolation structures, and enabling the composite grids to protrude out of the plurality of functional layers. Compared with the process flow of forming the photosensitive region by high-energy ion implantation in the traditional manufacturing method, the manufacturing method of forming the isolation structure firstly, then etching the substrate back and depositing the functional layers in sequence to form the photosensitive region is adopted, so that device damage caused by high-energy ion implantation is avoided, and the photosensitive performance of the image sensor is improved.
The semiconductor structure can be used as a manufacturing base in the technical process, the isolation structure can avoid mutual interference between electric crosstalk and light waves with different wavelengths, imaging quality of the image sensor is improved, and compared with a traditional functional layer, the multi-layer functional layer has no defects and better photoelectric conversion performance, and photosensitivity of the image sensor is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to one embodiment;
FIG. 2 is a schematic cross-sectional view of a semiconductor structure obtained in step S102 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 3 is a schematic cross-sectional view of a semiconductor structure obtained in step S104 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 4 is a schematic cross-sectional view of the semiconductor structure obtained in step S106 in the method for fabricating a semiconductor structure according to one embodiment; FIG. 4 is a schematic cross-sectional view of an isolation structure obtained in the method for fabricating a semiconductor structure according to one embodiment;
FIG. 5 is a schematic cross-sectional view of a semiconductor structure obtained in step S108 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 6 is a schematic cross-sectional view of a semiconductor structure obtained in step S110 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 7 is a flowchart of step S106 in a method for fabricating a semiconductor structure according to one embodiment;
fig. 8-12 are schematic cross-sectional views of the structure obtained in step S702 in the method for fabricating a semiconductor structure according to an embodiment;
FIG. 13 is a schematic cross-sectional view of a semiconductor structure obtained in step S704 in a method for fabricating a semiconductor structure according to an embodiment;
FIG. 14 is a schematic cross-sectional view of a filter in a semiconductor structure according to one embodiment;
fig. 15 is a schematic cross-sectional view of a semiconductor structure provided in another embodiment.
Reference numerals illustrate:
1. a substrate; 2. shallow trench isolation structures; 3. a protective layer; 4. a silicon layer; 5. a photoresist; 6. a hard mask layer; 7. deep trenches; 8. an isolation structure; 81. a first sub-isolation layer; 82. a second sub-isolation layer; 83. a third sub-isolation layer; 801. a composite grid; 802. a deep trench isolation structure; 9. a plurality of functional layers; 91. a first functional layer; 92. a second functional layer; 93. a third functional layer; 10. a light filter; 12. an etch stop layer; 13. an interlayer dielectric layer; 14. a metal layer; 15. and a through hole.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Referring to fig. 1, the present application provides a method for fabricating a semiconductor structure, which includes steps S102-S110.
Step S102: a substrate is provided.
Referring to fig. 2, a plurality of shallow trench isolation structures 2 are formed in the substrate 1 at intervals, and the top surface of the shallow trench isolation structures 2 is flush with the first surface of the substrate 1.
As an example, the substrate 1 may be constituted by a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate 1 may have a single-layer structure or a multilayer structure. For example, the substrate 1 may be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III/V semiconductor substrate or II/VI semiconductor substrate. Alternatively, the substrate 1 may be a layered substrate comprising, for example, si/SiGe, si/SiC, silicon-on-insulator (SOI) or silicon-germanium-on-insulator. The type of substrate 1 should therefore not limit the scope of protection of the present disclosure. Wherein the thickness of the substrate 1 may be 2.5 micrometers to 3.5 micrometers, for example 3 micrometers, the first surface of the substrate 1 being the surface of the substrate 1 opposite the OY direction. In addition, the shape of the shallow trench isolation structure 2 in the preset section can be trapezoid in fig. 2, the depth of the shallow trench isolation structure 2 is smaller than the thickness of the substrate 1, and the dielectric material filled in the shallow trench isolation structure 2 can be oxide so as to isolate electrical crosstalk between different active areas and improve the imaging quality of the image sensor.
Step S104: a protective layer is formed on the second surface of the substrate.
Referring to fig. 3, as an example, the protective layer 3 may include a multi-layered protective layer of an oxide layer and a high dielectric constant layer, and the material and the film structure of the protective layer 3 are not particularly limited in this application. The protective layer 3 can protect the substrate 1 from being damaged in the process of forming the isolation structure, and improves the quality of the substrate 1, thereby ensuring the quality of a multi-layer functional layer and the isolation structure which are manufactured in the substrate, and further optimizing the quality of the image sensor.
As an example, the protective layer 3 may be formed by performing a heat treatment on the resulting structure after ion implantation of the substrate 1 from the second surface of the substrate 1, the implant material used for ion implantation of the substrate 1 includes, but is not limited to, oxygen gas, which is present in the substrate 1 in the form of oxygen radicals after being implanted into the substrate 1, and then performing a heat treatment on the resulting structure, the oxygen radicals reacting with silicon in the substrate 1 to form a silicon oxide layer as the protective layer 3.
Step S106: and forming a plurality of isolation structures corresponding to the shallow trench isolation structures in the substrate and the protection layer.
Referring to fig. 4, the isolation structure 8 protrudes outside the protection layer 3, and a portion of the isolation structure protruding outside the protection layer 3 is a composite grating 801, and a portion of the isolation structure located in the protection layer 3 and the substrate 1 is a deep trench isolation structure 802.
The composite grating 801 protruding out of the protective layer 3 is used for isolating light waves with different wavelengths, so that mutual interference between the light waves is avoided, the deep trench isolation structure 802 positioned in the protective layer 3 and the substrate 1 is used for isolating a plurality of photosensitive areas in the substrate 1, electrons between different photosensitive areas can be isolated, and electric crosstalk is avoided to influence imaging quality. As an example, the sum of the depth of the deep trench isolation structure 802 and the depth of the shallow trench isolation structure 2 is smaller than the thickness of the substrate 1.
Step S108: and removing the protection layer and part of the substrate to expose the deep trench isolation structures.
Referring to fig. 5, as an example, one or more of photolithography, dry etching, and wet etching may be used to remove the protective layer and part of the substrate 1, for example, chemical mechanical polishing (Chemical-Mechanical Planarization, CMP) or electrochemical etching may be used to directionally remove the protective layer and part of the substrate 1, where the CMP or electrochemical etching is helpful to improve etching accuracy, avoid damage to the isolation structure, and affect the isolation performance of the isolation structure.
Step S110: forming a plurality of functional layers on the substrate between the deep trench isolation structures, wherein the materials of the plurality of functional layers are different; wherein, the composite grille protrudes outside the multi-layer functional layer.
Referring to fig. 6, as an example, a multilayer functional layer 9 may be formed by solid diffusion, a silicon layer with a certain thickness is first deposited, then a first diffusion layer is deposited on the silicon layer, the first diffusion layer includes a target element, a device after the first diffusion layer is deposited is subjected to heat treatment, so that the target element is diffused into the silicon layer with a certain thickness to form a functional layer, the multilayer functional layer 9 may be formed by repeating the solid diffusion forming manner, the damage of the device caused by direct injection of high-energy ions is avoided, and the photosensitive performance of the image sensor is improved. In addition, the number of layers of the multi-layer functional layer 9 is not particularly limited, and the multi-layer functional layer 9 with different numbers of layers can be adopted according to actual requirements so as to increase the focusing property of light.
In the embodiment, the manufacturing method for forming the photosensitive region by forming the isolation structure, etching the substrate back and depositing the functional layers sequentially can avoid device damage caused by forming the photosensitive region by high-energy ion implantation, and avoid damage to the functional layer caused by forming the functional layer and then forming the isolation structure, so that the photosensitive performance of the image sensor is improved.
In one embodiment, referring to fig. 7, forming a plurality of isolation structures corresponding to shallow trench isolation structures in a substrate and a protection layer includes: step S702 to step S706.
Step S702: and forming a plurality of deep trenches corresponding to the shallow trench isolation structures in the substrate and the protective layer.
As an example, referring to fig. 8-12, forming a plurality of deep trenches corresponding to shallow trench isolation structures in a substrate and a protection layer may include: depositing a silicon layer 4 on the protective layer 3, and forming a plurality of photo-resists 5 which are arranged at intervals in the parallel direction of the OX on the silicon layer 4; exposing and developing the silicon layer 4 according to the photoresist 5; forming a hard mask layer 6 on the protective layer 3 and between the silicon layers 4; removing the developed silicon layer 4 to form a hard mask layer 6 with a first opening; and etching the substrate 1 according to the hard mask layer 6, and removing the hard mask layer 6 by dry etching to form a plurality of deep trenches 7.
Wherein, the photoresist 5 corresponds to the shallow trench isolation structure 2 and a first opening corresponds to the shallow trench isolation structure 2.
As an example, the material of the hard mask layer 6 may be silicon dioxide, silicon nitride, titanium nitride, or the like.
Step S704: and forming a plurality of isolation sublayers on the deep grooves and the protective layer in sequence.
The plurality of isolation sublayers can be made of different materials to realize different functions, for example, stress can be relieved by adopting silicon nitride or silicon oxide and the like, and light waves and the like are isolated by adopting the isolation sublayers made of metal materials; wherein the metal material includes but is not limited to at least one of titanium nitride, cobalt, platinum and titanium tungsten.
As an example, silicon oxide can be deposited by adopting an atomic layer deposition mode in chemical vapor deposition, firstly, activating the surfaces of the deep trench and the protective layer to improve the reactivity, introducing silicon source gas such as tetramethylsilicon into the reaction chamber to enable gas molecules to be adsorbed on the surfaces of the deep trench and the protective layer to form a single layer, removing silicon source gas molecules which are not adsorbed on the surfaces, introducing an oxidant such as oxygen to oxidize the silicon source gas molecules adsorbed on the surfaces into silicon oxide, and then repeating the above operation until the film thickness meets the requirement. Because the atomic layer deposition can be controlled to a single layer, the accuracy of film thickness and the surface flatness of the isolation sub-layers can be ensured by depositing a plurality of isolation sub-layers in an atomic layer deposition mode, and the formed isolation sub-layers are compact and uniform in structure, so that the accuracy of the isolation sub-layer deposition control can be improved, and the quality of a device is optimized.
Step S706: and removing part of the plurality of isolation sublayers on the protective layer to form an isolation structure protruding out of the protective layer.
In one embodiment, referring to fig. 13, a plurality of isolation sub-layers are sequentially formed on the deep trench and the protection layer, including: forming a first sub-isolation layer 81 on the groove wall, the groove bottom and the protection layer 3 of the deep groove respectively; forming a second sub-isolation layer 82 on the deep trench and the first sub-isolation layer 81, respectively; and forming a third sub-isolation layer 83 on the deep trench and the second sub-isolation layer 82, respectively. Wherein, in the deep trench, the second sub-isolation layer 82 is located between the first sub-isolation layer 81 and the third sub-isolation layer 83, and the third sub-isolation layer 83 is located in the middle region of the deep trench.
As an example, the first sub-isolation layer 81 may be a buffer layer, which not only may buffer stress generated between the protection layer 3 and the second sub-isolation layer 82 due to a larger difference in lattice constant, but also may enhance bonding force between adjacent film layers, and improve bonding strength of the device as a whole, and the thickness of the first sub-isolation layer 81 may range from 15nm to 25nm, for example: 18nm, 20nm, 22nm, 23nm, etc.; the second sub-spacer 82 may be a barrier layer for avoiding undesirable effects of electrons, such as reducing recombination of electron hole pairs, and may have a thickness in the range of 10nm to 20nm, for example: 12nm, 14nm, 16nm, 18nm, etc.; the third sub-spacer layer 83 may be a light isolation layer, so as to avoid interference of light waves with different wavelengths on the photosensitive region, and the thickness range may be 40nm-50nm, for example, 42nm, 44nm, 46nm, 48nm, etc.
In one embodiment, the first sub-isolation layer comprises a silicon dioxide layer, the second sub-isolation layer comprises a hafnium oxide layer, and the third sub-isolation layer comprises a titanium nitride layer.
In the embodiment, the silicon dioxide layer is used as the first sub-isolation layer, so that the stress between the hafnium oxide and the protection layer can be relieved, and the device damage caused by the stress is avoided; the hafnium oxide layer is adopted as the second sub-isolation layer, so that the interaction between electrons can be weakened by utilizing the insulativity of the hafnium oxide layer, and the non-ideal effect of the electrons can be reduced; the titanium nitride layer is used as the third sub-isolation layer to block light waves, so that the interference of the light waves between different photosensitive areas is avoided, and the performance of the image sensor is improved.
In one embodiment, please continue with fig. 4, removing portions of the plurality of isolation sublayers on the protective layer includes: and removing part of the plurality of isolation sublayers on the protective layer 3 by adopting photoetching and dry etching processes to form an isolation structure protruding outside the protective layer 3. Wherein, the part of the isolation structure protruding outside the protection layer 3 is trapezoid in shape of a preset section.
As an example, the preset cross section is a plane parallel to the plane in which OY and OX lie, and the trapezoidal shape of the composite grating 801 is co-located with the trapezoidal shape of the deep trench isolation structure 802.
By way of example, since hafnium oxide and titanium nitride have low selectivity to photoresist, a portion of the third sub-spacer 83 and a portion of the second sub-spacer 82 are first removed by dry etching, which includes at least Reactive Ion Etching (RIE)Any one of inductively coupled plasma etching (ICP) or high-concentration plasma etching (HDP); for example, RIE may be used to etch the third sub-spacer 83 using chlorine as the reactive gas and argon as the carrier gas, followed by CHF 3 Or C 4 F 8 The second sub-isolation layer 82 is etched by using the reaction gas and argon gas as carrier gases, and then the first sub-isolation layer 81 is subjected to photoetching by using a mask, so that the isolation structure 8 is obtained.
In the above embodiment, the composite grating and the deep trench isolation structure with trapezoid shapes on the preset cross section are adopted, and the trapezoids share the bottom edge, so that the luminous flux between the composite gratings can be increased, more light waves are received by the photosensitive area, the number of electron hole pairs generated by the photosensitive area is increased, the resolution of the image sensor is improved, and the photosensitive performance and the image quality of the device are further improved. In addition, part of the isolation sub-layer is etched by adopting a mode of combining photoetching and dry etching, so that the accuracy of etching patterns is ensured, and the etching efficiency is improved.
In one embodiment, please continue to refer to fig. 6, a multi-layer functional layer is formed on the substrate between the deep trench isolation structures, comprising: depositing a first material on the surface of one side of the substrate 1 away from the shallow trench isolation structure 2 to form a first functional layer 91; depositing a second material on the first functional layer 91 to form a second functional layer 92; a third material is deposited on the second functional layer 92 to form a third functional layer 93 to form a multi-layer functional layer.
Wherein the first material, the second material, and the third material are different and each include one of the group VA elements. As an example, the group VA element may include nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), and moromi (Mc), etc.
In one embodiment, the first material may comprise silicon phosphide, the second material may comprise silicon arsenide, and the third material may comprise silicon antimonide.
As an example, the first, second, and third functional layers 91, 92, and 93 may be sequentially formed using a chemical vapor deposition process. For example, the first functional layer 91 may be silicon phosphide, the reaction chamber is first heated to 350-400 ℃, for example 380 ℃, and a silicon source gas and a phosphorus source gas, for example dimethyl silicon dichloride and phosphorus chloride, are introduced into the heated reaction chamber, and the silicon source gas and the phosphorus source gas react at a high temperature using hydrogen as a carrier gas to generate silicon phosphide on the surface of the substrate 1. Similarly, the second functional layer 92 and the third functional layer 93 may be sequentially generated in a similar manner.
In the above embodiment, the first material, the second material and the third material are directly deposited by using a chemical vapor deposition process to form a multi-layer functional layer, so that damage to the photosensitive region caused by high-energy ion implantation is avoided, the photosensitive performance of the photosensitive region is affected, and the ion or electron concentration of the photosensitive region can be increased by using a direct deposition method compared with a solid diffusion method, thereby increasing the number of electron hole pairs and improving the imaging quality.
In one embodiment, the thickness of the first functional layer may range from 500nm to 600nm, for example: 530nm, 560nm, 580nm, etc.; the thickness of the second functional layer may range from 400nm to 500nm, for example: 420nm, 440nm, 460nm, 480nm, etc.; the thickness of the third functional layer may range from 300nm to 400nm, for example: 320nm, 340nm, 360nm, 380nm, etc.
In the above embodiment, the number of electron hole pairs can be increased by using the multi-layer functional layer with the thickness range as the photosensitive region, thereby improving the photoelectric conversion performance of the device. In other embodiments, the appropriate thickness range may also be selected according to the number of functional layers.
In one embodiment, referring to fig. 14, the method for fabricating the semiconductor structure further includes: and forming optical filters on the multi-layer functional layers between the composite grids.
As an example, the filter 10 includes, but is not limited to, a red filter, a yellow filter, a blue filter, and the like, and the three filters are adjacently arranged as a pixel group. The red light wave is transmitted by the red light filter, the yellow light wave is transmitted by the yellow light filter, the blue light wave is transmitted by the blue light filter, the mutual interference among different light waves can be avoided by the composite grid, and the quality of the pixel is improved.
It should be understood that, although the steps in the flowcharts of fig. 1 and 7 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 1 and 7 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in turn or alternately with at least a portion of the steps or stages in other steps or other steps.
With continued reference to fig. 6, the present application further provides a semiconductor structure, including: a substrate 1, an isolation structure 8 and a multi-layer functional layer 9.
Wherein, a plurality of shallow trench isolation structures 2 are formed in the substrate 1 at intervals, and the top surface of the shallow trench isolation structures 2 is flush with the first surface of the substrate 1; the isolation structures 8 are positioned in the substrate 1 and the multilayer functional layer 9 and are arranged corresponding to the shallow trench isolation structures 2, the isolation structures 8 are outwards protruded from the multilayer functional layer 9, part of the isolation structures outwards protruded from the multilayer functional layer 9 are composite grids, and part of the isolation structures positioned in the multilayer functional layer 9 and the substrate 1 are deep trench isolation structures; a plurality of functional layers 9 are located on the substrate 1 between the deep trench isolation structures, the materials of each of the plurality of functional layers 9 being different.
In the above embodiment, the substrate 1 may be used to provide a manufacturing base for a device, the isolation structure 8 may avoid electrical crosstalk and mutual interference between light waves with different wavelengths, so as to improve imaging quality of the image sensor, and the multi-layer functional layer has better photoelectric conversion performance than the conventional functional layer, so as to improve photosensitivity of the image sensor.
With continued reference to fig. 4, in one embodiment, the isolation structure includes a plurality of isolation sub-layers, wherein a portion of the isolation structure protruding from the multi-layer functional layer has a trapezoid shape in a predetermined cross section.
Specifically, the isolation structure 8 includes a first sub-isolation layer 81, a second sub-isolation layer 82, and a third sub-isolation layer 83; wherein the second sub-isolation layer 82 is located between the first sub-isolation layer 81 and the third sub-isolation layer 83, and the third sub-isolation layer 83 is located in the middle region of the deep trench.
In the above embodiment, the composite grating 801 and the deep trench isolation structure 802 with trapezoid shapes on the preset cross section are adopted, and the trapezoids share the bottom edge, so that the luminous flux between the composite gratings can be increased, more light waves are received by the photosensitive area, the number of electron hole pairs generated by the photosensitive area is increased, and therefore the resolution of the image sensor is improved, and the photosensitive performance and the image quality of the device are further improved.
In one embodiment, the first sub-isolation layer comprises a silicon dioxide layer, the second sub-isolation layer comprises a hafnium oxide layer, and the third sub-isolation layer comprises a titanium nitride layer.
In the embodiment, the silicon dioxide layer is used as the first sub-isolation layer, so that the stress between the hafnium oxide layer and the protection layer can be relieved, and the device damage caused by the stress is avoided; the hafnium oxide layer is adopted as the second sub-isolation layer, so that the interaction between electrons can be weakened by utilizing the insulativity of the hafnium oxide layer, and the non-ideal effect of the electrons can be reduced; the titanium nitride layer is used as the third sub-isolation layer to block light waves, so that the interference of the light waves between different photosensitive areas is avoided, and the performance of the image sensor is improved.
With continued reference to fig. 6, in one embodiment, the multi-layer functional layer includes: a first functional layer comprising a first material, a second functional layer comprising a second material, and a third functional layer comprising a third material; wherein the first material, the second material, and the third material are different and each include one of the group VA elements.
In one embodiment, the first material comprises silicon phosphide, the second material comprises silicon arsenide, and the third material comprises silicon antimonide.
In the above embodiment, the use of the material of phosphorus, arsenic, antimony, or the like in the VA group element as the material of the functional layer can improve the photoelectric conversion efficiency, thereby improving the photosensitivity of the device.
With continued reference to fig. 14, in one embodiment, the semiconductor structure further includes: and optical filters 10 between the composite gratings and on the multiple functional layers.
In the above embodiment, by providing the optical filter 10 on the multi-layer functional layer, the light waves with different wavelengths can be received by different photosensitive regions by using the filtering characteristics of the optical filters with different colors, thereby forming pixels.
In one embodiment, referring to fig. 15, the semiconductor structure further includes: an etch stop layer 12, an interlayer dielectric layer 13, a metal layer 14, and a via 15.
Wherein the etching stop layer 12 covers the first surface of the substrate 1 for avoiding damaging the substrate when etching the through hole 15; the interlayer dielectric layer 13 covers the etching stop layer 12 and is used for isolating the substrate 1 from the metal layer 14; the metal layer 14 is positioned on the surface of the interlayer dielectric layer 13 and is arranged corresponding to the through hole 15; wherein, the through hole 15 is located in the interlayer dielectric layer 13 and the etching stop layer 12 and is used for connecting the metal layer 14 and devices in the substrate 1.
The manufacturing method of the semiconductor structure and the structure thereof have the following unexpected beneficial effects: the substrate is provided, shallow trench isolation structures are formed in the substrate at intervals, the top surfaces of the shallow trench isolation structures are flush with the first surface of the substrate, the shallow trench isolation structures can be used for isolating a plurality of active areas in the substrate, a protective layer is formed on the second surface of the substrate, the substrate can be protected from damage, a plurality of isolation structures corresponding to the shallow trench isolation structures are formed in the substrate and the protective layer, the isolation structures comprise composite grids protruding out of the protective layer and deep trench isolation structures located in the protective layer and the substrate, the deep trench isolation structures can avoid electrical crosstalk between devices, the composite grids can avoid interference between light waves, then the protective layer and part of the substrate are removed, the deep trench isolation structures are exposed, a plurality of functional layers are formed on the substrate between the deep trench isolation structures, materials of the functional layers are different, and the composite grids protrude out of the plurality of the functional layers. Compared with the process flow of forming the photosensitive region by high-energy ion implantation in the traditional manufacturing method, the manufacturing method of forming the isolation structure firstly, then etching the substrate back and depositing the functional layers in sequence to form the photosensitive region is adopted, so that device damage caused by high-energy ion implantation is avoided, and the photosensitive performance of the image sensor is improved.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein a plurality of shallow trench isolation structures are formed in the substrate at intervals, and the top surfaces of the shallow trench isolation structures are flush with the first surface of the substrate;
forming a protective layer on the second surface of the substrate;
forming a plurality of isolation structures corresponding to the shallow trench isolation structures in the substrate and the protection layer; the isolation structure protrudes out of the protective layer, part of the isolation structure protruding out of the protective layer is a composite grid, and part of the isolation structure located in the protective layer and the substrate is a deep groove isolation structure;
removing the protective layer and part of the substrate to expose the deep trench isolation structures;
forming a plurality of functional layers on the substrate between the deep trench isolation structures, wherein the materials of the functional layers are different; wherein, the compound grid is outwards protruded from the multi-layer functional layer.
2. The method of fabricating a semiconductor structure according to claim 1, wherein forming a plurality of isolation structures corresponding to the shallow trench isolation structures in the substrate and the protective layer comprises:
forming a plurality of deep trenches corresponding to the shallow trench isolation structures in the substrate and the protection layer;
sequentially forming a plurality of isolation sublayers on the deep trenches and the protective layer;
and removing part of the isolation sublayers on the protective layer to form the isolation structure protruding outwards from the protective layer.
3. The method of fabricating a semiconductor structure according to claim 2, wherein said removing portions of said plurality of isolation sublayers on said protective layer comprises:
removing part of the isolation sublayers on the protective layer by adopting photoetching and dry etching processes to form the isolation structure protruding outwards from the protective layer; the isolation structure is arranged on the protective layer, wherein the part of the isolation structure protruding outwards from the protective layer is trapezoid in shape at a preset section.
4. The method of fabricating a semiconductor structure of claim 2, wherein sequentially forming a plurality of isolation sub-layers over the deep trench and the protection layer comprises:
forming a first sub-isolation layer on the groove wall, the groove bottom and the protection layer of the deep groove respectively;
forming a second sub-isolation layer on the deep trench and the first sub-isolation layer respectively;
forming a third sub-isolation layer on the deep trench and the second sub-isolation layer respectively; the second sub-isolation layer is located between the first sub-isolation layer and the third sub-isolation layer in the deep trench, and the third sub-isolation layer is located in the middle area of the deep trench.
5. The method of claim 4, wherein the first sub-spacer comprises a silicon dioxide layer, the second sub-spacer comprises a hafnium oxide layer, and the third sub-spacer comprises a titanium nitride layer.
6. The method of claim 1, wherein forming a multi-layer functional layer on the substrate between the deep trench isolation structures comprises:
depositing a first material on the surface of one side of the substrate, which is away from the shallow trench isolation structure, to form a first functional layer;
depositing a second material on the first functional layer to form a second functional layer;
depositing a third material on the second functional layer to form a third functional layer to form the multi-layer functional layer; wherein the first material, the second material, and the third material are different and each include one of group VA elements.
7. The method of claim 6, wherein the first material comprises silicon phosphide, the second material comprises silicon arsenide, and the third material comprises silicon antimonide.
8. The method according to any one of claims 1-7, further comprising:
and forming a light filter on the multi-layer functional layer between the composite grids.
9. A semiconductor structure, comprising:
a substrate, wherein a plurality of shallow trench isolation structures are formed in the substrate at intervals, and the top surfaces of the shallow trench isolation structures are flush with the first surface of the substrate;
the isolation structure is positioned in the substrate and the multilayer functional layer and corresponds to the shallow trench isolation structure, the isolation structure protrudes out of the multilayer functional layer, part of the isolation structure protruding out of the multilayer functional layer is a composite grid, and part of the isolation structure positioned in the multilayer functional layer and the substrate is a deep trench isolation structure;
and the functional layers are positioned on the substrate between the deep trench isolation structures, and the materials of the functional layers are different.
10. The semiconductor structure of claim 9, wherein the isolation structure comprises a plurality of isolation sublayers, wherein a portion of the isolation structure protruding beyond the multilayer functional layer has a trapezoid shape in a predetermined cross-section.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130292750A1 (en) * | 2012-05-04 | 2013-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Image device and methods of forming the same |
| US20210074747A1 (en) * | 2019-09-10 | 2021-03-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pixel device layout to reduce pixel noise |
| EP3945588A2 (en) * | 2020-07-29 | 2022-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pixel isolation structure |
| CN115881750A (en) * | 2023-02-02 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN115911074A (en) * | 2023-02-02 | 2023-04-04 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN116031272A (en) * | 2023-03-31 | 2023-04-28 | 合肥新晶集成电路有限公司 | Method for preparing semiconductor structure and semiconductor structure |
| CN116110923A (en) * | 2023-03-31 | 2023-05-12 | 合肥新晶集成电路有限公司 | Method for preparing semiconductor structure and semiconductor structure |
| CN116314229A (en) * | 2023-03-31 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN116646366A (en) * | 2023-07-17 | 2023-08-25 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130292750A1 (en) * | 2012-05-04 | 2013-11-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Image device and methods of forming the same |
| US20210074747A1 (en) * | 2019-09-10 | 2021-03-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Pixel device layout to reduce pixel noise |
| EP3945588A2 (en) * | 2020-07-29 | 2022-02-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pixel isolation structure |
| CN115881750A (en) * | 2023-02-02 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN115911074A (en) * | 2023-02-02 | 2023-04-04 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN116031272A (en) * | 2023-03-31 | 2023-04-28 | 合肥新晶集成电路有限公司 | Method for preparing semiconductor structure and semiconductor structure |
| CN116110923A (en) * | 2023-03-31 | 2023-05-12 | 合肥新晶集成电路有限公司 | Method for preparing semiconductor structure and semiconductor structure |
| CN116314229A (en) * | 2023-03-31 | 2023-06-23 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN116646366A (en) * | 2023-07-17 | 2023-08-25 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
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