CN117573605A - SoC structure based on CORTEX-R4 architecture - Google Patents

Abstract

The invention discloses an SoC structure based on a CORTEX-R4 architecture, which comprises a system processor, an EMIF1 controller, an EMIF2 controller, a pin multiplexing control module IOMAX and a plurality of functional peripheral modules; the system processor is a core of a CORTEX-R4 processor; the system processor and a plurality of functional peripheral modules are integrated on an on-chip BUS system BUS MATRIX; the ATCM, the B0TCM and the B1TCM of the three interfaces of the TCM address space of the system processor are respectively connected with the FLASH module in the external connection sheet, the EMIF1 controller and the on-chip SRAM memory; the EMIF2 controller supports access control of the large-capacity memory, the pins EMIF2IO of the EMIF2 controller and the pins EMIF1IO of the EMIF1 controller are controlled by the pin multiplexing control module IOMAX, and the external pins of the EMIF2 controller and the EMIF1 controller are EMIF IO MUX; the external pin MODE is input to the pin multiplexing control module IOMAX, determines the reset value of the module internal register MODE REG, and configures the module REG through the on-chip bus interface after the reset.

Description

SoC structure based on CORTEX-R4 architecture

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a SoC structure based on a CORTEX-R4 architecture.

Background

The instruction space of an ARM CORTEX-R4 architecture SoC typically starts with a 0x0000 address, the first 16MB address space starting with a 0 address maps to the TCM access interface (TCM space is divided into ATCM and BTCM, both of which are configurable from a range of 4KB-8MB, totaling a maximum of 16 MB), and the other memory spaces on the chip typically can only use the address range behind 16MB. After the processor is reset, the instruction execution program is read from the TCM address space, so the address space from which the TCM starts is generally used to store the instruction executed after the reset, and the physical memory location mapped by the address space from which the 0x0000 starts determines the convenience of testing and application.

In the first case, if an EMIF (external memory access interface) controller is integrated to the TCM access interface, the address space of the address section from the 0 address is allocated to the memory access pin of the chip, and the ATE test machine can provide instructions for the memory access pin in real time to realize online test. If a second EMIF controller is integrated in the chip and used for controlling the external high-capacity memory, two sets of EMIF interfaces of a single chip are realized, about 40-60 IOs are usually required for a single EMIF interface, and two EMIFs occupy too many IO resources, so that the chip area is increased, and the packaging and PCB design complexity are increased.

In the second case, if referring to the design scheme of many SoC products with ARM core x-R4 architecture on the market, the address space from 0x00000000 is mapped to the on-chip Flash memory, and the on-chip Flash controller and the on-chip Flash memory are integrated for the TCM access interface, then the on-chip Flash memory needs to be programmed with instructions through the debug interface before the ATE test, and then the test program is reset and executed. The method is not beneficial to the development of test work and increases the test cost and time expenditure of chips, but the design scheme generally integrates the EMIF memory on an on-chip bus interface, is convenient for externally connecting a large-capacity off-chip memory, and is more beneficial to meeting the application requirements of different users.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a SoC structure based on a CORTEX-R4 architecture, which is used for solving the problems in the background art.

In order to achieve the above purpose, the present invention provides the following technical solutions:

the SoC structure based on the CORTEX-R4 architecture comprises a system processor, an EMIF1 controller, an EMIF2 controller, a pin multiplexing control module IOMAX and a plurality of functional peripheral modules;

the system processor is a core of a CORTEX-R4 processor; the system processor and the functional peripheral modules are integrated on an on-chip BUS system BUS MATRIX;

the ATCM, the B0TCM and the B1TCM of three sets of interfaces of the TCM address space of the system processor are respectively connected with the FLASH module in the external connection sheet, the EMIF1 controller and the SRAM memory in the chip;

the EMIF2 controller supports access control of the large-capacity memory, the pins EMIF2IO of the EMIF2 controller and the pins EMIF1IO of the EMIF1 controller are controlled by a pin multiplexing control module IOMAX, and the external pins of the EMIF2 controller and the EMIF1 controller are EMIF IO MUX;

the external pin MODE is input to the pin multiplexing control module IOMAX, determines the reset value of the module internal register MODE REG, and configures the module REG through the on-chip bus interface after the reset.

Preferably, the bus interface of the system processor is a bus interface compatible with the AXI protocol of the ARM company.

Preferably, when the EMIF IO MUX interface needs to be externally connected with a high-capacity off-chip memory, the off-chip memory is an SDRAM or Flash memory.

Preferably, the system processor is connected with a debug interface JTAG, and when the JTAG interface is externally connected with a debugger, the input command controls the processor to enter a debug mode to access an internal address space for programming a Flash memory in the chip.

Preferably, the configuration input port LOCZRAMA of the system processor is driven by an off-chip input pin MODE;

when MODE is 0, the initial addresses 0x0000 0000-0 x003F FFFF are mapped to the B0TCM interface; when MODE is 1, the initial addresses 0 x00000000-0 x0077F FFFF map to the ATCM interface.

Preferably, the configuration input ports CFGATCMSZ and CFGBTCMSZ of the system processor determine the spatial dimensions of the processors ATCM, B0TCM and B1TCM, and the size ranges from 4KB to 8MB.

Preferably, the IOMAX module comprises a selector MUX1 and a selector MUX2; the reset signal RSTN is respectively connected to the reset ports of the selection terminal SEL1 and the Mode reg register of the selector MUX 1; the external pin MODE input is connected with the input end 0 of the selector MUX1, and the on-chip bus access control output is connected with the other input end 1 of the selector MUX 1; the output end of the selector MUX1 is connected with the input end D of the Mode reg register; the output end Q of the Mode reg register is connected with the selection end SEL2 of the selector MUX2; the pins EMIF2IO of the EMIF2 controller and the pins EMIF1IO of the EMIF1 controller are respectively connected with the input end of the selector MUX2, and the output end of the selector MUX2 is used as an external pin EMIF IO MUX;

when the reset signal RSTN is 0, the input SEL1 of the selector MUX1 is 0, the MUX1 outputs a MODE pin signal to a MODE reg register, the Q terminal of the MODE reg register controls the selection terminal SEL2 of the selector MUX2, and the MUX2 connects an EMIF1IO signal or an EMIF2IO signal in the chip with an EMIF IO MUX pin, depending on whether the MODE signal is 0 or 1; when the reset signal RSTN is 1, the selector MUX1 selects the input terminal D to which the bus access control output signal is given to the Mode reg, the Q of the Mode reg outputs the value of the D terminal at the next clock rising edge, the selection terminal SEL2 of the selector MUX2 is controlled to be 0 or 1, depending on whether the bus configuration information is 0 or 1, and the MUX2 connects the EMIF1IO signal or the EMIF2IO signal in the chip with the EMIF IO MUX pin according to the configuration information. Therefore, the MODE pin selects the EMIF IO MUX control right during the reset period when the RSTN is 0, and the bus access selects the EMIF IO MUX control right after the RSTN is 1.

Preferably, the external pin MODE directly drives the LOCZRAMA signal to the system processor.

Preferably, when the MODE input pin is 0, the test MODE is used for performing on-line test of the ATE or for an application scenario in which no external large-capacity off-chip memory is required; when the MODE input pin is 1, the function MODE is used for meeting the use requirement of the SoC external high-capacity off-chip memory.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention provides an SoC structure based on a CORTEX-R4 architecture, which comprehensively considers the testability and application requirements of a chip, and provides an SoC structure based on-chip dual EMIF integration, pin multiplexing dynamic control and flexible address space control switching structure on the premise of ARM CORTEX-R4 architecture. The invention is suitable for the design of SoC and similar architecture products of all CORTEX-R4 architectures, and can effectively reduce the test cost and the pin overhead of the chip.

The SoC provided by the invention has two modes, meets the use requirement of the SoC external high-capacity off-chip memory in the functional mode, supports rapid ATE on-line test in the test mode, omits the step of programming Flash in the traditional design, reduces the test time, and realizes comprehensive consideration of the test efficiency and the use requirement. Only one set of EMIF IO pins are led out of the SoC, so that pin overhead is reduced. The invention can be conveniently integrated into various SoCs of ARM CORTEX-R4 architecture according to actual application requirements, has definite structure and simple control logic, and can effectively reduce test cost and pin overhead of a chip.

Drawings

FIG. 1 is a block diagram of a low pin overhead SoC architecture for easy testing based on the CORTEX-R4 architecture.

Fig. 2 is a schematic diagram of MODE pin input control pin multiplexing.

Detailed Description

The invention will now be described in further detail with reference to specific examples, which are intended to illustrate, but not to limit, the invention.

The invention discloses a CORTEX-R4 architecture-based SoC design method and structure with easy testing and low pin overhead, and aims to solve the problem that the existing CORTEX-R4 architecture SoC design scheme cannot be compatible with easy testing and application requirements. The invention is suitable for the design of SoC and similar architecture products of all CORTEX-R4 architectures, can effectively reduce the test cost and the pin overhead of the chip, meets the quick test requirement of SoC products and the application requirement of large-capacity memory banks, and has good economic benefit.

The invention provides a CORTEX-R4 architecture SoC design method and a CORTEX-R4 architecture SoC design structure which are easy to test and low in pin overhead, and the CORTEX-R4 architecture SoC design method and the CORTEX-R4 architecture SoC design structure based on double EMIF integration, pin multiplexing dynamic control and address space flexible control switching structure are provided, so that on one hand, the requirements of ATE test are met, the test efficiency is improved, and on the other hand, the requirements of application on mass storage are met, and excessive pin overhead is not increased. The method is clear in implementation method, clear in control structure and universal, is suitable for the design of SoCs of all CORTEX-R4 architectures and similar architecture products, and can effectively reduce the test cost and the pin overhead of chips.

The SoC design method and the implementation structure which are based on the CORTEX-R4 architecture and easy to test and low in pin overhead are as follows:

the SoC structure block diagram proposed by the present invention is shown in fig. 1, the system processor is a core of a core-R4 processor, modules-1, 2 are functional peripheral modules, pins are IO-1, IO-2 are IO-n, the peripheral modules and the processor are integrated together on an on-chip BUS system BUS, the BUS interface of the processor is an AXI BUS interface of the ARM standard, and the functional peripheral Module BUS interface BI can be self-planned according to the actual IP design and integration conditions. The ATCM, B0TCM and B1TCM of three sets of interfaces of the TCM address space of the processor respectively externally connect an internal FLASH memory, an EMIF1 controller and an internal SRAM memory, wherein FLASH Module in the figure comprises a FLASH controller and a FLASH memory, and SRAM Module comprises an SRAM controller and an SRAM memory. The EMIF2 controller supports access control of a large-capacity memory such as SDRAM, flash and the like, the pins EMIF2IO of the EMIF2 controller and the pins EMIF1IO of the EMIF1 controller are controlled by the pin multiplexing control module IOMAX, and the external pins of the two modules are finally EMIF IO MUX.

The external pin MODE is input to the IOMAX module, determines the input of the internal register MODE REG of the module, and after reset, can configure the MODE REG through the on-chip bus interface. The output of the MODE REG register determines whether the control of this portion of the pins of the EMIF IO MUX is assigned to EMIF1 or EMIF2, and the MODE pin input control structure in the IOMAX module is shown in FIG. 2.

The IOMAX module comprises a selector MUX1 and a selector MUX2; the reset signal RSTN is respectively connected to the reset ports of the selection terminal SEL1 and the Mode reg register of the selector MUX 1; the external pin MODE input is connected with the input end 0 of the selector MUX1, and the on-chip bus access control output is connected with the other input end 1 of the selector MUX 1; the output end of the selector MUX1 is connected with the input end D of the Mode reg register; the output end Q of the Mode reg register is connected with the selection end SEL2 of the selector MUX2; the pins EMIF2IO of the EMIF2 controller and the pins EMIF1IO of the EMIF1 controller are respectively connected with the input end of the selector MUX2, and the output end of the selector MUX2 is used as an external pin EMIF IO MUX.

IOMAX module, when reset signal RSTN is 0, input SEL1 of selector MUX1 is 0, MUX1 outputs MODE pin signal to MODE reg register, Q end of MODE reg register controls selection end SEL2 of selector MUX2, MUX2 connects EMIF1IO signal or EMIF2IO signal and EMIF IO MUX pin in the chip, it depends on MODE signal is 0 or 1; when the reset signal RSTN is 1, the selector MUX1 selects the input terminal D to which the bus access control output signal is given to the Mode reg, the Q of the Mode reg outputs the value of the terminal D at the next clock rising edge, the selection terminal SEL2 of the selector MUX2 is controlled to be 0 or 1, depending on the bus configuration information being 0 or 1, the MUX2 connects the internal EMIF1IO signal or the internal EMIF2IO signal of the chip with the EMIF IO MUX pin according to the configuration information, so that the Mode pin selects the EMIF IO MUX control right during the reset period when the RSTN is 0, and the bus access selects the EMIF IO MUX control right after the RSTN is 1 reset.

The two sets of inputs CFGATCMSZ [3:0] and CFGBTCMSZ [3:0] determine the spatial dimensions of the processors ATCM and BTCM, ranging in size from 4KB-8MB. In this embodiment, CFGATCMSZ [3:0] and CFGBTCMSZ [3:0] of the CORTEX-R4 processor are set to 4' b1110, and the corresponding ATCM is 8MB, B0TCM is 4MB, B1TCM is 4MB, and TCM space is 16MB. The MODE pin inputs direct drive processor configuration input LOCZRAMA, when the input of LOCZRAMA is 1 according to ARM CORTEX-R4 processor manual, the initial address 0x 0000-0 x 0077F FFFF space of the processor is mapped to an ATCM interface Flash Module,0x 00800000-0 x00BF FFFF space is mapped to a B0TCM interface EMIF1 controller, and 0x00C 00000-0 x00FF FFFF space is mapped to a B1TCM interface SRAM Module; when the input of LOCZRAMA is 0, the initial addresses 0x0000 0000-0 x003F FFFF space of the processor are mapped to the B0TCM interface EMIF1 controller, 0x0040 0000-0 x0070F FFFF space is mapped to the B1TCM interface SRAM Module, and 0x0080 0000-0 x00FF FFFF space is mapped to the ATCM interface Flash Module.

The MODE input pin is 1, and is in a functional MODE. In this case, before the processor runs, the MODE REG is 1, and the pin control right of the EMIF IO MUX is attributed to the EMIF2 controller. The configuration input LOCZRAMA of the CORTEX-R4 processor is 1, the initial addresses 0x 00000000-0 x 0077F FFFF are mapped to the ATCM interface, and after the system is powered on and reset, the instruction execution program is read from the Flash memory connected with the ATCM. EMIF2 can be used to store large volumes of data or instructions, the address space is within the address range behind the TCM interface space, and the specific address range of EMIF2 is implemented by designing an on-chip bus system according to the system requirements. Because the Flash memory has no external pin in the chip, in this way, the program needs to be written into the Flash Module of the initial instruction area through the JTAG debugging interface control system before the use, and then reset again, and the SoC executes the expected program to start working. JTAG interface communication speed is slow, flash memory is generally long in programming time, soC usually has a plurality of test vectors, when the mode test is adopted, each vector needs to be operated, flash needs to be firstly erased, and then an observation result of an operation program is reset, so that a large amount of ATE test time is consumed.

The MODE input pin is 0, which is the test MODE. In this case, before the processor runs, MODE REG is 0, and the pin control right of the EMIF IO MUX is attributed to the EMIF1 controller. The configuration input LOCZRAMA of the CORTEX-R4 processor is 0, the initial addresses 0x 00000000-0 x003F FFFF are mapped to the B0TCM interface, and the instruction execution program is read from the EMIF1 externally connected with the B0TCM after the system is powered on and reset. When the chip is tested by the ATE, all input pins and output pins of the chip are connected with an ATE test machine, the ATE test machine can provide continuous instruction flow for the EMIF IO MUX interface, the chip is controlled to perform online test, the requirement of quick test is met, and the operation of burning Flash in advance like a functional mode is not needed. When testing other modules except EMIF2, setting an ATE machine to output an instruction stream to an EMIF IO MUX pin, directly reading instructions from the EMIF IO MUX pin after resetting a processor and executing the instructions, wherein the instructions are directly defined as functional test programs for each module, when one section of program is tested, switching the programs, directly resetting and setting the ATE machine to output the next section of program to the EMIF IO MUX pin, and completing the test of each module without repeatedly programming Flash; when the function of the EMIF2 module in the test piece is tested, the ATE machine station is set to output a BOOT program to the EMIF IO MUX pin, the BOOT program is defined by a user, instructions and data defined by the program can be set to be carried into an on-chip SRAM memory of the B1TCM, the BOOT program can define an address space of the instructions and the data to be carried out outside the BOOT program of the EMIF1 module, for example, the front 1MB of the EMIF1 is the BOOT, the rear 3MB is the test program and the data area to be carried, after reset, the processor reads the part of the BOOT instructions from the front 1MB space of the EMIF1 and operates, the content of the rear 3MB of the EMIF1 is stored into the on-chip SRAM memory, after carrying is finished, the processor executes a jump instruction to be jumped to 0x0040 0000 to 0x 0072F FFFF address space corresponding to the SRAM memory, after that the control right of the part of the pin of the EMIF IO module is attributed to the EMIF2 controller, and the function and the communication parameters of the EMIF2 module can be tested in the following program.

When the MODE input pin is 0, the method is not only suitable for chip testing, but also can be used for setting the instruction area of the processor to be an off-chip EMIF space for working in the scene that a user does not need external mass storage.

The design method and the implementation structure provided by the invention do not prescribe the form of the on-chip bus interface BI and do not limit the number of on-chip peripheral functional modules (Module-1, module-2. For convenience of description, the CFGATCMSZ [3:0] and CFGBTCMSZ [3:0] are set as 4' b1110, and the mapping relationship between the CFGATCMSZ [3:0], CFGBTCMSZ [3:0] and the TCM space is not repeated here, but reference may be made to ARM CORTEX-R4 INTERGRATION MANUAL, and the scheme may be adjusted according to different application requirements in practical design. In addition, only the multiplexing control of the EMIF1 and EMIF2 modules IO by the IOMAX unit is described herein, and in practical design and application, multiplexing control can be implemented by the IO of the EMIF1, EMIF2 and other functional modules, which is not limited herein. In practical design and application, the method and the structure provided by the invention can be conveniently integrated into SoCs of ARM CORTEX-R4 architectures with different application requirements according to practical application requirements and system architectures.

Examples

As shown in fig. 1, the architecture block diagram of the corex-R4 architecture-based SoC of the present invention is easy to test.

The processor is ARM CORTEX-R4 kernel, the TCM interface of the processor comprises three sets of ATCM, B0TCM and B1TCM, flash Module, EMIF1 and SRAM Module are integrated respectively, and in the embodiment, the TCM address space is 0x0000 0000-0 x00FF FFFF. The external BUS interface of the processor is an AXI BUS interface, the processor can be used as an AXI host to access each device on the on-chip BUS BUS, the access address of each device on the BUS is between 0x0100 0000 and 0xFFFF FFFF, and EMIF2, IOMAX, module-1, module-2, module-n and the like in the figure are all in the address space range. Configuration input ports relevant to the present invention include LOCZRAMA, CFGATCMSZ, CFGBTCMSZ. LOCZRAMA is driven by an off-chip input pin MODE, and when MODE is 0, the initial addresses 0x0000 0000-0 x003F FFFF are mapped to a B0TCM interface; when MODE is 1, the initial addresses 0x00000000 to 0 x0077F FFFF map to the ATCM interface. CFGATCMSZ, CFGBTCMSZ in this embodiment, the input is 4' B1110, the corresponding ATCM is 8MB, and the b0TCM and the B1TCM are both 4MB, so that the actual design can be adjusted according to different application requirements. JTAG is the debug interface of the processor, when JTAG interface connects the debugger, can control the processor to enter the debug mode to visit the internal address space, can be used for writing the Flash memory in the slice. The MODE input and on-chip address mapping is shown in table 1 below.

Other functional peripheral modules include EMIF2, IOMAX, module-1, module-2, module-n, etc., which are integrated on the on-chip BUS, and the number and interface form of the peripheral modules are not limited. IO pins of modules such as IO-1 and IO-2. The IOMAX module is a pin multiplexing control unit, the EMIF1IO and the EMIF2IO realize multiplexing through IOMAX control, only one set of EMIF pin EMIF IO MUX is led out, the MODE input determines the reset value of a MODE reg register in the IOMAX module, the output of the MODE reg register determines that the control right of the pins of the EMIF IO MUX is attributed to the EMIF1 or EMIF2 module, and the MODE reg updates and outputs after the BUS ACCESS is accepted after reset, and the specific logic structure diagram is shown in the following figure 2. RSTN is a reset signal, 0 is a reset active state, MUX1 and MUX2 are two selectors, MUX1 determines the source of the Mode reg register input, MUX2 determines EMIF1IO or EMIF2IO controls EMIF IO MUX pins. MODE directly drives the lock ram signal to the core x-R4 processor.

The SoC design method and structure based on the CORTEX-R architecture and easy to test and low in pin overhead are applied to a general 32-bit MCU, can be applied to SoCs of all ARM CORTEX-R4 architectures, can effectively reduce test cost and pin overhead of chips, and simultaneously meets the quick test requirement of SoC products and the application requirement of a large-capacity memory bank, and has good economic benefit. This architecture is suitable for use in SoC systems that include processors of similar architecture, without limitation, the processor must be ARM core x-R4.

Claims (9)

1. The SoC structure based on the CORTEX-R4 architecture is characterized by comprising a system processor, an EMIF1 controller, an EMIF2 controller, a pin multiplexing control module IOMAX and a plurality of functional peripheral modules;

the system processor is a core of a CORTEX-R4 processor; the system processor and the functional peripheral modules are integrated on an on-chip BUS system BUS MATRIX;

the ATCM, the B0TCM and the B1TCM of three sets of interfaces of the TCM address space of the system processor are respectively connected with the FLASH module in the external connection sheet, the EMIF1 controller and the SRAM memory in the chip;

the EMIF2 controller supports access control of a large-capacity memory, the pins EMIF2IO of the EMIF2 controller and the pins EMIF1IO of the EMIF1 controller are controlled by a pin multiplexing control module IOMAX, and the external pins of the EMIF2 controller and the EMIF1 controller are EMIFIO MUX;

the external pin MODE is input to the pin multiplexing control module IOMAX, determines the reset value of the module internal register MODE REG, and configures the module REG through the on-chip bus interface after the reset.

2. The SoC architecture based on the core-R4 architecture of claim 1, wherein the bus interface of the system processor is an ARM company AXI compliant bus interface.

3. The SoC structure based on the core-R4 architecture of claim 1, wherein when the EMIF IO MUX interface requires an external high-capacity off-chip memory, the off-chip memory is an SDRAM or a Flash memory.

4. The SoC architecture based on the core-R4 architecture of claim 1, wherein the system processor is coupled to a debug interface JTAG, and when the JTAG interface is externally connected to a debugger, the input commands control the processor to enter a debug mode to access an internal address space for programming Flash memory within the chip.

5. The SoC architecture based on the core-R4 architecture of claim 1, wherein the configuration input port LOCZRAMA of the system processor is driven by an off-chip input pin MODE;

when MODE is 0, the initial addresses 0x0000 0000-0 x003F FFFF are mapped to the B0TCM interface; when MODE is 1, the initial addresses 0 x00000000-0 x0077F FFFF map to the ATCM interface.

6. The SoC architecture based on the core x-R4 architecture of claim 1, wherein the configuration input ports CFGATCMSZ and CFGBTCMSZ of the system processor determine the spatial dimensions of the processors ATCM, B0TCM and B1TCM, ranging in size from 4KB to 8MB.

7. The SoC architecture based on the cotex-R4 architecture of claim 1, wherein the IOMAX module includes a selector MUX1 and a selector MUX2; the reset signal RSTN is respectively connected to the reset ports of the selection terminal SEL1 and the Mode reg register of the selector MUX 1; the external pin MODE input is connected with the input end 0 of the selector MUX1, and the on-chip bus access control output is connected with the other input end 1 of the selector MUX 1; the output end of the selector MUX1 is connected with the input end D of the Mode reg register; the output end Q of the Mode reg register is connected with the selection end SEL2 of the selector MUX2; the pins EMIF2IO of the EMIF2 controller and the pins EMIF1IO of the EMIF1 controller are respectively connected with the input end of the selector MUX2, and the output end of the selector MUX2 is used as an external pin EMIFIO MUX;

when the reset signal RSTN is 0, the input SEL1 of the selector MUX1 is 0, the MUX1 outputs a MODE pin signal to a MODE reg register, the Q terminal of the MODE reg register controls the selection terminal SEL2 of the selector MUX2, and the MUX2 connects the intra-chip EMIF1IO signal or the EMIF2IO signal with the emiio MUX pin, depending on whether the MODE signal is 0 or 1; when the reset signal RSTN is 1, the selector MUX1 selects the input terminal D of the Mode reg to which the bus access control output signal is given, the Q of the Mode reg outputs the value of the terminal D at the next clock rising edge, the selection terminal SEL2 of the selector MUX2 is controlled to be 0 or 1, depending on the bus configuration information being 0 or 1, the MUX2 connects the internal EMIF1IO signal or the internal EMIF2IO signal of the chip with the emiio MUX pin according to the configuration information, so that the Mode pin selects the EMIF IO MUX control right during the reset period when the RSTN is 0, and the bus access selects the EMIF IO MUX control right after the RSTN is 1 reset.

8. The SoC architecture based on the core-R4 architecture of claim 1, wherein the external pin MODE directly drives the LOCZRAMA signal to the system processor.

9. The SoC architecture based on CORTEX-R4 architecture as recited in claim 1, wherein

Is characterized in that when the MODE input pin is 0, the test MODE is used for carrying out ATE on-line test,

or for application scenarios that do not require external large capacity off-chip memory; when the MODE input pin is 1,

the function mode is used for meeting the use requirement of the SoC external high-capacity off-chip memory.