CN117573458A - Debugging device and method for memory bank slot - Google Patents

Debugging device and method for memory bank slot Download PDF

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Publication number
CN117573458A
CN117573458A CN202311512858.1A CN202311512858A CN117573458A CN 117573458 A CN117573458 A CN 117573458A CN 202311512858 A CN202311512858 A CN 202311512858A CN 117573458 A CN117573458 A CN 117573458A
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China
Prior art keywords
control circuit
load
debugging
capacitance
load access
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Inventor
许超超
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Shenzhen Guoxin Hengyun Information Security Co ltd
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Shenzhen Guoxin Hengyun Information Security Co ltd
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Priority to CN202311512858.1A priority Critical patent/CN117573458A/en
Publication of CN117573458A publication Critical patent/CN117573458A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2247—Verification or detection of system hardware configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The invention provides a debugging device and a debugging method installed in a memory bank slot, comprising the following steps: the device comprises a power supply end, a load control circuit, a capacitance control circuit and an MCU main control unit, wherein one ends of the load control circuit and the capacitance control circuit are connected to a power supply pin of a memory bank slot, and the other ends of the load control circuit and the capacitance control circuit are connected to a ground wire; the load control circuit comprises at least two paths of resistive load access loops which are mutually connected in parallel, and different resistive load access loops comprise resistors with different powers; the capacitive load access circuit comprises at least two capacitive load access circuits which are connected in parallel, and different capacitive load access circuits respectively comprise capacitors with different capacitance values; and the control ends of each path of the resistive load access loop and the capacitive load access loop are respectively connected to the MCU main control unit. The invention can realize the debugging of control parameters through the USB interface, effectively reduce the debugging cost and shorten the research and development period.

Description

Debugging device and method for memory bank slot
Technical Field
The invention relates to a debugging device, in particular to a debugging device installed in a memory bank slot, and further relates to a debugging method of the debugging device installed in the memory bank slot.
Background
At present, in a personal computer and a server, a problem of abnormal work caused by combination and collocation of special components is sometimes encountered, such as a problem of abnormal work caused by collocation of components such as a processor, a memory, a display card, a power module and the like, but any one of the components is normal in practice, namely, one of the components can work normally when being switched to a manufacturer or a model, and the special phenomenon is simply called a system resonance phenomenon, and belongs to one of the phenomena in system compatibility.
Currently, it is common in the industry to circumvent this by modifying the list of parts that can support the product or the default configuration. Or to modify the PCB circuit board to accommodate more configuration scenarios. However, in this way of modifying the PCB, on one hand, if modification is to be performed, the corresponding hardware motherboard circuit must face a new round of PCB design, PCB fabrication, and PCB verification, which requires a lot of manpower and material resources, and has a long period; on the other hand, the problem of need of replacing the motherboard suppliers may be caused, the uncertain influence is brought to the stability of the product, and the problem of economic loss may be caused.
Disclosure of Invention
The invention aims to solve the technical problem of providing a debugging device installed in a memory bank slot, so that the debugging of control parameters can be realized through the memory bank slot, the debugging requirement of system compatibility can be met on the basis of not modifying the original design of a product, the hardware design of the product is not required to be replaced, the cost of the product is effectively reduced, and the research and development period is shortened. On the basis, a debugging method of the debugging device installed in the memory bank slot is further provided.
In view of the above, the present invention provides a debug apparatus mounted in a memory slot, comprising: the device comprises a power supply end, a load control circuit, a capacitance control circuit and an MCU main control unit, wherein one end of the load control circuit and one end of the capacitance control circuit are respectively connected to a power supply pin of a memory bank slot through the power supply end, and the other end of the load control circuit and the other end of the capacitance control circuit are respectively connected to a ground wire of the memory bank slot through a ground terminal; the load control circuit comprises at least two paths of resistive load access loops which are mutually connected in parallel, and different resistive load access loops respectively comprise resistors with different powers; the capacitive load access circuit comprises at least two capacitive load access circuits which are connected in parallel, and different capacitive load access circuits respectively comprise capacitors with different capacitance values; the control ends of each path of the resistive load access loop and the capacitive load access loop are respectively connected to the MCU main control unit; when the power is first applied, the MCU main control unit closes all the resistive load access loops and the capacitive load access loops through the control end, and after the power is applied and the debugging is completed, the current control parameters of the load control circuit and the capacitive control circuit are stored as set values; when the power is supplied again, the MCU master control unit reads the set value first and controls the switches of the load control circuit and the capacitance control circuit respectively according to the set value.
The MCU main control unit comprises a debugging control interface, wherein the debugging control interface is connected to the control ends of the resistive load access loop and the capacitive load access loop through GPIO buses.
The MCU main control unit is connected to the terminal equipment through the USB interface, and the terminal equipment comprises a computer and is convenient to connect and operate.
The invention further improves that the load control circuit comprises four paths of resistive load access loops which are mutually connected in parallel, the first path of resistive load access loop comprises a resistor R1, a MOS switch tube Q1, a resistor R5 and a resistor R6, a G pole of the MOS switch tube Q1 is connected to the MCU main control unit through the resistor R6, a connection point of the G pole of the MOS switch tube Q1 and the resistor R6 is connected with one end of the resistor R5, an S pole of the MOS switch tube Q1 and the other end of the resistor R5 are connected with the power supply end, and a D pole of the MOS switch tube Q1 is grounded through the resistor R1.
A further improvement of the invention is that the four-way resistive load access loop comprises resistors with powers of 5W, 10W, 20W and 50W, respectively.
The invention is further improved in that the capacitance control circuit comprises four capacitive load access loops which are mutually connected in parallel, the first capacitive load access loop comprises a resistor R13, a MOS switch tube Q5, a resistor R14 and a capacitor C1, a G pole of the MOS switch tube Q5 is connected to the MCU main control unit through the resistor R14, a connection point of the G pole of the MOS switch tube Q5 and the resistor R14 is connected with one end of the resistor R13, an S pole of the MOS switch tube Q5 and the other end of the resistor R13 are connected with the power supply end, and a D pole of the MOS switch tube Q5 is grounded through the capacitor C1.
A further development of the invention is that the capacitive load access loop comprises capacitances with capacitance values of 22uF, 47uF, 100uF and 470uF, respectively.
The invention also provides a debugging method for the memory bank slot, which adopts the debugging device installed in the memory bank slot and comprises the following steps:
step S1, inserting the debugging device installed in the memory slot into the memory slot of the main board;
step S2, powering up and starting up the main board;
step S3, checking an operating system log, judging whether the current state is normal starting, if not, jumping to the step S4; if yes, ending the debugging;
step S4, gradually increasing the load capacity value accessed by the capacitance control circuit, judging whether the current state is normal starting up or not, and storing the current control parameters as set values and ending debugging until the current state is normal starting up; otherwise, jumping to the step S5;
step S5, the load power accessed by the resistance control circuit is regulated up, whether the current state is normal startup or not is judged, the current control parameter is saved as a set value until the normal startup is achieved, and the debugging is finished; otherwise, jumping to the step S6;
step S6, comprehensively adjusting the load power accessed by the resistance control circuit and the load capacity accessed by the capacitance control circuit, judging whether the current state is normal starting up or not, and storing the current control parameters as set values and ending debugging until the current state is normal starting up; otherwise, sending out error prompt information.
The invention further improves that the process for judging whether the current state is normal startup comprises the following steps: judging whether the system is restarted regularly, judging whether a hardware module of the system is initialized normally, judging whether the voltage value on a power supply branch fluctuates by more than +/-5%, and judging that the system is not started normally if any abnormality occurs, wherein the hardware module comprises a memory module, a hard disk module and a display card module.
The invention further improves that in the step S6, the load power accessed by the resistance control circuit and the load capacitance accessed by the capacitance control circuit are comprehensively adjusted, and the method comprises any one of the following substeps:
step S601, after the load power accessed by the resistance control circuit is firstly increased, the load capacitance accessed by the capacitance control circuit is then increased or decreased;
step S602, after the load capacity value accessed by the capacitance control circuit is firstly increased, the load power accessed by the resistance control circuit is increased or decreased;
step S603, inserting another memory bank slot into the debugging device installed in the memory bank slot, and repeating steps S2 to S5 for debugging again.
Compared with the prior art, the invention has the beneficial effects that: the load control circuit comprises at least two paths of resistive load access loops which are mutually connected in parallel, and different resistive load access loops respectively comprise resistors with different powers so as to access the resistive loads with different powers for the debugging process; the capacitive control circuit comprises at least two capacitive load access loops which are connected in parallel, and different capacitive load access loops respectively comprise capacitors with different capacitance values so as to access capacitive loads with different capacitance values for the debugging process; the control ends of each path of the resistive load access loop and the capacitive load access loop are respectively connected to the MCU main control unit; when the power is first applied, the MCU main control unit closes all the resistive load access loops and the capacitive load access loops through the control end, and after the power is applied and the debugging is completed, the current control parameters of the load control circuit and the capacitive control circuit are stored as set values; when the MCU is electrified again, the MCU master control unit reads the set value first, and controls the switches of the load control circuit and the capacitance control circuit respectively according to the set value, so that the MCU master control unit can realize installation through a memory slot of the MCU master control unit on the basis of not modifying a part list or default configuration of a product, and realize debugging of control parameters through a USB interface, thereby meeting the adaptation and debugging requirements of system compatibility, realizing simple and efficient process, effectively reducing the cost of the product and shortening the research and development period of the product.
Drawings
FIG. 1 is a schematic block diagram of a circuit design of one embodiment of the present invention;
FIG. 2 is a circuit schematic of a load control circuit according to one embodiment of the invention;
FIG. 3 is a circuit schematic of a capacitance control circuit according to one embodiment of the present invention;
FIG. 4 is a schematic workflow diagram of one embodiment of the present invention.
Description of the drawings: 1-a power supply terminal; 2-a load control circuit; 201-resistive load access loop; a 3-capacitance control circuit; 301-capacitive load access loop; 4-MCU master control unit; 5-a ground terminal; 6-USB interface.
Detailed Description
In the description of the invention, if reference is made to "a number", it means more than one; if "a plurality" is referred to, it means more than two; if "greater than", "less than", "exceeding" are referred to, they are understood to not include the present number; references to "above," "below," "within," and "within" are to be construed as including the present number. If reference is made to "first," "second," etc., it is to be understood that the same or similar technical feature names are used only for distinguishing between them, and it is not to be understood that the relative importance of a technical feature is implied or indicated, or that the number of technical features is implied or indicated, or that the precedence of technical features is implied or indicated.
Preferred embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
As shown in fig. 1 to 3, the present embodiment provides a debug apparatus installed in a memory slot, including: the power supply terminal 1, the load control circuit 2, the capacitance control circuit 3 and the MCU master control unit 4. One end of the load control circuit 2 and one end of the capacitance control circuit 3 are respectively connected to a power pin of the memory slot through the power end 1, and the other end of the load control circuit 2 and the other end of the capacitance control circuit 3 are respectively connected to a ground wire of the memory slot through a ground end 5; the load control circuit 2 comprises at least two paths of resistive load access loops 201 which are connected in parallel, and different resistive load access loops 201 respectively comprise resistors with different powers; the capacitance control circuit 3 comprises at least two capacitive load access loops 301 which are connected in parallel, and different capacitive load access loops 301 respectively comprise capacitances with different capacitance values; the control ends of each path of the resistive load access loop 201 and the capacitive load access loop 301 are respectively connected to the MCU main control unit 4. When the power is first turned on, the MCU master control unit 4 closes all the resistive load access loops 201 and the capacitive load access loops 301 through the control end, and after the power is turned on and the debugging is completed, the current control parameters of the load control circuit 2 and the capacitive control circuit 3 are stored as set values; when the power is turned on again, the MCU master control unit 4 reads the set value first and controls the switch of the load control circuit 2 and the switch of the capacitance control circuit 3 respectively according to the set value. The control parameters refer to GPIO control signals respectively corresponding to the control ends of the resistive load access loop 201 and the capacitive load access loop 301, wherein a high level indicates that the corresponding resistive load access loop 201 or capacitive load access loop 301 is closed, and a low level indicates that the corresponding resistive load access loop 201 or capacitive load access loop 301 is opened.
As shown in fig. 2 and 3, the MCU master control unit 4 of the present embodiment preferably includes a debug control interface, where the debug control interface is a GPIO interface, and the debug control interface is connected to the control ends of the resistive load access loop 201 and the capacitive load access loop 301 through a GPIO bus. As shown in fig. 1, the MCU master control unit 4 of the present embodiment further preferably includes a USB interface 6, and the MCU master control unit 4 is connected to a terminal device including a computer through the USB interface 6. The MCU master control unit 4 refers to an MCU integrated chip.
In this embodiment, the MCU of the MCU master control unit 4 preferably controls the capacitance and the load size of the 12V main power supply loop through a MOS switch tube. The available computer is connected to the debugging device of the embodiment through the USB interface, and parameters such as capacitive reactance, load and the like can be set when the computer works, so that the computer has the advantages of low cost, convenience in operation and wide parameter adjusting range.
As shown in fig. 2, the load control circuit 2 of this embodiment includes four paths of resistive load access loops 201 connected in parallel, where the first path of resistive load access loop 201 includes a resistor R1, a MOS switch tube Q1, a resistor R5, and a resistor R6, a G pole of the MOS switch tube Q1 is connected to the MCU main control unit 4 through the resistor R6, a connection point between the G pole of the MOS switch tube Q1 and the resistor R6 is connected to one end of the resistor R5, an S pole of the MOS switch tube Q1 and the other end of the resistor R5 are connected to the power supply terminal 1, and a D pole of the MOS switch tube Q1 is grounded through the resistor R1. The four-way resistive load access loop 201 of the present embodiment preferably includes resistors with power of 5W, 10W, 20W, and 50W, respectively. VCC represents the positive pole of the DC power obtained from the power supply pin of the memory slot, and GND represents the negative pole.
When the MCU master control unit 4 drives the control end GPIO1 of the first resistive load access loop 201 to be in a low level, the MOS switch tube Q1 is conducted, and a 5W resistive load is accessed to the main board power supply loop; when the MCU master control unit 4 drives the control end GPIO2 of the second resistive load access loop 201 to be in a low level, the MOS switch tube Q2 is conducted, and a 10W resistive load is accessed to the main board power supply loop; when the MCU master control unit 4 drives the control end GPIO3 of the third resistive load access loop 201 to be in a low level, the MOS switch tube Q3 is conducted, and a 20W resistive load is accessed to the main board power supply loop; when the MCU master control unit 4 drives the control terminal GPIO4 of the fourth resistive load access loop 201 to be at a low level, the MOS switch Q4 is turned on, and a 50W resistive load is connected to the main board power supply loop. When more than two paths and more than two paths of the resistive load access loops 201 are simultaneously opened, the resistive load added to the main board is the sum of the loads of the opened resistive load access loops 201.
As shown in fig. 3, the capacitance control circuit 3 in this embodiment includes four capacitive load access loops 301 connected in parallel, the first capacitive load access loop 301 includes a resistor R13, a MOS switch tube Q5, a resistor R14, and a capacitor C1, a G pole of the MOS switch tube Q5 is connected to the MCU main control unit 4 through the resistor R14, a connection point between the G pole of the MOS switch tube Q5 and the resistor R14 is connected to one end of the resistor R13, an S pole of the MOS switch tube Q5 and the other end of the resistor R13 are connected to the power supply terminal 1, and a D pole of the MOS switch tube Q5 is grounded through the capacitor C1. The capacitive load access loop 301 in this embodiment includes capacitors having capacitance values of 22uF, 47uF, 100uF, and 470uF, respectively.
When the MCU master control unit 4 drives the control end GPIO5 of the first capacitive load access loop 301 to be at a low level, the MOS switch tube Q5 is conducted, and one 22uF capacitive load is accessed to the main board power supply loop; when the MCU master control unit 4 drives the control end GPIO6 of the second capacitive load access loop 301 to be in a low level, the MOS switch tube Q6 is conducted, and a 47uF capacitive load is accessed to the main board power supply loop; when the MCU master control unit 4 drives the control end GPIO7 of the third capacitive load access loop 301 to be at a low level, the MOS switch tube Q7 is conducted, and a 100uF capacitive load is accessed to the main board power supply loop; when the MCU master control unit 4 drives the control terminal GPIO8 of the fourth capacitive load access circuit 301 to be at a low level, the MOS switch Q8 is turned on, and a 470uF capacitive load is connected to the main board power supply circuit. When two or more capacitive load access loops 301 are simultaneously opened, the capacitance added to the motherboard is the sum of the capacitance values of the opened capacitive load access loops 301.
As shown in fig. 4, the present embodiment further provides a method for debugging a memory bank slot, which adopts the debugging device installed in the memory bank slot as described above, and includes the following steps:
step S1, inserting the debugging device installed in the memory slot into the memory slot of the main board;
step S2, powering up and starting up the main board;
step S3, checking an operating system log, judging whether the current state is normal starting, if not, jumping to the step S4; if yes, ending the debugging; said debugging is also called adaptation debugging;
step S4, gradually increasing the load capacity value accessed by the capacitance control circuit 3, judging whether the current state is normal starting up or not, and storing the current control parameters as set values and ending debugging until the current state is normal starting up; otherwise, jumping to the step S5;
step S5, the load power accessed by the resistance control circuit is regulated up, whether the current state is normal startup or not is judged, the current control parameter is saved as a set value until the normal startup is achieved, and the debugging is finished; otherwise, jumping to the step S6;
step S6, comprehensively adjusting the load power accessed by the resistance control circuit and the load capacity accessed by the capacitance control circuit 3, judging whether the current state is normal starting up or not, and storing the current control parameters as set values and ending debugging until the current state is normal starting up; otherwise, sending out error prompt information.
The process of judging whether the current state is normal startup in this embodiment includes: judging whether the system is restarted regularly, judging whether a hardware module of the system is initialized normally and judging whether the voltage value on a power supply branch fluctuates by more than +/-5%, if any abnormality occurs, judging that the system is not started normally, wherein the hardware module comprises a memory module, a hard disk module and a display card module, and if the initialization fails, judging that the system is abnormal; if the regular restarting occurs, judging that the operation is abnormal; if the voltage value on the power supply branch fluctuates by more than + -5%, the abnormality is judged.
In step S6 of the present embodiment, the comprehensive adjustment of the load power accessed by the resistance control circuit and the load capacitance accessed by the capacitance control circuit 3 includes any one of the following sub-steps:
step S601, after the load power accessed by the resistance control circuit is first turned up, the load capacitance accessed by the capacitance control circuit 3 is turned up or turned down; the power of the accessed load is adjusted up or down, and the operation can be realized by opening or closing one or more corresponding resistive load access loops 201; the load capacity value of the access is adjusted up or down, and the operation can be realized by opening or closing one or more corresponding capacitive load access loops 301;
step S602, after the load capacity value accessed by the capacitance control circuit 3 is first turned up, the load power accessed by the resistance control circuit is turned up or turned down;
step S603, inserting another memory bank slot into the debugging device installed in the memory bank slot, and repeating steps S2 to S5 for debugging again.
In summary, the load control circuit 2 of the present embodiment includes at least two paths of resistive load access loops 201 connected in parallel, and different resistive load access loops 201 respectively include resistors with different powers so as to access resistive loads with different powers for the debugging process; the capacitance control circuit 3 comprises at least two capacitive load access loops 301 which are connected in parallel, and different capacitive load access loops 301 respectively comprise capacitances with different capacitance values so as to access capacitive loads with different capacitance values for the debugging process; the control ends of each path of the resistive load access loop 201 and the capacitive load access loop 301 are respectively connected to the MCU master control unit 4; when the power is first turned on, the MCU master control unit 4 closes all the resistive load access loops 201 and the capacitive load access loops 301 through the control end, and after the power is turned on and the debugging is completed, the current control parameters of the load control circuit 2 and the capacitive control circuit 3 are stored as set values; when the MCU is powered on again, the MCU main control unit 4 reads the set value first, and controls the switch of the load control circuit 2 and the switch of the capacitance control circuit 3 according to the set value respectively, so that the installation can be realized through the memory slot of the MCU main control unit on the basis of not modifying the component list or default configuration of the product, the debugging of control parameters is realized through the USB interface, the adaptation and debugging requirements of the system compatibility are met, the realization process is simple and efficient, the cost of the product can be effectively reduced, and the research and development period of the product is shortened.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.

Claims (10)

1. A debug apparatus mounted in a memory stick socket, comprising: the device comprises a power supply end, a load control circuit, a capacitance control circuit and an MCU main control unit, wherein one end of the load control circuit and one end of the capacitance control circuit are respectively connected to a power supply pin of a memory bank slot through the power supply end, and the other end of the load control circuit and the other end of the capacitance control circuit are respectively connected to a ground wire of the memory bank slot through a ground terminal; the load control circuit comprises at least two paths of resistive load access loops which are mutually connected in parallel, and different resistive load access loops respectively comprise resistors with different powers; the capacitive load access circuit comprises at least two capacitive load access circuits which are connected in parallel, and different capacitive load access circuits respectively comprise capacitors with different capacitance values; the control ends of each path of the resistive load access loop and the capacitive load access loop are respectively connected to the MCU main control unit; when the power is first applied, the MCU main control unit closes all the resistive load access loops and the capacitive load access loops through the control end, and after the power is applied and the debugging is completed, the current control parameters of the load control circuit and the capacitive control circuit are stored as set values; when the power is supplied again, the MCU master control unit reads the set value first and controls the switches of the load control circuit and the capacitance control circuit respectively according to the set value.
2. The device according to claim 1, wherein the MCU main control unit includes a debug control interface connected to control ends of the resistive load access loop and the capacitive load access loop through GPIO buses.
3. The debugging device installed in a memory stick slot of claim 1, wherein the MCU main control unit further comprises a USB interface, the MCU main control unit is connected to a terminal device through the USB interface, and the terminal device comprises a computer.
4. The debugging device installed in a memory slot according to any one of claims 1 to 3, wherein the load control circuit comprises four paths of resistive load access loops connected in parallel, the first path of resistive load access loop comprises a resistor R1, a MOS switch tube Q1, a resistor R5 and a resistor R6, a G pole of the MOS switch tube Q1 is connected to the MCU main control unit through the resistor R6, a connection point of the G pole of the MOS switch tube Q1 and the resistor R6 is connected to one end of the resistor R5, an S pole of the MOS switch tube Q1 and the other end of the resistor R5 are connected to the power supply terminal, and a D pole of the MOS switch tube Q1 is grounded through the resistor R1.
5. The debug apparatus installed in a memory stick socket as claimed in claim 4, wherein four of the resistive load access loops comprise resistors with power of 5W, 10W, 20W and 50W, respectively.
6. The debugging device installed in a memory slot according to any one of claims 1 to 3, wherein the capacitance control circuit comprises four capacitive load access loops connected in parallel, the first capacitive load access loop comprises a resistor R13, a MOS switch tube Q5, a resistor R14 and a capacitor C1, a G pole of the MOS switch tube Q5 is connected to the MCU main control unit through the resistor R14, a connection point between the G pole of the MOS switch tube Q5 and the resistor R14 is connected to one end of the resistor R13, an S pole of the MOS switch tube Q5 and the other end of the resistor R13 are connected to the power supply end, and a D pole of the MOS switch tube Q5 is grounded through the capacitor C1.
7. The device of claim 6, wherein the capacitive load access loop includes capacitors having capacitance values of 22uF, 47uF, 100uF, and 470uF, respectively.
8. A debug method for mounting in a memory stick slot, characterized in that a debug apparatus for mounting in a memory stick slot according to any one of claims 1 to 7 is employed, and comprising the steps of:
step S1, inserting the debugging device installed in the memory slot into the memory slot of the main board;
step S2, powering up and starting up the main board;
step S3, checking an operating system log, judging whether the current state is normal starting, if not, jumping to the step S4; if yes, ending the debugging;
step S4, gradually increasing the load capacity value accessed by the capacitance control circuit, judging whether the current state is normal starting up or not, and storing the current control parameters as set values and ending debugging until the current state is normal starting up; otherwise, jumping to the step S5;
step S5, the load power accessed by the resistance control circuit is regulated up, whether the current state is normal startup or not is judged, the current control parameter is saved as a set value until the normal startup is achieved, and the debugging is finished; otherwise, jumping to the step S6;
step S6, comprehensively adjusting the load power accessed by the resistance control circuit and the load capacity accessed by the capacitance control circuit, judging whether the current state is normal starting up or not, and storing the current control parameters as set values and ending debugging until the current state is normal starting up; otherwise, sending out error prompt information.
9. The method of claim 8, wherein the step of determining whether the current state is normal power-on comprises: judging whether the system is restarted regularly, judging whether a hardware module of the system is initialized normally, judging whether the voltage value on a power supply branch fluctuates by more than +/-5%, and judging that the system is not started normally if any abnormality occurs, wherein the hardware module comprises a memory module, a hard disk module and a display card module.
10. The method for debugging a memory slot according to claim 8, wherein in step S6, the load power accessed by the resistance control circuit and the load capacitance accessed by the capacitance control circuit are comprehensively adjusted, and the method comprises any one of the following sub-steps:
step S601, after the load power accessed by the resistance control circuit is firstly increased, the load capacitance accessed by the capacitance control circuit is then increased or decreased;
step S602, after the load capacity value accessed by the capacitance control circuit is firstly increased, the load power accessed by the resistance control circuit is increased or decreased;
step S603, inserting another memory bank slot into the debugging device installed in the memory bank slot, and repeating steps S2 to S5 for debugging again.
CN202311512858.1A 2023-11-14 2023-11-14 Debugging device and method for memory bank slot Pending CN117573458A (en)

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CN202311512858.1A CN117573458A (en) 2023-11-14 2023-11-14 Debugging device and method for memory bank slot

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Publication Number Publication Date
CN117573458A true CN117573458A (en) 2024-02-20

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