CN117560011A

CN117560011A - Digital-to-analog converter, digital-to-analog conversion circuit and electronic equipment

Info

Publication number: CN117560011A
Application number: CN202210930195.4A
Authority: CN
Inventors: 弋才敏
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-08-03
Filing date: 2022-08-03
Publication date: 2024-02-13
Also published as: WO2024027377A1

Abstract

The embodiment of the application provides a digital-to-analog converter, a digital-to-analog conversion circuit and electronic equipment; the method is used in the field of digital signal processing. The digital-to-analog converter comprises a first resistor and a first switch which are connected in parallel. The first switch and the first resistor are corresponding to each code bit of the digital signal. And the first voltage or the second voltage representing different values of the code bit is input through the first switch, and the first voltage or the second voltage is output to the first resistor through the third end of the first switch according to the value of the code bit corresponding to the digital signal through the controlled end of the first switch. The second ends of all the first resistors are coupled to the first coupling point, and analog signals corresponding to each code bit of the digital signals are output to the first coupling point. The digital-to-analog converter provided by the embodiment of the application has the advantages that the output impedance is low, the resistance value is constant, and the application of the digital-to-analog converter under high speed and high precision is realized.

Description

Digital-to-analog converter, digital-to-analog conversion circuit and electronic equipment

Technical Field

The present disclosure relates to digital signal processing chips, and particularly to a digital-to-analog converter, a digital-to-analog conversion circuit, and an electronic device.

Background

Digital-to-analog converters (DACs) are indispensable in the field of electronic devices today as devices for converting digital signals into analog voltage signals. Common digital-to-analog converters include current-mode digital-to-analog converters (IDACs) and resistive digital-to-analog converters (RDACs). With the development of chips, the requirements on the processing speed and the processing precision of digital signals are also higher and higher. In processing scenarios where high-rate, high-precision processing of digital signals is required, current-mode digital-to-analog converters are often employed.

In a processing scenario requiring a high rate, it is often necessary to reduce the output impedance by reducing the resistance of the resistor, thereby increasing the rate of signal processing. The use of a smaller resistance resistor will in turn increase the effect of the on-resistance of the over-current switch in the resistive digital-to-analog converter on the linearity of the digital-to-analog converter. If the size of the over-current switch is increased to reduce the influence of on-resistance on the linearity of the digital-to-analog converter, a larger parasitic capacitance is generated due to the increased size of the over-current switch. Therefore, in the existing application, it is difficult to realize the high-speed and high-precision resistor-type digital-to-analog converter.

Disclosure of Invention

The embodiment of the application provides a digital-to-analog converter, a digital-to-analog conversion circuit and electronic equipment, which realize that the resistive digital-to-analog converter has high speed and high precision.

In order to achieve the above purpose, the embodiments of the present application adopt the following technical solutions:

in a first aspect, a digital-to-analog converter is provided, the digital-to-analog converter includes a first voltage terminal, a second voltage terminal, a control unit, and a first conversion unit, the first conversion unit includes N first switches, N first resistors; the first voltage terminal is used for inputting a first voltage; the second voltage terminal is used for inputting a second voltage; the control unit is used for receiving a first digital signal, the first digital signal comprises N code bits which are in one-to-one correspondence with the N first switches, and the control unit is used for respectively controlling the N first switches according to the N code bits of the first digital signal, so that the first ends of the first resistors corresponding to the N first switches are coupled to the first voltage end or the second voltage end; the second ends of the N first resistors are coupled to the first coupling point; the first coupling point is used for outputting first analog signals corresponding to N code bits of the first digital signals.

In this embodiment of the present application, the N first resistors respectively correspond to different code bits of the N code bits of the input first digital signal, so as to input the first voltage or the second voltage of the first resistor to the value of the N code bits of the first digital signal. The embodiment of the application is general By coupling the second ends of the first resistors to the first coupling point, an equivalent parallel connection of N first resistors is achieved. At this time, all the first resistors can be equivalently connected in parallel, and no matter the corresponding first resistor inputs the first voltage or the second voltage, the corresponding first resistor provides the resistance value for the whole first conversion unit, so the equivalent resistance value R of the first conversion unit ₁ The resistance value of the first resistors after being equivalently connected in parallel is smaller than that of the first resistors and is a constant resistance value. Further, when the N code bits of the first digital signal are the fixed input binary code, the output impedance rout=r of the first conversion unit ₂ 2, wherein R is ₂ The resistance value of the first resistor corresponding to the highest code bit in the N code bits of the first digital signal. When the N code bits of the first digital signal are thermometer codes with fixed input, the output impedance rout=R of the first conversion unit ₃ /2 ^N ，R ₃ The resistance value of the first resistor corresponding to the highest code bit in the N code bits of the first digital signal. It can be seen that the output impedance of the first conversion unit is small and constant at this time. Under the application of the embodiment of the application, the resistor with a larger resistance value can be adopted in the first resistor, and under the condition that the resistance value of the resistor is not required to be reduced, stable and very small output impedance is obtained, and under the condition that an overcurrent switch with a larger size is avoided, high-precision and high-speed digital-to-analog conversion can be realized.

In one possible implementation, the first digital signal further includes E code bits, the E code bits of the first digital signal being lower than the N code bits of the first digital signal; the digital-to-analog converter also comprises a resistor voltage division unit and a second conversion unit; the second conversion unit comprises N second switches and N second resistors; the control unit is also used for generating a second digital signal according to the first digital signal; the control unit respectively controls the N second switches according to the N code bits of the second digital signal, so that the first ends of the second resistors corresponding to the N second switches are coupled to the first voltage end or the second voltage end; the second ends of the N second resistors are coupled to a second coupling point; the second coupling point is used for outputting a second analog signal corresponding to the second digital signal; the value of the second digital signal is larger than that of the first digital signal; the first input end of the resistor voltage division unit is coupled to the first coupling point and used for inputting a first analog signal, and the second input end of the resistor voltage division unit is coupled to the second coupling point and used for inputting a second analog signal; the control unit is used for controlling the output end of the resistor voltage division unit to output a third analog signal corresponding to the sum of the N code bits of the first digital signal and the E code bits of the first digital signal according to the E code bits of the first digital signal.

In the embodiment of the application, the digital signal including a plurality of bits is segmented into N code bits of the first digital signal of the high code bit segment and E code bits of the first digital signal of the low code bit segment, and at the same time, a second digital signal is generated, where the second digital signal also includes N code bits, and the value of the N code bits of the second digital signal is greater than the value of the N code bits of the first digital signal. And generating a first analog signal corresponding to N code bits of the first digital signal through the first conversion unit, and generating a second analog signal corresponding to N code bits of the second digital signal through the second conversion unit. The first analog signal is output to a first input end of the resistor divider unit through a first coupling point; the second analog signal is output to the second input end of the resistor divider unit through the second coupling point. The third coupling point is used as an output end of the digital-to-analog converter to output a third analog signal, and the third analog signal is used for expressing the analog signal corresponding to the combination of N code bits of the first digital signal of the high code bit section and E code bits of the first digital signal of the low code bit section into the digital signal of the multi-code bit section. E code bits of the first digital signal are used as digital signals of low code bit sections and used for controlling the resistance values of the first resistor module and the second resistor module. When the value of the E code bits of the first digital signal is lower, the output third analog signal is more similar to the first analog signal. When the value of the E code bits of the first digital signal is higher, the output third analog signal is more similar to the second analog signal.

In one possible implementation manner, the resistor voltage dividing unit specifically includes an output selection switch and E third resistors; one end of the E third resistors after being connected in series is used as a first input end of the resistor voltage dividing unit to be coupled with a first coupling point, and the other end of the E third resistors after being connected in series is used as a second input end of the resistor voltage dividing unit to be coupled with a second coupling point; the control unit is used for coupling the selection input end of the output selection switch to a third coupling point according to the value of E code bits of the first digital signal, wherein the third coupling point is the first end or the second end of one of E third resistors, and the sum of the resistance values of all the third resistors between the third coupling point and the first coupling point corresponds to the value of E code bits of the first digital signal.

In the embodiment of the application, in the E third resistors, a third resistor coupling point is arranged between two adjacent third resistors, and then the E third resistors have E-1 third resistor coupling points, and in the E third resistors which are connected in series, the head and the tail of each third resistor are respectively provided with an endpoint which is not connected with other third resistors. E-1 third resistance coupling points are added with the two end points from the beginning to the end, E end points can be obtained, and one of the E end points is used as the third coupling point according to the value of E code bits of the first digital signal. When the value of the E code bits of the first digital signal is smaller, the third coupling point is closer to the first coupling point, and conversely, the third coupling point is closer to the second coupling point. In this embodiment of the present application, by adjusting the coupling position of the output selection switch, that is, the position of the third coupling point, the number of third resistors between the second coupling point and the third coupling point is reduced, thereby reducing the resistance value of the second resistor module located between the second coupling point and the third coupling point, and increasing the resistance value of the first resistor module located between the first coupling point and the third coupling point. When the value of the E code bits of the first digital signal is higher, the output third analog signal is more similar to the second analog signal.

In one possible implementation, the digital-to-analog converter further includes a first bridge resistor; the output end of the first conversion unit is coupled to the first input end of the resistor voltage division unit through a first bridge resistor.

In this embodiment, when the digital-to-analog converter includes the first bridge resistor, a sum of an equivalent resistance of the first conversion unit plus an equivalent resistance of the second conversion unit and a resistance of the first bridge resistor is equal to a resistance of a third resistor. At this time, by adjusting the resistance of the first bridge resistor, the equivalent resistances of the first conversion unit and the second conversion unit can be increased or decreased appropriately, and the resistances of the first resistor and the second resistor can be set better.

In one possible implementation, the digital-to-analog converter further includes a second bridge resistor; the output end of the second conversion unit is coupled to the second end of the second resistor module through a second bridge resistor.

In this embodiment, when the digital-to-analog converter includes the second bridge resistor, a sum of the equivalent resistance of the first conversion unit and the equivalent resistance of the second conversion unit and the resistance of the second bridge resistor is equal to the resistance of a third resistor. At this time, by adjusting the resistance of the second bridge resistor, the equivalent resistances of the first conversion unit and the second conversion unit can be increased or decreased appropriately, and the resistances of the first resistor and the second resistor can be set better. Similarly, when the digital-to-analog converter includes the second bridge resistor, the sum of the equivalent resistance of the first conversion unit plus the equivalent resistance of the second conversion unit and the resistance of the first bridge resistor and the resistance of the second bridge resistor is equal to the resistance of a third resistor. At this time, by adjusting the resistances of the first bridge resistor and the second bridge resistor, the equivalent resistances of the first conversion unit and the second conversion unit can be increased or decreased appropriately, and the resistances of the first resistor and the second resistor can be set better.

In one possible implementation, the E code bits of the first digital signal are thermometer codes; the resistance values of the E third resistors are equal.

In this embodiment of the present application, each code bit of the thermometer code corresponds to a third resistor, and the resistance values of the third resistors are equal. And when the resistance values of the third resistors are overlapped, the different values are overlapped correspondingly. The third resistors with the same resistance values under the thermometer codes can reduce the overlarge deviation of the analog signals output by overlarge voltage or current when the third resistors with different resistance values output different voltages or currents as analog signals, and generate larger interference on the whole analog signals.

In one possible implementation, the N code bits of the second digital signal are thermometer codes; the resistance values of the N second resistors are equal.

In the embodiment of the application, the resistances of the second resistors under the thermometer codes are equal, so that when the second resistors with different resistances output different voltages or currents as analog signals, the deviation of the analog signals output by the overlarge voltages or currents is overlarge, and the overall analog signals are greatly disturbed.

In one possible implementation, the N code bits of the second digital signal are binary codes; and the resistance value of the second resistor corresponding to the lower code bit of the adjacent code bits in the N code bits of the second digital signal is twice as high as that of the second resistor corresponding to the higher code bit of the adjacent code bits in the N code bits of the second digital signal.

In the embodiment of the application, the binary code is used as N code bits of the second digital signal, and the number of the corresponding second resistors is smaller than that of the thermometer codes, so that the binary code is suitable for the scenes with lower precision requirements and smaller required resistor numbers.

In one possible implementation, the first digital signal further includes M code bits; the M code bits of the first digital signal are higher than the E code bits of the first digital signal and lower than the N code bits of the first digital signal; the first conversion unit further comprises a first segmentation unit; the second conversion unit further comprises a second segmentation unit; the output end of the first segmentation unit and the first coupling point are coupled to the first input end of the resistor voltage division unit; the output end of the second conversion unit and the second coupling point are coupled to the second input end of the resistor voltage division unit; the control unit is also used for controlling the first segmentation unit to output a fourth analog signal corresponding to the M code bits of the first digital signal to the first input end of the resistor voltage division unit according to the M code bits of the first digital signal; generating M code bits of a second digital signal; the M code bits of the second digital signal are lower than the N code bits of the second digital signal; and controlling the second segmentation unit to output a fifth analog signal corresponding to the M code bits of the second digital signal to the second input end of the resistor voltage division unit according to the M code bits of the second digital signal.

In this embodiment, for example, there is a digital signal including a plurality of bits, the digital signal including a plurality of bits is segmented into N bits of a first digital signal of a high-bit section and M bits of a first digital signal of a low-bit section, the M bits of the first digital signal are input into a first segmentation unit of a parallel resistor segmentation circuit, so that a fourth analog signal corresponding to the M bits of the first digital signal of the low-bit section is output from the first segmentation unit, a first analog signal corresponding to the N bits of the first digital signal of the high-bit section is output from a first coupling point through cooperation of a first switch and a first resistor, and a sum of the first analog signal and the fourth analog signal is used for expressing an analog signal corresponding to the digital signal including a plurality of bits. Meanwhile, the second segmentation unit is correspondingly arranged in the second conversion unit, and N code bits of the second digital signal correspond to N code bits of the first digital signal in value, but the value of M code bits of the second digital signal is larger than that of M code bits of the first digital signal.

In one possible embodiment, the first and second segment units are parallel-type resistive segment units; the parallel resistor segmentation unit comprises M fourth switches and M fourth resistors, wherein the M fourth switches and the M fourth resistors are in one-to-one correspondence with M code bits of the first digital signal or M code bits of the second digital signal; the control unit is used for respectively controlling the M fourth switches according to the M code bits of the first digital signal or the M code bits of the second digital signal, so that the first ends of the fourth resistors corresponding to the M fourth switches are coupled to the first voltage end or the second voltage end; the second ends of the M fourth resistors are coupled to a fourth coupling point; the fourth coupling point is used for outputting a fourth analog signal corresponding to M code bits of the first digital signal or a fifth analog signal corresponding to M code bits of the second digital signal.

In the embodiment of the application, the parallel type resistor segmentation unit is realized in a mode that a plurality of fourth resistors are equivalently connected in parallel, so that the equivalent resistance value and the output impedance of the whole circuit can be kept constant.

In one possible embodiment, the parallel resistor segmentation unit further comprises a third bridge resistor; the fourth coupling point is coupled to the first end of the third bridge resistor; the second end of the third bridge resistor is used as the output end of the parallel resistor segmentation unit.

In this embodiment of the present application, the equivalent resistance of the parallel resistor segment circuit needs to be the resistance of the first resistor corresponding to the lowest bit of the N code bits of the first digital signal. Therefore, after the digital signal with multiple bits is segmented, the corresponding relation between the resistance values of the fourth resistor in the parallel resistor segmentation circuit and the first resistor in the first conversion unit needs to be adjusted. Because the equivalent resistance of the parallel resistor segment circuit is far smaller than the resistance of the fourth resistor corresponding to the highest code bit of the fourth digital signal (the fourth resistor with the smallest resistance under the binary code), the equivalent resistance of the parallel resistor segment circuit needs to be equal to the resistance of the first resistor corresponding to the lowest code bit of the N code bits of the first digital signal (the resistance of the first resistor with the largest resistance under the binary code). In this case, the fourth resistor needs to have a large resistance (particularly, when the fourth digital signal is a binary code, the resistance of the fourth resistor corresponding to the lowest bit of the fourth digital signal needs to be very large). Before the third bridge resistor is arranged, the equivalent resistance value of the parallel resistor segmentation circuit is the sum of the equivalent resistances of the fourth resistors connected in parallel. And after the third bridging resistor is arranged, the equivalent resistance of the parallel type resistor segmentation circuit is the sum of the equivalent resistances of the fourth resistors connected in parallel and the resistance of the third bridging resistor. Therefore, by setting the third bridge resistor, the fourth resistor with an overlarge resistance value is not required to be set in the segmentation process, the realization possibility of the scheme is increased, meanwhile, the setting of the corresponding relation of the resistance values between the fourth resistor and the first resistor is more flexible, and the resistance value of the third bridge resistor can be adjusted adaptively.

In one possible implementation, the M code bits of the first digital signal or the M code bits of the second digital signal are binary codes; among the M fourth resistors, between two fourth resistors corresponding to adjacent code bits of the M code bits of the first digital signal or the M code bits of the second digital signal, the resistance of the fourth resistor corresponding to the lower code bit of the adjacent code bits of the M code bits of the first digital signal or the M code bits of the second digital signal is twice the resistance of the fourth resistor corresponding to the higher code bit of the adjacent code bits of the M code bits of the first digital signal or the M code bits of the second digital signal.

In the embodiment of the application, the binary code is used as the fourth digital signal, and the number of the corresponding fourth resistors is smaller than that of the thermometer code, so that the binary code is suitable for a scene with lower precision requirements and fewer required resistors.

In one possible implementation, the M code bits of the first digital signal or the M code bits of the second digital signal are thermometer codes; the resistance values of the M fourth resistors are equal.

In this embodiment of the present application, the resistance values of the fourth resistors under the thermometer code are all equal, so that when the fourth resistors with different resistance values output different voltages or currents as analog signals, the deviation of the analog signals output by the excessive voltages or currents is excessive, and the overall analog signals are greatly disturbed.

In a possible embodiment, the second conversion unit further comprises a fifth resistor; the first end of the fifth resistor is coupled to the first voltage end to input the first voltage or coupled to the second voltage end to input the second voltage; a second end of the fifth resistor is used for being coupled to the first coupling point; the resistance of the fifth resistor is equal to the resistance of the resistor corresponding to the lowest code bit of the second digital signal.

The embodiment of the application can be used for better expressing analog signals output by digital-to-analog conversion by setting the fifth resistor, and can carry the indicated numerical value.

In a possible embodiment, the second conversion unit further comprises a fifth switch; a first end of the fifth resistor is coupled with the fifth switch; the control unit is used for controlling the first end of the fifth resistor to be coupled to the first voltage end through the fifth switch or controlling the first end of the fifth resistor to be coupled to the second voltage end through the fifth switch.

The fifth switch is controlled by the control unit to adjust the first resistor with high voltage or the second resistor with low voltage to be input to the fifth resistor.

In one possible implementation, the N code bits of the first digital signal are binary codes; among the N first resistors, between two first resistors corresponding to adjacent code bits in the N code bits of the first digital signal, the resistance of the first resistor corresponding to the lower code bit of the adjacent code bits in the N code bits of the first digital signal is twice the resistance of the first resistor corresponding to the higher code bit of the adjacent code bits in the N code bits of the first digital signal.

In the embodiment of the application, the binary code is used as the N code bits of the first digital signal, and the number of the corresponding first resistors is smaller than that of the thermometer code, so that the binary code is suitable for the scene with lower precision requirements and smaller required resistance numbers.

In one possible implementation, the N code bits of the first digital signal are thermometer codes; the resistance values of the N first resistors are equal.

In the embodiment of the application, the resistance values of the first resistors under the thermometer codes are all equal, so that when the first resistors with different resistance values output different voltages or currents as analog signals, the deviation of the analog signals output by the overlarge voltages or currents is overlarge, and the overall analog signals are greatly disturbed.

In one possible embodiment, the first conversion unit further comprises a sixth resistor; the first end of the sixth resistor is coupled to the first voltage end to input the first voltage or coupled to the second voltage end to input the second voltage; the resistance value of the sixth resistor is equal to the resistance value of the resistor corresponding to the lowest code bit of the first digital signal.

In the embodiment of the application, the sixth resistor is configured to better express the analog signal output by digital-to-analog conversion, and carry the value indicated by the output analog signal.

In one possible embodiment, the first conversion unit further comprises a sixth switch; a first end of the sixth resistor is coupled with the sixth switch; the control unit is used for controlling the first end of the sixth resistor to be coupled to the first voltage end through the sixth switch or controlling the first end of the sixth resistor to be coupled to the second voltage end through the sixth switch.

The embodiment of the application controls the sixth switch through the control unit to adjust the first resistor which is input to the sixth resistor to be high voltage or the second resistor which is input to the sixth resistor to be low voltage.

In a second aspect, there is provided a digital-to-analog conversion circuit comprising a resistive digital-to-analog converter and a drive amplifier as described in the first aspect; the driving amplifier is coupled to the output end of the resistance type digital-to-analog converter; the resistive digital-to-analog converter is used for inputting digital signals, generating analog signals and outputting the analog signals to the driving amplifier, and the driving amplifier is used for amplifying the analog signals.

A third aspect of an electronic device comprising the resistive digital-to-analog converter as recited in the first aspect above or comprising the digital-to-analog conversion circuit as recited in the second aspect above; the resistive digital-to-analog converter or the digital-to-analog conversion circuit is used for generating an analog signal according to an input digital signal.

For a description of technical effects of the second and third aspects, reference may be made to the relevant description of the first aspect described above.

Drawings

Fig. 1 is a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of still another digital-to-analog converter according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of still another electronic device according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present application;

fig. 6 is a schematic structural diagram of a first switch according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of still another digital-to-analog converter according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of still another digital-to-analog converter according to an embodiment of the present application;

fig. 9 is a schematic structural diagram of still another digital-to-analog converter according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a resistor voltage dividing unit according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of a parallel resistor segment unit according to an embodiment of the present application;

FIG. 13 is a schematic diagram of a parallel resistor segment unit according to an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a parallel resistor segment unit according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a second conversion unit according to an embodiment of the present application.

Detailed Description

It should be noted that the terms "first," "second," and the like in the embodiments of the present application are used for distinguishing between the same type of feature, and not to be construed as indicating a relative importance, quantity, order, or the like.

The terms "exemplary" or "such as" and the like, as used in connection with embodiments of the present application, are intended to be exemplary, or descriptive. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

The terms "coupled" and "connected" in connection with embodiments of the present application are to be construed broadly, and may refer, for example, to a physical direct connection, or to an indirect connection via electronic devices, such as, for example, a connection via electrical resistance, inductance, capacitance, or other electronic devices.

First, some basic concepts of the embodiments of the present application will be explained:

digital-to-analog converters (DACs) are indispensable in the field of electronic devices today as devices for converting digital signals into analog voltage signals. Common digital-to-analog converters include current-to-analog converters (IDACs) and digital-to-analog converters (RDACs). With the development of chips, the requirements on the processing speed and the processing precision of digital signals are also higher and higher. In a processing scenario where a high-speed and high-precision processing is required for digital signals, a current-type digital-to-analog converter is often adopted, but it is difficult to apply the digital-to-analog converter to the processing scenario with high-speed and high-precision.

The embodiment of the application provides a digital-to-analog converter, as shown in fig. 1, in which the digital-to-analog converter 1 finally realizes high-precision feedback of an analog signal corresponding to a digital signal containing a plurality of bits by dividing a resistor into segments. But this embodiment requires the addition of multiple buffers 11, increasing device cost and area.

The embodiment of the present application also provides a digital-to-analog converter, as shown in fig. 2, where the digital-to-analog converter 1 includes two high-stage series units 14 and one low-stage series unit 15. A digital signal including a plurality of bits is segmented into a high-stage digital signal including a high-code bit section and a low-stage digital signal including a low-code bit section. Each of the high-stage series units 14 includes a plurality of high-stage resistors 12 corresponding to bits of the high-stage digital signal. The input terminal of one of the high-stage series units 14 is used for inputting a positive voltage, and the input terminal of the other high-stage series unit 14 is used for inputting a negative voltage. The low-stage series unit 15 includes a plurality of low-stage resistors 13 connected in series, and two ends of the plurality of low-stage resistors 13 connected in series are respectively coupled with the output ends of the two high-stage series units 14. The first end or the second end of one low-stage resistor 13 in the plurality of low-stage resistors 13 is correspondingly selected as a coupling point through the value of the low-stage digital signal so as to output an analog signal.

The embodiment of the application realizes that after the analog signal corresponding to the high-stage digital signal is output to the low-stage serial unit 15 through the high-stage serial unit 14, the analog signal corresponding to the digital signal combining the low-stage digital signal and the high-stage digital signal is output through the low-stage serial unit 15. However, over-current switches are added to the high-stage series unit 14 and the low-stage series unit 15 to select different numbers and resistances of the high Duan Dianzu and the low-stage resistor 13 to output analog signals. In the case of the resistive digital-to-analog converter 1, in the processing scenario of high-rate requirements, it is often necessary to reduce the output impedance by reducing the resistances of the high Duan Dianzu and low-stage resistors 13, thereby increasing the rate of signal processing. The use of a smaller resistance resistor will in turn increase the influence of the on-resistance of the over-current switch in the resistive digital-to-analog converter 1 on the linearity of the digital-to-analog converter 1. If the on-resistance of the over-current switch is reduced by increasing the size of the over-current switch, the influence on the linearity of the digital-to-analog converter 1 is reduced, and a larger parasitic capacitance is generated by increasing the size of the over-current switch. Therefore, in practical applications, it is difficult to realize a digital-to-analog converter that has high accuracy while ensuring a high rate.

An embodiment of the present application provides an electronic device, as shown in fig. 3, the electronic device 2 includes a digital-to-analog converter 3. Alternatively, as shown in fig. 4, the electronic device 2 includes a digital-to-analog conversion circuit including a digital-to-analog converter 3 and a drive amplifier 4. The digital-to-analog converter 3 or the digital-to-analog conversion circuit is used for generating an analog signal from an input digital signal.

The electronic device 2 may be, for example, a delta sigma modulator (sigma selta modulator, SDM), successive approximation registers (successive approximation register, SAR), a sensor, a digital graphics processor, an audio processor, etc.

As shown in fig. 5, the digital-to-analog converter 3 includes a first voltage terminal, a second voltage terminal, a control unit 30, and a first conversion unit 31. The first voltage terminal is used for providing a first voltage; the second voltage terminal is used for providing a second voltage; the control unit 30 is configured to input a first digital signal, where the first digital signal includes N code bits; the first conversion unit 31 includes N first switches 311 and N first resistors 312 corresponding to the N code bits of the first digital signal; as shown in fig. 6, a first terminal of the N first switches 311 is used for inputting a first voltage, and a second terminal of the N first switches 311 is used for inputting a second voltage; the third terminal of each first switch 311 is coupled to a first terminal of a corresponding first resistor 312; the controlled end of each first switch 311 is used for inputting one code bit of the N code bits of the first digital signal, so as to conduct the first end of the first switch 311 with the third end of the first switch 311 under the control of the first digital signal, or conduct the second end of the first switch 311 with the third end of the first switch 311 under the control of the first digital signal. As shown in fig. 5, the second ends of the N first resistors 312 are coupled to a first coupling point 314; the first coupling point 314 is used as an output terminal of the first conversion unit 31 for outputting a first analog signal corresponding to N code bits of the first digital signal.

In this embodiment, all the first resistors 312 are respectively corresponding to one of the N code bits of the first digital signal, and then the first voltage or the second voltage is selected and input according to the value of the code bit, and then the second ends of all the first resistors 312 are coupled to the first coupling point 314 as output ends. The first analog signal corresponding to the N code bits of the first digital signal is output through the first coupling point 314. At this time, all the first resistors 312 can be equivalently connected in parallel, and no matter the corresponding first resistor inputs the first voltage or the second voltage, the resistance value is provided for the whole first conversion unit 31, so the equivalent resistance value R1 of the first conversion unit 31 is the resistance value after all the first resistors 312 are equivalently connected in parallel, which is smaller than the resistance value of the first resistor 312 and is a constant resistance value. Illustratively, when the N code bits of the input first digital signal are fixed binary codes, the output impedance rout=r of the first conversion unit 31 ₂ 2, wherein R is ₂ The resistance of the first resistor 312 corresponding to the highest bit of the N bits of the first digital signal. In the case where the resistance value of the first resistor 312 corresponding to the highest code bit of the N code bits of the first digital signal is constant, the output impedance of the first conversion unit 31 is constant and is smaller than the resistance value of the first resistor 312. When N code bits of the input first digital signal are fixed as thermometer codes, the output impedance rout=r of the first conversion unit 31 ₃ /2 ^N ，R ₃ When N code bits of the first digital signal are thermometer codesThe resistance of the first resistor 312 corresponding to the highest bit of the code. It can be seen that when the N code bits of the first digital signal are fixed as thermometer codes, the output impedance of the first conversion unit 31 is smaller than when the N code bits of the first digital signal are binary codes, and in the case where the resistance value of the first resistor 312 is constant, the equivalent impedance is also a constant value. Under the application of the embodiment of the present application, the output impedance of the digital-to-analog converter 3 can be reduced to be very small, and the resistance value of the first resistor 312 does not need to be greatly reduced in the implementation process, and the stable and very small output impedance can be obtained by adopting the resistor with the conventional resistance value as the first resistor 312, so that the digital-to-analog conversion with high precision and high speed can be realized under the condition of avoiding using the overcurrent switch with a larger size.

In some possible implementations, the N code bits of the first digital signal are binary codes.

Illustratively, taking a binary code in which the first digital signal includes four code bits as an example, N code bits of the first digital signal may be denoted as xxxx, where the first voltage is a high voltage and the second voltage is a low voltage. At this time, N is the number of bits of the binary code, i.e., 4. The controlled ends of the 4 first switches 311 respectively correspond to 0 bit, 1 bit, 2 bit and 3 bit of the input first digital signal, and when the corresponding bit takes high value, the first ends and the third ends of the first switches 311 are conducted so as to output a first voltage which is high voltage to the first resistor 312; when the value of the corresponding bit is low, the second terminal and the third terminal of the first switch 311 are turned on to output a second voltage, which is a low voltage, to the first resistor 312.

In this embodiment, the corresponding value of each bit is 0 or 1 is corresponding to the different voltage values of the first voltage and the second voltage, when a certain bit is 1, the value is represented as high by the first voltage being high voltage, and when a certain bit is 0, the value is represented as low by the second voltage being low voltage. Meanwhile, different bits represent different digital sizes, and 1000, 0100, 0010 and 0001 are taken as examples, and 1 of 1000 is a value of 3 bits, which represents a decimal number of 8. 0100 is a 2-bit value representing a decimal number of 4. 0010 is a 1-bit value representing a decimal number of 2. 0001 is a 0-bit value representing a decimal number of 1. It can be seen that in the case of a binary code, the value of the higher bit is twice that of the lower bit in the adjacent two bits. So for a plurality of first resistors 312 representing different bits. According to the level of the corresponding bit, different resistance values can be given to the first resistor 312 corresponding to different bits, and when the same voltage (e.g., the first voltage) is input, the lower the resistance value of the first resistor 312 corresponding to the higher bit, the lower the resistance value of the first resistor 312 is, the less the voltage is divided by the first voltage, so that the higher voltage value can be output to correspond to the value of the higher bit.

Illustratively, when the N code bits of the first digital signal are binary codes, the resistance of the first resistor 312 of the lower bit is twice the resistance of the first resistor 312 of the higher bit of the two first resistors 312 corresponding to the two adjacent bits.

In some possible implementations, the N code bits of the first digital signal are thermometer codes.

Illustratively, the N first resistors 312 have equal resistance values.

Illustratively, the conversion relationship between the thermometer code and the binary code is: bit width of thermometer code=2 ⁿ -1, wherein n is the number of bits of the binary code. As shown in table 1 below, taking the first digital signal with 3 bits as an example, the first digital signal is a binary code, i.e., the first digital signal may be represented as xxx, the first voltage is a high voltage, and the second voltage is a low voltage. At this time, n is the number of bits of the binary code, that is, 3, and 8 different values from 0 (10) to 7 (10) under decimal can be expressed by the first digital signal of 3 bits. And the code bits of the thermometer code are 7 bits, namely the N code bits of the first digital signal are 7 code bits. At this time, the number N of the first resistors 312 corresponds to the code bit of the thermometer code, i.e. 7. The controlled ends of the 7 first switches 311 respectively correspond to 1 code bit to 7 code bits of the input first digital signal, and when the corresponding bit has a value of 1, the first ends and the third ends of the first switches 311 are turned on to A first voltage which is a high voltage is input to the first resistor 312; when the corresponding bit has a value of 0, the second terminal and the third terminal of the first switch 311 are turned on to input a second voltage, which is a low voltage, to the first resistor 312. When the value of the 7 code bits of the first digital signal is 0 (10), the values corresponding to the 7 code bits are all 0, that is, the controlled ends of the 7 first switches 311 turn on the second ends and the third ends of the corresponding first switches 311, so as to input the second voltage with low voltage to the 7 first resistors 312. When the value of 7 code bits of the first digital signal is 1 (10), the controlled end of the first switch 311 corresponding to the 1 code bit turns on the first end and the third end of the corresponding first switch 311 to input the first voltage which is the high voltage to the first resistor 312 corresponding to the 1 code bit, and the controlled ends of the first switches 311 corresponding to the rest 6 code bits turn on the second end and the third end of the corresponding first switch 311 to input the second voltage which is the low voltage to the 6 first resistors 312 from the 2 code bits to the 7 code bits. Similarly, when the value of the 7 bits of the first digital signal is 2 (10), the first resistor 312 corresponding to the 1 bit and the 2 bits is input with a first voltage of high voltage, and the first resistor 312 corresponding to the 3 bits to the 7 bits is input with a second voltage of low voltage. When the value of the 7 code bits of the first digital signal is 7 (10), the 7 first resistors 312 are all input with the first voltage being the high voltage.

Table 1 3 bit binary code and thermometer code contrast table

In this embodiment of the present application, when the binary code control switch is used to output the corresponding analog signal, the resistance of the resistor corresponding to each bit of the binary code is different, the resistance of the resistor corresponding to the high bit is smaller, the output voltage or current is larger, the resistance of the resistor of the low bit is too large, and the output voltage or current is smaller. When outputting a completely different voltage or current as an analog signal, a larger analog will produce a larger disturbance error at the output, thereby affecting the overall accuracy, while in the form of thermometer codes. The code bit of each thermometer code corresponds to the value 1 under decimal system, so the resistance value corresponding to the code bit of each thermometer code is equal, and the generation of interference errors can be reduced.

Illustratively, as shown in fig. 5, in the first converting unit 31, the number of the first resistors 312 may be changed to two times, and the first switches 311 may be changed to two times the number of single pole single throw switches, one half of the double first resistors 312 input the first voltage through the corresponding single pole single throw switch, and the other half of the first resistors 312 input the second voltage through the corresponding single pole single throw switch; each first resistor 312 inputting the first voltage corresponds to one of N code bits of the first digital signal; each first resistor 312 inputting the second voltage also corresponds to one of the N code bits of the first digital signal; one code bit of the N code bits of the first digital signal controls one first resistor 312 of the corresponding first voltage input and one first resistor 312 of the corresponding second voltage input, which is coupled to the first coupling point 314. The principle of implementation of the present embodiment using a single pole single throw switch is essentially identical to the principle of using the first switch 311.

In some possible embodiments, when the bits of the first digital signal are more, the digital signal with more bits can be implemented in a segmented manner to achieve high-rate and high-precision digital-to-analog conversion.

Optionally, one segmentation method is: a first digital signal including a plurality of code bits is input, and the first digital signal is segmented into N code bits in an upper segment and E code bits in a lower segment. And simultaneously, generating a second digital signal corresponding to N code bits of the high-order segment of the first digital signal, wherein the second digital signal comprises N code bits, and the value of the N code bits of the second digital signal is larger than that of the N code bits of the first digital signal. As shown in fig. 7, the digital-to-analog converter 3 further includes a second conversion unit 32 and a resistor voltage division unit 33. As shown in fig. 8, the resistor voltage dividing unit 33 includes a first resistor module 331 and a second resistor module 332; the first end of the first resistor module 331 is coupled to the output end (i.e. the first coupling point 314) of the first converting unit 31, and the second end of the first resistor module 331 and the first end of the second resistor module 332 are coupled to the third coupling point 333; a second end of the second resistor module 332 is coupled to an output of the second conversion unit 32; the third coupling point 333 serves as an output of the digital-to-analog converter 3.

As shown in fig. 9, the second conversion unit 32 includes N second switches 321, N second resistors 322, and a second division unit 323; the first ends of the N second switches 321 are used for inputting a first voltage, and the second ends of the N second switches 321 are used for inputting a second voltage; a third terminal of each second switch 321 is coupled to a first terminal of a corresponding second resistor 322; the controlled end of each second switch 321 is used for inputting one code bit of the N code bits of the second digital signal, so as to conduct the first end of the second switch 321 with the third end of the second switch 321 under the control of the second digital signal, or conduct the second end of the second switch 321 with the third end of the second switch 321 under the control of the second digital signal; the first end of the second segment unit 323 is used for inputting a first voltage or a second voltage; a second end of the N second resistors 322 is coupled to a second coupling point 324; the second coupling point 324 is used as an output terminal of the second converting unit 32 for outputting a second analog signal corresponding to N code bits of the second digital signal.

In this embodiment, by segmenting the first digital signal including the plurality of code bits into N code bits of the first digital signal located in the high code bit segment and E code bits of the first digital signal located in the low code bit segment, a second digital signal is generated, where the second digital signal includes N code bits, and the value of the N code bits of the second digital signal is greater than the value of the N code bits of the first digital signal (e.g., the value of the N code bits of the first digital signal is 13 (10), and the value of the N code bits of the second digital signal is 14 (10)). The first analog signal corresponding to the N code bits of the first digital signal is generated by the first conversion unit 31, and the second analog signal corresponding to the N code bits of the second digital signal is generated by the second conversion unit 32. The first analog signal is output to the first resistor module 331 through the first coupling point 314; the second analog signal is output to the second resistor module 332 through the second coupling point 324. The third coupling point 333 is used as an output end of the digital-to-analog converter 3 to output a third analog signal, where the third analog signal is used to express N code bits of the first digital signal in the high-code-bit section and E code bits of the first digital signal in the low-code-bit section, where N is 4 and E is 4, and the analog signal (for example, the first digital signal is a binary signal 1010 1011) corresponding to the first digital signal combined into the first digital signal in the plurality of code bits, and may be segmented into 1010 (corresponding to the N code bits of the first digital signal) in the high-code-bit section and 1011 (corresponding to the E code bits of the first digital signal) in the low-code-bit section. The E code bits of the first digital signal are used as the digital signals of the low code bit section for controlling the resistances of the first resistor module 331 and the second resistor module 332. When the E code bits of the first digital signal are lower, the resistance of the second resistor module 332 is higher, and the resistance of the first resistor module 331 is lower, the output third analog signal is more similar to the first analog signal. When the E code bits of the first digital signal are higher, the resistance of the second resistor module 332 is lower, and the resistance of the first resistor module 331 is higher, the output third analog signal is more similar to the second analog signal.

Illustratively, the value of the N code bits of the second digital signal is greater than 1 than the value of the N code bits of the first digital signal.

In this embodiment of the present application, the difference between the values of the N code bits of the second digital signal and the values of the N code bits of the first digital signal may represent the value range of the E code bits of the first digital signal, and when the N code bits of the first digital signal and the E code bits of the first digital signal are continuous code bits, after the E code bits of the first digital signal take the maximum value, 1 is added, which corresponds to the lowest code bit value of the N code bits of the first digital signal as 1. At this time, the value of N code bits of the second digital signal is set to be 1 greater than the value of N code bits of the first digital signal, so that the third analog signal can be better used to indicate the value of the first digital signal obtained by combining the N code bits of the first digital signal with the E code bits of the first digital signal. However, when the value of N code bits of the second digital signal is greater than the value of N code bits of the first digital signal by a value different from 1, the value of the first digital signal obtained by combining the N code bits of the first digital signal and the E code bits of the first digital signal may be indicated by the third analog signal by adjusting the corresponding relationship between the resistance values of the first resistor module 331 and the second resistor module 332 and the resistance values of the first resistor 312 and the second resistor 322.

In some possible embodiments, the N code bits of the second digital signal are binary codes.

Illustratively, when the N code bits of the second digital signal are binary codes, the resistance of the second resistor 322 of the lower bit is twice the resistance of the second resistor 322 of the higher bit of the two second resistors 322 corresponding to the two adjacent bits.

Illustratively, the resistance of the second segment unit 323 is equal to the resistance of the second resistor 322 corresponding to the lowest bit of the N code bits of the second digital signal.

In some possible implementations, the N code bits of the second digital signal are thermometer codes.

Illustratively, when the N code bits of the second digital signal are thermometer codes, the resistance values of the N second resistors 322 are equal.

Illustratively, when the N code bits of the second digital signal are thermometer codes, the resistance of the second segment unit 323 is equal to the resistance of the second resistor 322.

When the N code bits of the second digital signal are the binary code and the thermometer code, the description of the related technical effects of the second segmentation unit 323 and the second resistor 322 in the second conversion unit 32 can refer to the description of the N code bits of the first digital signal as the binary code and the thermometer code, which is not repeated.

In some possible embodiments, as shown in fig. 10, the resistor voltage dividing unit 33 specifically includes an output selection switch 334 and E third resistors 330; one end of the E third resistors 330 connected in series is coupled with the first coupling point 314, and the other end is coupled with the second coupling point 324; the selection input end of the output selection switch 334 is used for coupling E code bits controlled by the first digital signal to the first end or the second end of one third resistor 330 in the E third resistors 330, and the coupling point between the selection input end of the output selection switch 334 and the first end or the second end of one third resistor 330 is used as a third coupling point 333; the third resistor 330 between the third coupling point 333 and the first coupling point 314 is used to form the first resistor module 331, and the third resistor 330 between the third coupling point 333 and the second coupling point 324 is used to form the second resistor module 332.

In the embodiment of the present application, when the value of E code bits of the first digital signal is higher, the output third analog signal is more similar to the second analog signal, and then the number of the third resistors 330 between the second coupling point 324 and the third coupling point 333 is reduced by adjusting the coupling position of the selection input end of the output selection switch 334, that is, the position of the third coupling point 333, so as to reduce the resistance of the second resistor module 332 between the second coupling point 324 and the third coupling point 333 and increase the resistance of the first resistor module 331 between the first coupling point 314 and the third coupling point 333.

Illustratively, when the E code bits of the first digital signal are thermometer codes, the number E of the third resistor 330 takes a value of 2 ⁿ -1, where n is the number of bits when the E code bits of the first digital signal are binary codes. And the resistance value of each third resistor 330 is equal.

In this embodiment, when the E code bits of the first digital signal are thermometer codes, taking the thermometer code corresponding to the binary code with the low code bit segment of the first digital signal being four bits as an example, 15 code bits are needed, which are respectively 1 code bit to 15 code bits. When the value of the E code bits of the first digital signal is 0 (10), the third coupling point 333 coincides with the first coupling point 314, that is, the second resistor module 332 includes 15 third resistors 330, and the first resistor module 331 includes 0 third resistors 330. At this time, the second analog signal and the first analog signal are output from the third coupling point 333 after being connected in parallel, but the first analog signal is output from the first coupling point 314 of the first conversion unit 31 without any voltage division by the third resistor 330, and the second analog signal is output from the second coupling point 324 of the second conversion unit 32, then is output to the third coupling point 333 after passing through 15 third resistors 330, and finally the output third analog signal is equal to the value of the first analog signal. Similarly, when the value of the third analog signal is 15 (10), the third coupling point 333 coincides with the second coupling point 324, and at this time, the second analog signal can be output to the third coupling point 333 without being divided by the third resistor 330, and the first analog signal can be output to the third coupling point 333 after passing through 15 third resistors 330, and at this time, the value of the output third analog signal is equal to the second analog signal.

For example, in the case where the value of N code bits of the second digital signal is greater than the value of N code bits of the first digital signal by 1, in the present embodiment, in the digital-to-analog converter 3 shown in fig. 7, 8, 9 and 10, the sum of the equivalent resistance value of the first conversion unit 31 and the equivalent resistance value of the second conversion unit 32 needs to be equal to the resistance value of one third resistor 330.

In some possible embodiments, as shown in fig. 11, the digital-to-analog converter 3 further includes a first bridge resistor 34, and the output terminal (i.e., the first coupling point 314) of the first conversion unit 31 is coupled to the first terminal of the first resistor module 331 through the first bridge resistor 34.

In some possible embodiments, as shown in fig. 11, the digital-to-analog converter 3 further includes a second bridge resistor 35, and the output terminal (i.e., the second coupling point 324) of the second conversion unit 32 is coupled to the second terminal of the second resistor module through the second bridge resistor 35.

In the embodiment of the present application, when the digital-to-analog converter 3 includes the first bridge resistor 34, the sum of the equivalent resistance of the first conversion unit 31 plus the equivalent resistance of the second conversion unit 32 and the resistance of the first bridge resistor 34 is equal to the resistance of a third resistor 330. At this time, by adjusting the resistance of the first bridge resistor 34, the equivalent resistances of the first conversion unit 31 and the second conversion unit 32 can be increased or decreased appropriately, and the resistances of the first resistor 312 and the second resistor 322 can be set better.

Similarly, when the digital-to-analog converter 3 includes the second bridge resistor 35, the sum of the equivalent resistance of the first conversion unit 31 and the equivalent resistance of the second conversion unit 32 and the resistance of the second bridge resistor 35 is equal to the resistance of the third resistor 330. At this time, by adjusting the resistance value of the second bridge resistor 35, the equivalent resistance values of the first conversion unit 31 and the second conversion unit 32 can be appropriately increased or decreased, and the resistance values of the first resistor 312 and the second resistor 322 can be better set.

Similarly, when the digital-to-analog converter 3 includes the second bridge resistor 35, the sum of the equivalent resistance of the first conversion unit 31 and the equivalent resistance of the second conversion unit 32, and the resistance of the first bridge resistor 34 and the resistance of the second bridge resistor 35 is equal to the resistance of a third resistor 330. At this time, by adjusting the resistances of the first bridge resistor 34 and the second bridge resistor 35, the equivalent resistances of the first conversion unit 31 and the second conversion unit 32 can be appropriately increased or decreased, and the resistances of the first resistor 312 and the second resistor 322 can be further set better.

Illustratively, the sum of the equivalent resistance of the first conversion unit 31 and the resistance of the first bridge resistor 34 may be equal to the sum of the equivalent resistance of the second conversion unit 32 and the resistance of the second bridge resistor 35. Alternatively, at this time, the equivalent resistance value of the first conversion unit 31 may be equal to the equivalent resistance value of the second conversion unit 32, or the equivalent resistance value of the first conversion unit 31 may not be equal to the equivalent resistance value of the second conversion unit 32.

In the embodiment of the present application, the equivalent resistance or the resistance of each of the first conversion unit 31, the second conversion unit 32, the first bridge resistor 34 and the second bridge resistor 35 is not limited, and the four may be completely equal, partially equal or completely unequal, and only the requirement that the sum of the equivalent resistance or the resistance of the four is equal to the resistance of one third resistor 330 is satisfied.

In some possible embodiments, as shown in fig. 5, the first conversion unit 31 further comprises a fifth resistor 315; the resistance of the fifth resistor 315 is equal to the resistance corresponding to the lowest bit of the first digital signal. A first end of the fifth resistor 315 is fixedly coupled to the first voltage terminal for inputting the first voltage, or a first end of the fifth resistor 315 is fixedly coupled to the second voltage terminal for inputting the second voltage; a second terminal of the fifth resistor 315 is coupled to the first coupling point 314.

Illustratively, the first digital signal includes N code bits, for example, thermometer codes, including N first resistors 312. Each first resistor 312 correspondingly outputs a voltage, and the first coupling point 312 can output voltages with values of 0/N, 1/N, 2/N, … and N/N, for example, when the value of the first resistor 312 corresponds to 1, according to the difference of the values of the N code bits of the first digital signal. And after a fifth resistor 315 is provided. When the fifth resistor 315 is fixedly coupled to the second voltage terminal, the fifth resistor 315 is fixedly coupled to output a voltage with a value of 0/(n+1), and the first coupling point 312 can output voltages with values of 0/(n+1), 1/(n+1), 2/(n+1), …, and N/(n+1), which can be used to express binary numbers 0 to N, and at this time, the first conversion unit 31 is more beneficial to carry calculation. When the fifth resistor 315 is fixedly coupled to the first voltage terminal, the fifth resistor 315 is fixedly coupled to output a voltage with a value of 1/(n+1), and the first coupling point 312 can output voltages with values of 1/(n+1), 2/(n+1), …, (n+1)/(n+1), which can be used to express binary numbers 1 to n+1. At this time, the resistance of the fifth resistor 315 is the resistance of the first resistor 312 corresponding to the lowest bit of the N bits of the first digital signal.

In some possible embodiments, as shown in fig. 5, the first conversion unit 31 further comprises a fifth switch 316. A first end of the fifth resistor 315 is coupled to the fifth switch 316; the control unit 30 is configured to control the first end of the fifth resistor 315 to be coupled to the first voltage terminal through the fifth switch 316 or control the first end of the fifth resistor 315 to be coupled to the second voltage terminal through the fifth switch 316.

In the embodiment of the present application, the control unit 30 controls the fifth switch 315 to couple the first end of the fifth resistor 315 to the first voltage end or the second voltage end, so as to implement the value represented by the first conversion unit 31.

In some possible embodiments, as shown in fig. 9, the second conversion unit 32 further includes a sixth resistor 325; the resistance value of the sixth resistor 325 is equal to the resistance value corresponding to the lowest code bit of the N code bits of the second digital signal. The first end of the sixth resistor 325 is fixedly coupled to the first voltage terminal for inputting the first voltage, or the first end of the sixth resistor 325 is fixedly coupled to the second voltage terminal for inputting the second voltage; a second end of the sixth resistor 325 is coupled to the second coupling point 324.

In some possible embodiments, as shown in fig. 9, the second conversion unit 32 further includes a sixth switch 326. A first terminal of a sixth resistor 325 is coupled to a sixth switch 326; the control unit 30 is configured to control the first terminal of the sixth resistor 325 to be coupled to the first voltage terminal through the sixth switch 326 or control the first terminal of the sixth resistor 325 to be coupled to the second voltage terminal through the sixth switch 326.

The description of the technical effects of the sixth resistor 315 and the sixth switch 326 in the embodiments of the present application may refer to the above description about the fifth resistor 315 and the fifth switch 325, so that the description is omitted.

In some possible embodiments, a digital-to-analog conversion is performed on a set of digital signals comprising a plurality of successively increasing values of 1.

Illustratively, for a set of digital signals including a plurality of values (e.g., values 010 011 (2), 010 100 (2), 010 101 (2), 010 110 (2), …, 111 111 (2)), each of the set of digital signals is segmented into N code bits of the first digital signal of the upper code bit segment and E code bits of the first digital signal of the lower code bit segment. E code bits of the first digital signal of the low code bit section are input into the resistor voltage dividing unit to control the resistance values of the first resistor module 331 and the second resistor module 332. As shown in fig. 10, taking a six-bit digital signal 010 011 (2) as an example, a 3-bit digital signal 010 (2) segmented into a high-bit section (i.e., N bits of the first digital signal) and a 3-bit digital signal 011 (2) segmented into a low-bit section (i.e., E bits of the first digital signal), inputting the high-bit 3-bit digital signal 010 (2) into the first conversion unit 31, generating a 3-bit digital signal 011 (2) having a value greater than 1 of the high-bit 3-bit digital signal 010 (2), inputting the low-bit 3-bit digital signal 011 (2) into the second conversion unit 32, and then inputting the low-bit 3-bit digital signal 011 (2) into the resistor divider unit 33, wherein the E bits of the first digital signal are the low-bit section and the 3-bit digital signal, there is 2 ³ -1=7 third resistors 330, which canFor expressing a total of 8 values of 000 (2) -111 (2), when performing digital-to-analog conversion on a group of digital signals including a plurality of digital signals with values continuously increased by 1, for example, when performing digital-to-analog conversion on digital signals with values of 010 011 (2) -010111 (2), only the values of E code bits of the first digital signal in the input resistor voltage dividing unit 33 need to be changed, namely, the value of 011 (2) is gradually increased by 1 until the value is 111 (2). After the E code bits of the first digital signal reach 111 (2), the digital-to-analog conversion of the first digital signal with the subsequent value added with 1 is performed in the following two ways:

mode one: the N code bits of the first digital signal input into the first conversion unit 31 are added by 1, the N code bits of the second digital signal input into the second conversion unit 32 are added by 1, and the output selection switch 334 in the resistor voltage division unit 33 is re-coupled to the coupling point representing the lowest value, that is, the third coupling point 333 is close to the first coupling point 314. And then sequentially adding 1 to the values of the E code bits of the first digital signal in the input resistor voltage dividing unit 33, so as to respectively perform digital-to-analog conversion on a plurality of digital signals with continuous values added with 1 in a group of digital signals.

Mode two: the value of N code bits of the first digital signal input to the first conversion unit 31 is added by 2. At this time, the output selection switch 334 is controlled to gradually approach the third coupling point 333 from a position close to the second coupling point 324 of the second conversion unit 32 to the first coupling point 314 with N code bits of the second digital signal input in the second conversion unit 32 as the high code bit segment of the digital signal to be digital-to-analog converted and then with E code bits of the low code bit segment of the digital signal to be digital-to-analog converted as the E code bits of the first digital signal. When the third coupling point 333 coincides with the first coupling point 314 or is coupled to the output terminal of the first bridge resistor 34, the E code bits representing the first digital signal have been counted to the highest level and cannot take any more value. At this time, the N code bits of the second digital signal input to the second conversion unit 32 are added by 2, so that the N code bits of the first digital signal input to the first conversion unit 31 are used again as the high code bit segment of the digital signal to be digital-to-analog converted, and the E code bits of the low code bit segment of the first digital signal to be digital-to-analog converted are successively added by one to express digital-to-analog conversion of the digital signal with the value gradually added by 1. At this time, the third coupling point 333 gradually approaches the second coupling point 324 from the first coupling point 314. By the pushing, the N code bits of the first digital signal and the N code bits of the second digital signal are alternately used as high-order code bit segments of the digital signal for digital-to-analog conversion. In the case of using the second mode of processing, in the structure shown in fig. 9, when the equivalent resistance of the first conversion unit 31 is equal to the equivalent resistance of the second conversion unit 32 and is equal to half of the resistance of the third resistor 330, the differential nonlinearity (differential nonlinearity, DNL) in the digital-to-analog conversion is preferable in the second mode. In the structure including the first bridge resistor 34 and the second bridge resistor 35 as shown in fig. 11, when the sum of the equivalent resistance of the first conversion unit 31 and the resistance of the first bridge resistor 34 is equal to the sum of the equivalent resistance of the second conversion unit 32 and the resistance of the second bridge resistor 34 and is equal to half of the resistance of the third resistor 330, the differential nonlinearity (differential nonlinearity, DNL) in the digital-to-analog conversion is preferable.

In the method of the first embodiment of the present application, the values of the E code bits of the first digital signal serving as the low-order code segment reach the highest value each time, when the high-order code segment needs to be carried, the values of the N code bits of the first digital signal and the values of the N code bits of the second digital signal need to be changed at the same time, and the coupling point of the selection input end of the output selection switch 334 needs to be adjusted. In the second mode, when the E code bits of the first digital signal of the resistor voltage dividing unit 33 are carried to the high code bit section, only the value of one of the N code bits of the first digital signal or the N code bits of the second digital signal needs to be changed, so that the operation is more convenient and faster.

As illustrated in fig. 5 and 9, taking a data signal input with four bits as an example, the fifth resistor 315 of the first conversion unit 31 and/or the sixth resistor 325 of the second conversion unit 32 may fix a first voltage input as a high voltage to achieve numerical expressions of 1 (10) to 16 (10) or fix a second voltage input as a low voltage to achieve expressions of 0 (0) to 15 (10). When the value of the input first conversion unit 31 or the second conversion unit 32 needs to be changed, the control unit 30 can control the fifth switch 316 or the sixth switch 326 to switch the voltage input to the fifth resistor 315 or the sixth resistor 325 to the first voltage or the second voltage. For example, N code bits of the first digital signal input to the first conversion unit 31 are used as high-order code bit segments of the digital signal subjected to digital-to-analog conversion. If the first conversion unit 31 and the second conversion unit 32 can both express the digital signal with 4 bits, if the value of the N code bits of the first digital signal is 15 (10), the resistor voltage division unit 33 needs to carry to the higher code bit stage if the value of the N code bits of the first digital signal reaches the maximum, in the first embodiment of the above manner, the first conversion unit 31 can adjust the voltage input to the fifth resistor 315 to be the first voltage so as to realize the value expression of 16 (10), but the second conversion unit 32 cannot realize the expression of 17 (10) on the N code bits of the second digital signal, at this time, in the second embodiment of the above manner, the voltage input to the sixth resistor 325 in the second conversion unit 32 is switched from the second voltage to the first voltage, the second conversion unit 32 can input the N code bits of the second digital signal with the value of 16 (10), and at this time, the N code bits of the second digital signal are taken as the higher code bit stage of the digital signal so as to realize the continuous digital-analog-to-analog conversion of the subsequent digital signal.

Alternatively, another segmentation method is: a segment of a digital signal comprising a plurality of bits is segmented into N code bits of a first digital signal of a high code bit segment and M code bits of a first digital signal of a low code bit segment. As shown in fig. 5, a first segmentation unit 313 is provided in the first conversion unit. The first segmentation unit 313 is provided as a parallel type resistive segmentation unit. As shown in fig. 12, the parallel resistance segmentation unit 5 includes M fourth switches 51, M fourth resistors 52;

the first ends of the M fourth switches 51 are used for inputting a first voltage, and the second ends of the M fourth switches 51 are used for inputting a second voltage; the third terminal of each fourth switch 51 is coupled to the first terminal of a corresponding fourth resistor 52; the controlled end of each fourth switch 51 is configured to input one of M code bits of the first digital signal, so as to conduct the first end of the fourth switch 51 with the third end of the fourth switch 51 under the control of the M code bits of the first digital signal, or conduct the second end of the fourth switch 51 with the third end of the fourth switch 51 under the control of the M code bits of the first digital signal; a second end of the M fourth resistors 52 is coupled to a fourth coupling point 54; the fourth coupling point 54 is coupled to the first coupling point 314 as an output end of the parallel resistor segmentation unit 5, and is configured to output a fourth analog signal corresponding to M code bits of the first digital signal to the first coupling point 314; the first coupling point 314 serves as an output of the digital-to-analog converter 3 for outputting a signal comprising the first analog signal and the fourth analog signal.

In this embodiment, for example, there is a first digital signal including a plurality of bits, the first digital signal including a plurality of bits is segmented into N bits of the first digital signal of the high-bit segment and M bits of the first digital signal of the low-bit segment, the M bits of the first digital signal are input into the first segmentation unit 313 of the parallel resistor segmentation unit 5, so that a fourth analog signal corresponding to the M bits of the first digital signal of the low-bit segment is output from the first segmentation unit 313, and a first analog signal corresponding to the N bits of the first digital signal of the high-bit segment is output from the first coupling point 314 by matching the first switch 311 and the first resistor 312 as shown in fig. 5, and at this time, the sum of the first analog signal and the fourth analog signal output from the first coupling point 314 is used to express the analog signal corresponding to the first digital signal including a plurality of bits.

In some possible implementations, the M code bits of the first digital signal are binary codes.

Illustratively, when the M code bits of the first digital signal are binary codes, the number of fourth resistors 52 is equal to the number of bits of the M code bits of the first digital signal. Of the two fourth resistors 52 corresponding to the adjacent two bits, the fourth resistor 52 of the lower bit has a resistance twice that of the fourth resistor 52 of the higher bit.

The resistance of the fifth resistor 315 is the resistance of the resistor corresponding to the lowest bit of the first digital signal. At this time, the lowest bit of the first digital signal is the lowest bit of the M bits of the first digital signal. Therefore, the resistance of the fifth resistor 315 is equal to the resistance of the fourth resistor 52 corresponding to the lowest bit of the M bits of the first digital signal.

In some possible implementations, the M code bits of the first digital signal are thermometer codes.

Illustratively, when the M code bits of the first digital signal are thermometer codes, the number M of the fourth resistors 52 is equal to 2 ⁿ -1, wherein n is a bit corresponding to when M code bits of the first digital signal are binary codes. And the resistance values of the M fourth resistors 52 are equal.

Illustratively, when the M code bits of the first digital signal are thermometer codes, the resistance of the fifth resistor 315 is equal to the resistance of the fourth resistor 52. At this time, the resistance of the fifth resistor 315 is still equal to the resistance of the fourth resistor 52 corresponding to the lowest bit of the M bits of the first digital signal, but the resistances of the fourth resistors 52 are all equal.

In the embodiment of the present application, the description of the related technical principles and technical effects of the parallel-type resistor segmentation unit 5 shown in fig. 12 may refer to the description related to the first conversion unit 31 and the second conversion unit 32, and will not be repeated.

In some possible embodiments, when the first conversion unit 31 does not include the fifth resistor 315, the equivalent resistance of the first segmentation unit 313 is equal to the resistance of the first resistor 312 corresponding to the lowest bit of the N bits of the first digital signal. (i.e., when the N code bits of the first digital signal are binary signals, the equivalent resistance of the first segmentation unit 313 needs to be equal to the resistance of the first resistor 312 with the largest resistance; when the N code bits of the first digital signal are thermometer codes, the equivalent resistance of the first segmentation unit 313 needs to be equal to the resistance of the first resistor 312). When the first conversion unit 31 includes the fifth resistor 315, the equivalent resistance of the first segmentation unit 313 and the fifth resistor 315 is equal to the resistance of the first resistor 312 corresponding to the lowest bit of the N bits of the first digital signal.

In some possible embodiments, as shown in fig. 12, a third segmentation unit 53 may be further included in the parallel-type resistance segmentation unit 5. When the parallel resistor segmentation unit 5 performs digital-to-analog conversion on the M code bits of the first digital signal obtained after segmentation, the M code bits of the first digital signal may also be segmented to obtain a fifth digital signal of a high code bit segment among the M code bits of the first digital signal and a sixth digital signal of a low code bit segment among the M code bits of the first digital signal. As shown in fig. 13, the fifth digital signal of the high-bit segment is digital-to-analog converted by the fourth resistor 52, and the third segmentation unit 53 shown in fig. 12 is configured as the parallel resistor segmentation unit 5 shown in fig. 12, and the sixth digital signal of the low-bit segment is digital-to-analog converted by the parallel resistor segmentation unit 5, so as to obtain the analog signals corresponding to the M code bits of the first digital signal.

For example, for a digital signal of 10 bits, N code bits (N is 4) of a first digital signal of 4 bits which can be segmented into a high code bit segment and M code bits (M is 6) of a first digital signal of 6 bits which can be segmented into a low code bit segment are input into the digital-to-analog converter 3 shown in fig. 5, the N code bits (N is 4) of the first digital signal of 4 bits are digital-to-analog converted by the first resistor 312 of the digital-to-analog converter 3 shown in fig. 5, the first segmentation unit 313 in fig. 5 is set to the structure of the parallel resistor segmentation unit 5 shown in fig. 12, and the M code bits (M is 6) of the first digital signal of 6 bits are input into the first segmentation unit 313 of the structure of the parallel resistor segmentation unit 5 for digital-to-analog conversion. Further, when processing M code bits (M is 6) of the first digital signal of 6 bits, the M code bits (M is 6) of the first digital signal of 6 bits may be re-segmented into a fifth digital signal of 2 bits, for example, a high code bit segment, and a sixth digital signal of 4 code bit segments. The fifth digital signal of 2 bits is input to the fourth resistor 52 of the parallel type resistor segment unit 5 for digital-to-analog conversion. Meanwhile, as shown in fig. 13, a third segment unit 53 in the parallel type resistance segment unit 5 shown in fig. 12 is set to the configuration shown in fig. 12, and a sixth digital signal of the low code bit segment is digital-to-analog converted by the third segment unit 53. In fig. 13, reference numeral 51' denotes a structure of a fourth switch 51 in the parallel-type resistance segment unit 5 shown in fig. 12; reference numeral 52' denotes a structure of a fourth resistor 52 in the parallel type resistor segment unit 5 shown in fig. 12; reference numeral 53' denotes a structure of a third segment unit 53 in the parallel-type resistance segment unit 5 shown in fig. 12; reference numeral 55' denotes the structure of the third bridge resistor 55 in the parallel type segment unit 5 described in fig. 14. In this embodiment of the present application, theoretically, when digital signals of the segmented low-code bit segments are digital-to-analog converted by the parallel resistor segmentation unit 5, the digital signals of the low-code bit segments may be segmented again, so as to implement high-rate and high-precision digital-to-analog conversion of the digital signals under more bits.

Illustratively, since the input first digital signal is segmented, when the fifth resistor 315 is not provided, the equivalent resistance of the parallel resistor segmentation unit 5 of the lower code bit segment between the parallel resistor segmentation units 5 corresponding to the adjacent two code bit segments is equal to the lowest code bit of the M code bits of the parallel resistor segmentation unit 5 of the input higher code bit segment, and the resistance of the fourth resistor 52 corresponding to the parallel resistor segmentation unit of the higher code bit segment. When the fifth resistor 315 is set, the equivalent resistance value between the parallel resistor segment units 5 of the lower code segment and the fifth resistor 315 is equal to the lowest code bit of the M code bits of the parallel resistor segment units 5 of the input higher code segment, and the resistance value of the fourth resistor 52 is corresponding to the parallel resistor segment units of the higher code segment.

In some possible embodiments, as shown in fig. 14, the parallel-type resistor segmentation unit 5 further includes a third bridge resistor 55; the fourth coupling point 54 is coupled to the first coupling point 314 via a third bridge resistor 55.

In this embodiment, when there is only one parallel resistor segment unit 5, the equivalent resistance of the parallel resistor segment unit 5 needs to be the resistance of the first resistor 312 corresponding to the most code bit among the N code bits of the first digital signal. Therefore, after the first digital signal with multiple bits is segmented into N code bits and M code bits, the corresponding relationship between the resistance values of the fourth resistor 52 in the parallel resistor segmentation unit 5 and the first resistor 312 in the first conversion unit 31 needs to be adjusted. Since the equivalent resistance of the parallel-type resistor segmentation unit 5 is far smaller than the resistance of the fourth resistor 52 corresponding to the highest code bit of the M code bits of the first digital signal (the fourth resistor 52 with the smallest resistance under the binary code), the equivalent resistance of the parallel-type resistor segmentation unit 5 needs to be equal to the resistance of the first resistor 312 corresponding to the lowest code bit of the N code bits of the first digital signal (the resistance of the first resistor 312 with the largest binary code). In this case, the fourth resistor 52 needs to have a larger resistance value (particularly, when M code bits of the first digital signal are binary codes, the resistance value of the fourth resistor 52 corresponding to the lowest code bit of the M code bits of the first digital signal needs to be very large). Before the third bridge resistor 55 is provided, considering the fifth resistor 315, the equivalent resistance value of the parallel type resistor segment unit 5 is the sum of the equivalent resistances of the fourth resistor 52 and the parallel type adjustment resistor 53 connected in parallel. When the third bridge resistor 55 is provided, the equivalent resistance of the parallel resistor segment unit 5 is the sum of the equivalent resistances of the fourth resistor 52 and the fifth resistor 315 which are equivalently connected in parallel, plus the resistance of the third bridge resistor 55. Therefore, by setting the third bridge resistor 55, the fourth resistor 52 with an excessively large resistance value is not required to be set in the segmentation process, the implementation possibility of the scheme is increased, and meanwhile, the setting of the corresponding relation of the resistance values between the fourth resistor 52 and the first resistor 312 is more flexible, and the resistance value of the third bridge resistor 55 can be adjusted adaptively. When the M code bits of the first digital signal are further segmented, for example, into a fifth digital signal of a high code bit segment and a sixth digital signal of a low code bit segment, a third segmentation unit 53 is further provided in the parallel type resistance segmentation unit 5, and the structure of the third segmentation unit 53 is similar to that of the parallel type resistance segmentation unit 5. At this time, the equivalent resistance of the third segment unit 53 corresponding to the sixth digital signal of the low-order segment and the fifth resistor 315 needs to be equal to the resistance of the fourth resistor 52 corresponding to the lowest-order bit of the fifth digital signal in the parallel-type resistor segment unit 5 corresponding to the fifth digital signal of the high-order segment, and the resistance of the resistor 52' in the third segment unit 53 needs to be reduced. If the third bridge resistor 55 is also disposed in the third segment unit 53, the sum of the equivalent resistance of the third segment unit 53 corresponding to the sixth digital signal of the low-order segment and the resistance of the fifth resistor 315 and the resistance of the third bridge resistor 55 disposed in the third segment unit 53 is equal to the resistance of the fourth resistor 52 corresponding to the lowest-order bit of the fifth digital signal in the parallel-type resistor segment unit 5 corresponding to the fifth digital signal of the high-order segment, and at this time, the resistance of the resistor 52' in the third segment unit 53 can be satisfied without decreasing. Therefore, when a plurality of segments are performed on a digital signal, it is necessary to provide a plurality of parallel resistor segment units 5 as shown in fig. 12 in the manner described in fig. 12 and 13. If the third bridge resistor 55 is not provided in the parallel resistor segment unit 5, the requirements for the fourth resistor 52 in the parallel resistor segment unit 5 for each segment are very strict in the case of dividing the digital signal into multiple segments, and the resistance value of the fourth resistor 52 provided in the parallel resistor segment unit 5 representing the lower segment is also higher, and the implementation thereof is difficult in the case of not providing the third bridge resistor 55. When the third bridge resistor 55 is set in the plurality of parallel resistor segment units 5, the fourth resistor 52 without the need of an excessively large resistance value is realized by adjusting the value of the third bridge resistor 55, so that the signal segmentation of more segments of the digital signal can be completed. In addition, the equivalent resistance value corresponding to each segment of digital signal is constant regardless of the number of segments, and the equivalent impedance of each segment output is fixed due to the equivalent parallel structure. Under the condition of dividing into a plurality of sections of digital signals, the output end of the digital-to-analog converter 3 is always the first coupling point 314, the output impedance at the first coupling point 314 is the output impedance of the digital-to-analog converter 3, which is a fixed value and is far smaller than the resistance value of the first resistor 312, under the implementation mode, the output end of the digital-to-analog converter 3 can be directly connected with a load, in the traditional resistance type digital-to-analog converter, the resistance value of the connected resistor is also changed because the input digital signals are different, the output impedance is overlarge and the resistance value is not constant, and the load is difficult to directly carry at the output end, but a later-stage driving device and the like are required to be added. In implementing the electronic device 2 as shown in fig. 4, when the digital-to-analog converter 3 as shown in fig. 12, 13, 14 is applied, the driver amplifier 4 coupled to the output of the digital-to-analog converter 3 may be a trans-impedance amplifier (TIA).

In some possible embodiments, as shown in fig. 15, the second segmentation unit 323 in the second conversion unit 32 in the digital-to-analog converter 3 shown in fig. 7, 8, 9, 10, and 11 in the above embodiment may also be configured as the parallel resistor segmentation unit 5 shown in fig. 12, 13, and 14 to perform digital-to-analog conversion after segmenting the second digital signal. In fig. 15, reference numeral 51' denotes a structure of a fourth switch 51 in the parallel-type resistance segment unit 5 shown in fig. 12; reference numeral 52' denotes a structure of a fourth resistor 52 in the parallel type resistor segment unit 5 shown in fig. 12; reference numeral 53' denotes a structure of a third segment unit 53 in the parallel-type resistance segment unit 5 shown in fig. 12.

In the embodiment of the present application, the description about the second segment unit 323 being provided as the parallel type resistance segment unit 5 may refer to the description about the first segment unit 313 being provided as the parallel type resistance segment unit 5, so that the description is not repeated.

By including the digital-to-analog converter 3 with the structures shown in fig. 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15, the embodiment of the application reduces the equivalent impedance of the digital-to-analog converter 3 without reducing the resistance value of the resistor, thereby avoiding the influence of the on-resistance of the overcurrent switch on the linearity of digital-to-analog conversion due to the reduction of the resistance value of the resistor. Because the input first voltage or second voltage is constant, a large-size switch is not needed to be used as an overcurrent switch, and a small-size switch is used as an overcurrent switch, so that the problem of introducing more parasitic capacitance is avoided, and meanwhile, the linearity of post driving is higher. In addition, the output end of the existing digital-to-analog converter cannot be directly loaded, an in-phase amplifying device with a wide voltage input range needs to be designed, even an operational amplifier with a rail-to-rail input end is arranged at the input end, and when the digital-to-analog converter 3 shown in fig. 12, 13 and 14 is used, the output end of the digital-to-analog converter 3 can be directly loaded (such as a coupled transimpedance amplifier and the like) because the resistance value of the digital-to-analog converter 3 is constant, and the operational amplifier input point is a virtual place, so that the design of high linearity is easier to realize. In addition, the output impedance of the digital-to-analog converter 3 shown in fig. 12, 13, and 14 is small, and the output noise thereof is only 4kt×rout, where K is boltzmann constant, T is absolute temperature, and Rout is the output impedance of the digital-to-analog converter 3. Even if the current-mode digital-to-analog converter is intended to achieve the same noise level, it is necessary to additionally provide 1 to 2 large off-chip capacitors.

Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system, apparatus and module may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided in the present application, it should be understood that the disclosed devices, circuits, and apparatuses may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, and for example, the division of the unit modules is merely a logical function division, and there may be other division manners in which a plurality of modules or components may be combined or integrated into another device, or some features may be omitted or not performed in actual implementation. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, indirect coupling or communication connection of devices or modules, electrical, mechanical, or other form.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physically separate, i.e., may be located in one device, or may be distributed over multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in each embodiment of the present application may be integrated in one device, or each module may exist alone physically, or two or more modules may be integrated in one device.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The digital-to-analog converter is characterized by comprising a first voltage end, a second voltage end, a control unit and a first conversion unit, wherein the first conversion unit comprises N first switches and N first resistors;

The first voltage end is used for inputting a first voltage;

the second voltage end is used for inputting a second voltage;

the control unit is used for receiving a first digital signal, the first digital signal comprises N code bits, the N code bits are in one-to-one correspondence with the N first switches, and the control unit respectively controls the N first switches according to the N code bits of the first digital signal, so that a first end of a first resistor corresponding to the N first switches is coupled to the first voltage end or the second voltage end; a second end of the N first resistors is coupled to a first coupling point; the first coupling point is used for outputting first analog signals corresponding to N code bits of the first digital signals.

2. The digital to analog converter of claim 1, wherein said first digital signal further comprises E code bits, said E code bits of said first digital signal being lower than said N code bits of said first digital signal; the digital-to-analog converter also comprises a resistor voltage division unit and a second conversion unit; the second conversion unit comprises N second switches and N second resistors;

the control unit is further used for generating a second digital signal according to the first digital signal; the control unit is used for respectively controlling the N second switches according to the N code bits of the second digital signal, so that the first ends of second resistors corresponding to the N second switches are coupled to the first voltage end or the second voltage end; a second end of the N second resistors is coupled to a second coupling point; the second coupling point is used for outputting a second analog signal corresponding to the second digital signal; the value of the second digital signal is larger than that of the first digital signal;

A first input end of the resistor voltage dividing unit is coupled to the first coupling point and is used for inputting the first analog signal, and a second input end of the resistor voltage dividing unit is coupled to the second coupling point and is used for inputting the second analog signal; the control unit is used for controlling the output end of the resistor voltage division unit to output a third analog signal corresponding to the sum of the N code bits of the first digital signal and the E code bits of the first digital signal according to the E code bits of the first digital signal.

3. The digital-to-analog converter according to claim 2, wherein the resistor divider unit specifically includes an output selection switch and E third resistors; one end of the E third resistors after being connected in series is used as a first input end of the resistor voltage dividing unit to be coupled with the first coupling point, and the other end of the E third resistors after being connected in series is used as a second input end of the resistor voltage dividing unit to be coupled with the second coupling point;

the control unit is used for coupling the selection input end of the output selection switch to a third coupling point according to the value of E code bits of the first digital signal, the third coupling point is a first end or a second end of one of the E third resistors, and the sum of the resistance values of all the third resistors between the third coupling point and the first coupling point corresponds to the value of E code bits of the first digital signal.

4. A digital-to-analog converter according to claim 2 or 3, characterized in that it further comprises a first bridge resistor; the output end of the first conversion unit is coupled to the first input end of the resistor voltage dividing unit through the first bridging resistor.

5. The digital to analog converter according to any of claims 2-4, further comprising a second bridge resistor; the output end of the second conversion unit is coupled to the second end of the second resistor module through the second bridge resistor.

6. The digital to analog converter of claim 5, wherein E code bits of said first digital signal are thermometer codes; and the resistance values of the E third resistors are equal.

7. The digital to analog converter of any of claims 2-6, wherein N code bits of the second digital signal are thermometer codes; and the resistance values of the N second resistors are equal.

8. The digital to analog converter according to any of claims 2-6, wherein N code bits of the second digital signal are binary codes; and among the N second resistors, between two second resistors corresponding to adjacent code bits in N code bits of the second digital signal, the resistance of the second resistor corresponding to the lower code bit in the adjacent code bits in the N code bits of the second digital signal is twice the resistance of the second resistor corresponding to the higher code bit in the N code bits of the second digital signal.

9. The digital to analog converter of any of claims 2-8, wherein the first digital signal further comprises M code bits; the M code bits of the first digital signal are higher than the E code bits of the first digital signal and lower than the N code bits of the first digital signal; the first conversion unit further comprises a first segmentation unit; the second conversion unit further comprises a second segmentation unit; the output end of the first segmentation unit and the first coupling point are coupled to the first input end of the resistor voltage division unit; the output end of the second conversion unit and the second coupling point are coupled to the second input end of the resistor voltage dividing unit;

the control unit is further configured to control the first segmentation unit to output a fourth analog signal corresponding to M code bits of the first digital signal to the first input end of the resistor voltage division unit according to the M code bits of the first digital signal; generating M code bits of a second digital signal; the M code bits of the second digital signal are lower than the N code bits of the second digital signal; and controlling the second segmentation unit to output a fifth analog signal corresponding to the M code bits of the second digital signal to the second input end of the resistor voltage division unit according to the M code bits of the second digital signal.

10. The digital-to-analog converter of claim 9, wherein the first and second segment units are parallel-type resistive segment units; the parallel type resistor segmentation unit comprises M fourth switches and M fourth resistors, wherein the M fourth switches and the M fourth resistors are in one-to-one correspondence with M code bits of the first digital signal or M code bits of the second digital signal;

the control unit is used for respectively controlling the M fourth switches according to the M code bits of the first digital signal or the M code bits of the second digital signal, so that the first ends of the fourth resistors corresponding to the M fourth switches are coupled to the first voltage end or the second voltage end; second ends of the M fourth resistors are coupled to a fourth coupling point; the fourth coupling point is used for outputting a fourth analog signal corresponding to M code bits of the first digital signal or a fifth analog signal corresponding to M code bits of the second digital signal.

11. The digital to analog converter of claim 10, wherein said parallel resistor segment unit further comprises a third bridge resistor; the fourth coupling point is coupled to a first end of the third bridge resistor; the second end of the third bridge resistor is used as the output end of the parallel resistor segmentation unit.

12. Digital-to-analog converter according to claim 10 or 11, characterized in that the M code bits of the first digital signal or the M code bits of the second digital signal are binary codes; and in the M fourth resistors, between two fourth resistors corresponding to M code bits of the first digital signal or adjacent code bits in M code bits of the second digital signal, the resistance value of the fourth resistor corresponding to the M code bits of the first digital signal or the lower code bit of the adjacent code bits in M code bits of the second digital signal is twice the resistance value of the fourth resistor corresponding to the M code bits of the first digital signal or the higher code bit of the adjacent code bits in M code bits of the second digital signal.

13. Digital-to-analog converter according to claim 10 or 11, characterized in that the M code bits of the first digital signal or the M code bits of the second digital signal are thermometer codes; and the resistance values of the M fourth resistors are equal.

14. The digital to analog converter according to any of claims 2-13, wherein the second conversion unit further comprises a fifth resistor; a first end of the fifth resistor is coupled to the first voltage end to input the first voltage or coupled to the second voltage end to input the second voltage; a second end of the fifth resistor is used for being coupled to the first coupling point; the resistance value of the fifth resistor is equal to the resistance value of the resistor corresponding to the lowest code bit of the second digital signal.

15. The digital to analog converter of claim 14, wherein said second conversion unit further comprises a fifth switch; a first end of the fifth resistor is coupled with the fifth switch; the control unit is used for controlling the first end of the fifth resistor to be coupled to the first voltage end through the fifth switch or controlling the first end of the fifth resistor to be coupled to the second voltage end through the fifth switch.

16. The digital to analog converter of any of claims 1 to 15, wherein N code bits of the first digital signal are binary codes; and in the N first resistors, between two first resistors corresponding to adjacent code bits in N code bits of the first digital signal, the resistance of the first resistor corresponding to the lower code bit in the N code bits of the first digital signal is twice that of the first resistor corresponding to the higher code bit in the N code bits of the first digital signal.

17. The digital to analog converter of any of claims 1 to 15, wherein the N code bits of the first digital signal are thermometer codes; the resistance values of the N first resistors are equal.

18. The digital to analog converter according to any of claims 1-17, wherein the first conversion unit further comprises a sixth resistor; a first end of the sixth resistor is coupled to the first voltage end to input the first voltage or coupled to the second voltage end to input the second voltage; the resistance value of the sixth resistor is equal to the resistance value of the resistor corresponding to the lowest code bit of the first digital signal.

19. The digital to analog converter of claim 18, wherein said first conversion unit further comprises a sixth switch; a first end of the sixth resistor is coupled with the sixth switch; the control unit is used for controlling the first end of the sixth resistor to be coupled to the first voltage end through the sixth switch or controlling the first end of the sixth resistor to be coupled to the second voltage end through the sixth switch.

20. A digital-to-analog conversion circuit comprising a digital-to-analog converter and a drive amplifier as claimed in any one of claims 1 to 19; the drive amplifier is coupled to an output of the digital-to-analog converter; the digital-to-analog converter is used for inputting a digital signal, generating an analog signal and outputting the analog signal to the driving amplifier, and the driving amplifier is used for amplifying the analog signal.

21. An electronic device comprising a digital-to-analog converter as claimed in any one of claims 1-19 or comprising a digital-to-analog conversion circuit as claimed in claim 20; the digital-to-analog converter or the digital-to-analog conversion circuit is used for generating an analog signal according to an input digital signal.