CN117558331A - Method and device for detecting address stability of high-density test chip - Google Patents
Method and device for detecting address stability of high-density test chip Download PDFInfo
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
Abstract
The invention provides a detection method and a device for high-density test of chip address stability, comprising the following steps: acquiring a first address signal of the test chip; predefining error correction coding rules; coding based on the first address signal according to the error correction coding rule to obtain an error correction code; obtaining a second address signal based on the first address signal and the error correction code; selecting at least one signal bit in the second address signal to obtain a third address signal; monitoring the third address signal connection pad to obtain a first sequence signal; and determining the stability of the first address signal according to the first sequence signal. The invention monitors the correctness and stability of the internal address by using limited information related to the address, can realize detection more efficiently, saves pad resources and improves the density of the device to be detected.
Description
Technical Field
The invention belongs to the field of chip design and manufacturing, and particularly relates to a detection method and device for high-density test of chip address stability.
Background
High density test chips are chips with large memory capacity, which can store more complex applications and data, typically from a few MB to a few GB, even TB. The high-density chip can store complex application programs and data; the high-density chip has higher power consumption, and is suitable for equipment needing high performance, such as smart phones, notebook computers and the like. In a high-density test chip, the number of devices to be tested is large, and the number of address bits is large (> 10); on the other hand, the correctness of the test result directly determined by the correctness of the address; it is therefore necessary to monitor the correctness of the address. In a high-density test chip, address signals are generated entirely by internal circuitry. Because the address signal directly determines which device to be tested is selected, the correct stability of the address signal is ensured, or the correctness and stability of the address signal can be monitored, which is the basis for ensuring the reliability of the measured data.
In the prior art, address stability test for high-density test chips is mainly performed by directly leading all address signals to a bonding pad, so that the problem of taking up too many bonding pads is that the area of the chip is wasted, the density of devices to be tested is reduced, and the correctness and the accuracy of the address signals cannot be detected.
Disclosure of Invention
The invention provides a method and a device for detecting the address stability of a high-density test chip to monitor the address abnormality as much as possible, and can lead the sequence of the result to have no period and to have uniqueness, thereby improving the correctness and the accuracy of detecting the address signal, saving resources and improving the density of devices to be detected.
In order to achieve the above purpose, the technical scheme of the invention is realized as follows:
the first aspect of the present invention provides a method for detecting address stability of a high-density test chip, including: acquiring a first address signal of the test chip; predefining error correction coding rules; coding based on the first address signal according to the error correction coding rule to obtain an error correction code; obtaining a second address signal based on the first address signal and the error correction code; selecting at least one signal bit in the second address signal to obtain a third address signal; monitoring the third address signal connection pad to obtain a first sequence signal; and determining the stability of the first address signal according to the first sequence signal. The step of acquiring the first address signal of the test chip and the predefined error correction coding rule is not sequential.
Based on the above scheme, the predefined error correction coding rule includes at least one of: coding scheme, number of bits of error correction coding. Wherein the coding mode is at least one of parity check, cyclic redundancy check, low density parity check coding, turbo code, polarization code and the like. Of course, two or more types of error correction codes may be used simultaneously, and the number of bits of error correction codes exceeds 1 bit.
If the number of bits of the error correction code is 0, the second address signal is the same as the first address signal, a certain bit in the first address signal, for example, the lowest bit, can be directly led out of the bonding pad to directly obtain a first sequence signal, and if the number of bits of the error correction code is greater than 0, the error correction code is added into the first address signal to obtain the second address signal.
Based on the above scheme, when the number of bits of the error correction coding is 0, the second address signal is identical to the first address signal.
Based on the above scheme, the selecting at least one signal bit in the second address signal as the third address signal includes: and directly selecting the lowest bit in the second address signal corresponding to the first address signal as a third address signal.
Based on the scheme, the first address signals are sequentially increased or sequentially decreased, and the values presented by the first sequence signals are periodic sequences; determining the stability of the first address according to the first sequence signal comprises: when the first sequence signal is a periodic sequence, the first address is judged to be stable.
Based on the above scheme, the selecting at least one signal bit in the second address signal as the third address signal includes: and selecting signal bits corresponding to the error correction code in the second address signal, and taking the signal bits as a third address signal.
Based on the above scheme, determining the stability of the first address according to the first sequence signal includes: judging an address segment of the first address in the whole test address space based on the first sequence signal; and judging the stability of the first address by comparing whether the first sequence signal corresponds to the address segment correctly or not.
Based on the above scheme, monitoring the third address signal connection pad to obtain a first sequence signal, including: monitoring the third address signal connection pad to obtain a first sequence signal with the sequence length larger than N; based on the first sequence signal, an address segment of the first address in the whole test address space can be positioned; the value of N is determined according to the test address space and the error correction coding rule.
Based on the above scheme, the selecting at least one signal bit in the second address signal as the third address signal includes: selecting signal bits corresponding to error correction codes in the second address signals as fourth address signals; selecting at least one signal bit corresponding to the first address signal in the second address signal as a fifth address signal; the third address signal includes the fourth address signal and a fifth address signal.
Based on the scheme, the third address signal is connected to pad monitoring to obtain a first sequence signal; determining the stability of the first address according to the first sequence signal comprises: monitoring the fourth address signal connection pad to obtain a second sequence signal; monitoring the fifth address signal connection pad to obtain a third sequence signal; and judging the stability of the first address by using the second sequence signal and the third sequence signal.
A second aspect of the present invention provides a test apparatus for high-density testing of chip address stability, comprising: the acquisition module is used for acquiring a first address signal of the test chip; a predefining module for predefining error correction coding rules; the analysis module is used for coding based on the first address signal according to the error correction coding rule to obtain an error correction code; the first selecting module is used for obtaining a second address signal based on the address signal and the error correction code; the second selecting module is used for selecting at least one signal bit in the second address signal to obtain a third address signal; the establishing module is used for monitoring the third address signal connection pad to obtain a first sequence signal; and the confirmation module is used for determining the stability of the first address signal according to the first sequence signal.
A third aspect of the present invention provides an electronic apparatus, comprising: a memory; and the processor is connected with the memory and is used for executing the computer executable instructions stored on the memory and realizing the detection method for the high-density test chip address stability.
A fourth aspect of the present invention provides a computer storage medium having stored thereon computer-executable instructions; the computer executable instructions, when executed, enable the detection method for high density test chip address stability provided in any one of the above.
Compared with the prior art, the invention has the main beneficial effects that: the local address signals are led out of the bonding pad to realize the address detection function, meanwhile, error correction coding is carried out on the address signals in the chip, and secondary verification is carried out on the address detection function, so that the correctness of all addresses is detected, and the accuracy of detection results is improved.
Drawings
FIG. 1 is a schematic flow chart of a method for detecting address stability of a high-density test chip according to the present invention;
FIG. 2 is a schematic flow chart of a device for detecting address stability of a high-density test chip according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
So that the manner in which the features and aspects of the present application can be understood in more detail, a more particular description of the invention, briefly summarized above, may be had by reference to the appended drawings, which are not intended to be limiting of the present application.
As shown in fig. 1, an embodiment of the present disclosure provides a method for detecting address stability of a high-density test chip, the method including:
s110: acquiring a first address signal of the test chip;
s120: predefining error correction coding rules;
s130: coding based on the first address signal according to the error correction coding rule to obtain an error correction code;
s140: obtaining a second address signal based on the first address signal and the error correction code;
s150: selecting at least one signal bit in the second address signal to obtain a third address signal;
s160: connecting the third address signal to pad monitoring to obtain a first sequence signal;
s170: and determining the stability of the first address according to the first sequence signal.
The address signal refers to a signal representing an address in binary; for test address signals of a high-density test chip, specific address signals are completely generated by the internal circuit of the chip on the basis of knowing the address space of the test address signals. Because the address signal directly determines which device to be tested on the high-density test chip is selected, the correct stability of the address signal is ensured, or the correctness and stability of the address signal can be monitored, which is the basis for ensuring the reliability of the measured data.
In an embodiment of the present invention, the S110 may include: the first address signal of the test chip is acquired, wherein the acquisition refers to that the detection method needs to acquire the first address for subsequent error correction coding and the like, but if a technician performing the test cannot monitor all address bits of the first address by a connection pad (pad), the technician does not know the current first address. That is, the technician is known to the address space, i.e. the address space segment to be tested is known, but it is uncertain whether the current test address, i.e. the first address, generated inside the chip during the test, is generated correctly, which is what we need to monitor whether the generation of the first address is correct and stable during the whole test.
In some embodiments, the S120 may include: the predefined error correction coding rules include determining the number of bits and the coding scheme of the error correction coding. When the number of error correction coded bits is 0, then no error correction coding is used. In the current high-density test chip internal address signal generation mode, the address signals are sequentially increased, namely the first addresses are sequentially increased, if the lowest order bit in the address of the first address signal is connected to a bonding pad, the obtained first sequence signal presents a value which is a 010101 periodic sequence, and the time length of the period is twice the input clock period (namely two frequency division). The sequential increment of the address signals complements that the number of bits of the first address signal is fixed, but the address represented by the first address signal is incremented; since the sequence presented by the first sequence signal is periodic, only partial situations can be monitored for address correctness and stability. For example, when the address changes to: 01 2 3 5 6 7 8 9 10 the first sequence signal, e.g. the presented sequence, is 0101 10101 0, an instability can be detected because there are two consecutive 1's in the first sequence signal, e.g. the sequence, which necessarily corresponds to an incorrect address; alternatively, when the first address signal is changed to: 01 2 3 6 7 8 9 10, the first sequence signal exhibits a sequence of 010101 010, at which time no anomalies are observed by the first sequence signal and therefore no address anomalies can be detected.
In some embodiments, the S130 may include: using error correction coding (Error Correction Code, ECC) to increase the number of error correction coding bits based on the number of bits of the first address signal; such that the total number of bits is the number of address signal bits plus the number of error correction code encoded bits, wherein the error correction code comprises at least many other coding schemes, such as cyclic redundancy check (CRC, cyclic redundancy check), low-density parity-check code (LDPC), turbo code, polar code, etc. With a better error correction coding, the sequence presented by the first sequence signal should be made to have the following characteristics: no period or no apparent period; a sequence should be unique throughout the address space, and the shorter the length of the sequence, the better.
The step S150 selects the address signal in the second address signal to obtain a third address signal, specifically, selects at least one signal bit from the address signal bits in the second address signal to obtain the third address signal, and generally selects the third address signal from the error correction code bits, because the information in the error correction code bits can generally express the correctness of the address signal, but can also select the signal bit corresponding to the first address according to the requirement.
And in the step S160, selecting signal bits corresponding to error correction codes in the second address signals, and connecting the signal bits to an external interface pad for monitoring to obtain a first sequence signal.
In the step S160, the third address signal is connected to an external interface pad, so as to obtain a first sequence signal; at least one signal bit in the second address signal can be selected as a third address signal, namely, the signal bit corresponding to the first address and the signal bit corresponding to the error correction code are selected at the same time to be monitored by a connection pad, so that a first sequence signal is obtained. Selecting signal bits corresponding to error correction codes in the second address signals as fourth address signals; selecting at least one signal bit corresponding to the first address signal in the second address signal as a fifth address signal; the third address signal includes the fourth address signal and a fifth address signal. Monitoring the fourth address signal connection pad to obtain a second sequence signal, and obtaining the second sequence signal; monitoring the fifth address signal connection pad to obtain a third sequence signal; and judging the stability of the first address by using the second sequence signal and the third sequence signal.
In the step S170, the stability of the first address is determined by using the characteristics of the first sequence signal, and the first sequence obtained correspondingly has different characteristics according to the selection mode of the third address.
For example, if the lowest signal bit corresponding to the first address is selected as the third address signal, the first sequence is characterized by a periodic signal. For example, when the address changes to: 01 2 3 5 6 7 8 9 10 the first sequence signal, e.g. the presented sequence, is 0101 10101 0, an instability can be detected because there are two consecutive 1's in the first sequence signal, e.g. the sequence, which necessarily corresponds to an incorrect address; alternatively, when the first address signal is changed to: 01 2 3 6 7 8 9 10, the first sequence signal exhibits a sequence of 010101 010, at which time no anomalies are observed by the first sequence signal and therefore no address anomalies can be detected.
For example, when the signal bit corresponding to the error correction code is selected as the third address signal, the characteristics of the first sequence signal include: the first sequence signal is not a periodic sequence and is unique throughout an address space when a length of the first sequence signal is greater than a preset threshold. This threshold is determined from the test address space and the error correction coding rules. At this time, determining the stability of the first address according to the first sequence signal includes: judging an address segment of the first address in the whole test address space based on the first sequence; and judging the stability of the first address by comparing whether the first sequence and the address segment correspond correctly or not. Thus, when monitoring for a first sequence signal, at least one first sequence signal having a sequence length greater than a threshold value is typically monitored, based on which an address segment of the first address in the entire test address space can be located.
If the expected values of the correct preset first address signals at different moments are known in the step S170, the expected values of the correct first sequence signals at different moments, that is, the known third address signals, can be calculated according to the expected values. If the actually observed first sequence signal does not match the expected value at a certain time, it can be determined accordingly that the internal actual first address signal at that time is incorrect. If the same, the stability of the first address signal can be considered. By the method, error correction coding is carried out on the address signals in the chip, and the address detection function is verified for the second time, so that the correctness of partial addresses is detected, and the accuracy of a certain detection result is improved.
Embodiment one:
when the predefined error correction coding rule defines that the error correction coding bit number is 0, the second address signal is identical to the first address signal at this time, namely the first address signal is actually obtained. The step S110 is to acquire a first address signal of the test chip, where the first address signal is a first address signal planned to be generated in the test process as known in table 1. Taking the first address signal as an example of four bits, when the error correction coding bit number is 0, the first address signal is identical to the second address signal. The least significant bit of the first address signal or the second address signal is preset to be the third address signal, when the actual measurement process is performed, the actually generated first address signal, that is, the actual address first signal, may be the same as or different from the known first address signal, and when the third address signal is connected to the external interface pad, a first sequence signal is obtained: 011010. if the first sequence signal actually observed does not match the expected value, i.e., the known third address signal, at a certain time, as shown at time 3 in table 1, it can be determined therefrom that the internal a-bit address signal at this time is incorrect or stable.
TABLE 1 known address Signal to actual Address Signal correspondence
| Time of day | Knowing the first address signal | Third address signal | Actual first address signal |
| 1 | 0000 | 0 | 0000 |
| 2 | 0001 | 1 | 0001 |
| 3 | 0010 | 0 | 0011 |
| 4 | 0011 | 1 | 0100 |
| 5 | 0100 | 0 | 0101 |
| 6 | 0101 | 1 | 0110 |
It should be noted that since only the first sequence signal, i.e. the lowest order signal, can be observed from the external interface pad, the remaining bits of the first address signal are not observable, and thus by means of the present rule only, all incorrect cases cannot be found 100%. For example, at a certain moment, the first address signal is known to be 0100, and the third address signal is known to be 0; but if the actual first address signal is 0110, the first sequence signal is still 0, and the rule still results in correct stability.
Example two
Although error correction coding is not necessary, no error correction coding is actually used in the engineering. However, error correction coding is a means for realizing more efficient monitoring, and error correction coding is to add some redundant symbols into an information sequence to form a related symbol sequence, namely a code word; the correlation property class between symbols is used to detect errors and correct errors during decoding. Different error correction coding methods have different error detection or correction capabilities. In general, the greater the cost, the greater the error detection or correction capability, and the more signal bits at the cost of occupying more pads. . The error correction coding mode at least comprises parity check, cyclic redundancy check (CRC, cyclic redundancy check), low-density parity-check (LDPC), turbo code and polarization code. The present invention is not limited to the above-mentioned encoding method, for example, the encoding method of parity check is that no matter how many bits of data bits, the check bit is only one bit; if one number contained in the data bit and the error correction bit is odd, the data bit and the error correction bit are called odd check; if the total of 1 number of data bits and error correction bits is an even number, it is called even parity. Generally, one-bit errors occur in the process of data transmission, and parity check codes can find odd errors; for example, before data transmission, a check bit is obtained, and after the data transmission, a check bit is obtained again, and in parity check, an exclusive or method is generally adopted by comparing whether two check bits are identical, if the result is 1, an odd number of errors are indicated, and if the result is 0, a correct or even number of errors are indicated.
The number of bits of the error correction code refers to the number of errors that can be found and corrected, and the number of bits of the error correction code may be a predetermined empirical value or an experimental value such as 0, 1, 2, or 3.
The expected values of the first address signals at different times are currently known, which is determined by the overall test address space and the address signal generation circuit design within the high-density test chip. The error correction coding rules are also predefined, and the correspondence rules from the first address signal or the second address signal to the third address signal or the first sequence signal are preset, which is also determined by the circuit design. The actual change of the first address signal at different moments is often reflected on the third address signal, and the first sequence signal can be obtained through the connection and monitoring of the bonding pad. If the variation of the first address signal does not match the expectation, it is possible to present a sequence on the first sequence signal that does not match the expectation.
A parity code is used, which refers to: the original data and the check bits are always contained, and the number of binary 1 s is even (or odd). At this time, the number of bits of the error correction code is 1, that is, the number of bits of the error correction code is the same as that of the first sequence signal, and the unique error correction code is connected to the first sequence signal;
for example, when the first address signal is=010001, the error correction code is 0 (2 binary 1 s in total, even); when the first address signal is 01100, the error correction code is 1 (3 binary 1 s, odd number in total). Therefore, it can be verified that under the configuration, the sequence presented by the first sequence signal has no period, and when the continuous sequence length of the first sequence signal is greater than 515, the first sequence signal is unique in the whole address space, the address segment of the corresponding first address in the whole test address space can be judged based on the first sequence, and then the stability of the first address is judged by comparing whether the first sequence signal corresponds correctly with the address segment. Thus, in this embodiment, a vast majority of address anomalies can be detected. A better error correction coding should be such that the sequence of signal bits of the first sequence exhibits the following characteristics: no period or no apparent period; a sequence should be unique throughout the address space, and the shorter the length of the sequence, the better.
As shown in fig. 2, a flow chart of a detection apparatus for high-density testing of chip address stability is provided in the present embodiment;
an acquiring module 110, configured to acquire a first address signal of the test chip;
a predefined module 120 for predefining error correction coding rules;
an analysis module 130, configured to encode based on the first address signal according to the error correction encoding rule to obtain an error correction code;
a first selecting module 140, configured to obtain a second address signal based on the address signal and the error correction code;
a second selecting module 150, configured to select at least one signal bit in the second address signal to obtain a third address signal;
a building module 160, configured to monitor the third address signal connection pad to obtain a first sequence signal;
a confirmation module 170, configured to determine stability of the first address according to the first sequence signal.
In some embodiments, the acquisition module 110, the predefined module 120, the analysis module 130, the first selection module 140, the second selection module 150, the establishment module 160, and the determination module 170 may be program modules; the program modules may implement the operations of the various modules described above when executed by a processor.
In other embodiments, the acquiring module 110, the predefining module 120, the analyzing module 130, the first selecting module 140, the second selecting module 150, the establishing module 160, and the determining module 170 may be a soft-hard combination module; the soft and hard combined die block comprises but is not limited to: various programmable arrays; the programmable array includes, but is not limited to: a field programmable array and/or a complex programmable array.
In still other embodiments, the acquisition module 110, the predefined module 120, the analysis module 130, the first selection module 140, the second selection module 150, the setup module 160, and the determination module 170 may be purely hardware modules; the pure hardware modules wrap around but are not limited to: an application specific integrated circuit.
As shown in fig. 3, an embodiment of the present disclosure provides an electronic device, which is characterized in that the electronic device includes:
a memory;
a processor, coupled to the memory, for enabling the implementation of the methods provided in any of the preceding embodiments, e.g., performing the methods as shown in any of fig. 1-2, by executing computer-executable instructions stored on the memory.
The electronic device may be a terminal device and/or a server in a service platform.
As shown in fig. 3, the electronic device may also include a network interface that may be used to interact with a peer device over a network.
Embodiments of the present disclosure provide a computer storage medium having stored thereon computer-executable instructions; the computer-executable instructions, when executed by a processor, enable the method provided by any of the foregoing embodiments, such as performing the method as shown in any of figures 1-2.
The detection method for high-density test chip address stability provided by the embodiment of the disclosure can be applied to various electronic devices, including but not limited to: an integrated circuit.
It should be understood that in several embodiments provided in this application, the disclosed apparatus and methods may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (14)
1. A method for testing the address stability of a chip at high density, comprising:
acquiring a first address signal of the test chip;
predefining error correction coding rules;
coding based on the first address signal according to the error correction coding rule to obtain an error correction code;
obtaining a second address signal based on the first address signal and the error correction code;
selecting at least one signal bit in the second address signal to obtain a third address signal;
monitoring the third address signal connection pad to obtain a first sequence signal;
and determining the stability of the first address signal according to the first sequence signal.
2. A method for testing chip address stability at high density according to claim 1, wherein the predefined error correction coding rules comprise at least one of:
a coding mode; error correction coded bits.
3. The method for detecting the address stability of a high-density test chip according to claim 2, wherein the second address signal is identical to the first address signal when the number of bits of the error correction code is 0.
4. A method for testing the address stability of a chip according to claim 3, wherein said selecting at least one signal bit of said second address signal as a third address signal comprises:
and directly selecting the lowest bit in the second address signal corresponding to the first address signal as a third address signal.
5. A method for detecting address stability of a high-density test chip according to claim 3, wherein the first address signals are sequentially increased or sequentially decreased, and the first sequence signals exhibit values which are periodic sequences;
determining the stability of the first address according to the first sequence signal comprises: when the first sequence signal is a periodic sequence, the first address is judged to be stable.
6. The method for detecting address stability of high-density test chip according to claim 1, wherein said selecting at least one signal bit of said second address signal as a third address signal comprises:
and selecting signal bits corresponding to the error correction code in the second address signal, and taking the signal bits as a third address signal.
7. The method for detecting the address stability of a high-density test chip according to claim 6, wherein determining the stability of the first address based on the first sequence signal comprises:
judging an address segment of the first address in the whole test address space based on the first sequence signal;
and judging the stability of the first address by comparing whether the first sequence signal corresponds to the address segment correctly or not.
8. The method for detecting address stability of high-density test chip as claimed in claim 7, wherein monitoring said third address signal connection pad to obtain a first sequence of signals comprises:
monitoring the third address signal connection pad to obtain a first sequence signal with the sequence length larger than N; based on the first sequence signal, an address segment of the first address in the whole test address space can be positioned;
the value of N is determined according to the test address space and the error correction coding rule.
9. The method for detecting address stability of high-density test chip according to claim 1, wherein said selecting at least one signal bit of said second address signal as a third address signal comprises:
selecting signal bits corresponding to error correction codes in the second address signals as fourth address signals;
selecting at least one signal bit corresponding to the first address signal in the second address signal as a fifth address signal;
the third address signal includes the fourth address signal and a fifth address signal.
10. The method for detecting address stability of high-density test chip according to claim 9, wherein the third address signal is connected to pad monitoring to obtain a first sequence signal; determining the stability of the first address according to the first sequence signal comprises:
monitoring the fourth address signal connection pad to obtain a second sequence signal;
monitoring the fifth address signal connection pad to obtain a third sequence signal;
and judging the stability of the first address by using the second sequence signal and the third sequence signal.
11. The method for detecting the address stability of a high-density test chip according to claim 2, wherein the coding mode is at least one of parity check, cyclic redundancy check, low-density parity check coding, turbo code and polarization code.
12. A test device for high density testing of chip address stability, comprising:
the acquisition module is used for acquiring a first address signal of the test chip;
a predefining module for predefining error correction coding rules;
the analysis module is used for coding based on the first address signal according to the error correction coding rule to obtain an error correction code;
the first selecting module is used for obtaining a second address signal based on the address signal and the error correction code;
the second selecting module is used for selecting at least one signal bit in the second address signal to obtain a third address signal;
the establishing module is used for monitoring the third address signal connection pad to obtain a first sequence signal;
and the confirmation module is used for determining the stability of the first address signal according to the first sequence signal.
13. An electronic device, comprising:
a memory;
a processor, coupled to the memory, for executing computer-executable instructions stored on the memory and for implementing the method for detecting address stability of a high-density test chip provided in any one of claims 1 to 11.
14. A computer storage medium having stored thereon computer executable instructions; the computer-executable instructions, when executed, enable the detection method for high density test chip address stability provided in any one of claims 1 to 11.
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