CN113098632B - Detection method of communication chip - Google Patents
Detection method of communication chip Download PDFInfo
- Publication number
- CN113098632B CN113098632B CN202110456596.6A CN202110456596A CN113098632B CN 113098632 B CN113098632 B CN 113098632B CN 202110456596 A CN202110456596 A CN 202110456596A CN 113098632 B CN113098632 B CN 113098632B
- Authority
- CN
- China
- Prior art keywords
- communication chip
- communication
- module
- current
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
Abstract
The invention discloses a detection method of a communication chip, which comprises the following steps: reading ID information in a communication chip to be tested, and respectively checking whether the communication chip to be tested is normally contacted with a power supply and whether the communication between the communication chip and a signal generating unit is normal; and B: reading the output current of the power supply and comparing the output current with the theoretical current; and C: the signal generating unit is used for executing read-write operation on the communication chip so as to detect whether the read-write function of the communication chip is normal or not; step D: judging whether an internal register of the communication chip is invalid or not according to the execution result of the tested communication chip according to a set algorithm; step E: functional signals are input to the communication chip through the signal generating unit, and whether functional data output by the communication chip are consistent with expected data or not is judged. The function test can be carried out on the communication chip by inputting the function signal through the signal generating unit, and the performance of the communication chip can be comprehensively detected.
Description
Technical Field
The invention relates to the technical field of electronic chips, in particular to a detection method of a communication chip.
Background
In recent years, the demand of communication chips has increased greatly, and new vitality is injected into the global semiconductor industry, so that the communication chips are widely applied to the industries of mobile communication, wireless internet and wireless data transmission, which will become the largest application market of the global semiconductor chip industry in the beginning of the 21 st century.
The traditional test of the communication chip mainly comprises the step of repeatedly carrying out basic read-write operation test on the communication chip, and the mode can detect the basic read-write function of the communication chip, but lacks the detection of the function of the communication chip and cannot comprehensively detect the performance of the communication chip.
Disclosure of Invention
In order to overcome the defects of the prior art, the present invention provides a method for testing a communication chip, which can input a functional signal through a signal generating unit to perform a functional test on the communication chip, so as to comprehensively test the performance of the communication chip.
The purpose of the invention is realized by adopting the following technical scheme:
a detection method of a communication chip comprises the following steps,
step A: reading ID information in the communication chip to be tested, and respectively checking whether the contact between the communication chip to be tested and a power supply is normal or not and whether the communication between the communication chip and a signal generating unit is normal or not; if the two are normal, executing the next step; if not, connecting the line again;
and B, step B: reading the output current of a power supply, comparing the output current with a theoretical current, and if the output current is greater than the theoretical current, indicating that a circuit is short-circuited, and adjusting the output current; if the output current is less than or equal to the theoretical current, indicating that the circuit current is normal, and executing the next step;
and C: executing read-write operation on the communication chip by using a signal generating unit to detect whether the read-write function of the communication chip is normal, entering the next step if the read-write function is normal, and stopping detection if the read-write function is normal;
step D: judging whether an internal register of the communication chip fails or not according to the execution result of the tested communication chip according to a set algorithm, if the internal register fails, entering the next step, and if not, stopping detection;
step E: inputting a functional signal to the communication chip through the signal generating unit, judging whether functional data output by the communication chip is consistent with expected data or not, and indicating that the communication chip is a good chip when the functional data is consistent with the expected data; otherwise, the inconsistent functional data and the expected data are fed back to the signal generating unit for storage and analysis.
Further, in the step a, the ID information includes a rated voltage, a rated current, a timing and a functional description of the communication chip.
Further, in the step B, the theoretical current ITheory of things=IForehead (forehead)n/4, wherein ITheory of thingsIs theoretical current of chip，IForehead (forehead)The rated current of the chip and n are the pin number of the chip.
Further, in the step C, the signal generating unit includes a transmission module, a power module, an FPGA control module, a program storage module, and a communication interface module in signal connection with the communication chip to be tested, the transmission module, the FPGA control module, and the program storage module are respectively electrically connected with the power module, and the transmission module, the program storage module, and the communication interface module are respectively in signal connection with the FPGA control module.
Further, the signal generating unit further comprises an address selection module for selecting a communication chip, and the address selection module is in signal connection with the FPGA control module.
Furthermore, the signal generating unit further comprises a network interface, and the network interface is in signal connection with the transmission module.
Further, the detection method further comprises the following steps: and when the functional data is consistent with the expected data, judging whether the output current meets a set condition, if so, indicating that the communication chip is a good chip, otherwise, stopping detection.
Further, in the step F, the setting condition is ITransfusion system≤0.8ITheory of thingsWherein, ITransfusion systemFor the current output by the communication chip under test, ITheory of thingsIs a theoretical current.
Further, in the step D, the setting algorithm is a coding algorithm.
Further, in the step E, the function data includes address information, date information, or temperature information.
Compared with the prior art, the invention has the beneficial effects that:
in the detection method, the read-write function of the communication chip to be detected is tested, and the functional state of the communication chip is detected by inputting a functional signal to the communication chip by using the signal generating unit, so that the performance of the communication chip can be detected more comprehensively.
In addition, the detection method also feeds back inconsistent functional data and expected data to the signal generation unit for storage and analysis, thereby being beneficial to analyzing the internal reason of the communication chip outputting error information.
Drawings
FIG. 1 is a flow chart of an embodiment of a method for testing a communication chip according to the present invention;
FIG. 2 is a flow chart of another embodiment of a method for testing a communication chip according to the present invention;
fig. 3 is a schematic block diagram of a signal generation unit of the present invention.
Detailed Description
So that the manner in which the features and advantages of the invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
As shown in fig. 1, the present application discloses a detection method of a communication chip, comprising,
step A: reading ID information in the communication chip to be tested, and respectively checking whether the contact between the communication chip to be tested and a power supply is normal or not and whether the communication between the communication chip and a signal generating unit is normal or not; if the two are normal, executing the next step; if not, connecting the line again;
in the step A, the ID information comprises rated voltage, rated current, time sequence and function description of the communication chip. In the step, whether the line contact is normal or not and whether the signal generating unit is normal or not are mainly judged, if the signal generating unit is abnormal, the signal generating unit is replaced, and the power supply can provide direct current of 1.5-5V.
And B: reading the output current of a power supply, comparing the output current with a theoretical current, and if the output current is greater than the theoretical current, indicating that a circuit is short-circuited, and adjusting the output current; if the output current is less than or equal to the theoretical current, indicating that the circuit current is normal, and executing the next step;
in the step B, the theoretical current ITheory of things=IForehead (forehead)n/4, wherein ITheory of thingsIs the theoretical current of the chip, IForehead (forehead)The rated current of the chip and n are the pin number of the chip. For example, the number of pins of the communication chip is 8, and the rated current IForehead (forehead)100mA, the theoretical current ITheory of things=100×8÷4＝200mA。
And C: executing read-write operation on the communication chip by using a signal generating unit to detect whether the read-write function of the communication chip is normal, entering the next step if the read-write function is normal, and stopping detection if the read-write function is normal;
in the step C, the signal generating unit may output test data to the communication chip to be tested, so that the communication chip to be tested writes the test data to determine the write operation of the communication chip; the communication chip to be tested can read the data in the signal generating unit to judge the data reading capability of the communication chip to be tested.
Preferably, as shown in fig. 3, the signal generating unit includes a transmission module, a power module, an FPGA control module, a program storage module, and a communication interface module in signal connection with the communication chip to be tested, the transmission module, the FPGA control module, and the program storage module are respectively electrically connected with the power module, and the transmission module, the program storage module, and the communication interface module are respectively in signal connection with the FPGA control module.
The transmission module is beneficial to receiving commands or programs of external equipment (such as an upper computer such as a PC), and comprises a communication board, wherein a Samtec high-speed connector can be adopted; the power supply module is used for respectively supplying power to the transmission module, the program storage module and the FPGA control module, and mainly adopts two modules of LTM4644 of ADI company and LMZ31710 of TI company. The FPGA control module can output data such as test data and functional signals and can also control each module, and the FPGA control module comprises a Kintex-7FPGA chip. The program storage module is a flash module for storing running programs of the FPGA control module, the flash module adopts a serial SPI interface to communicate with the FPGA, and the SPI communication protocol is simple and easy to operate. The communication interface module can convert the data or signals output by the FPGA control module into data or signals which can be identified by a communication chip to be tested, and comprises various signal transmission interfaces.
In a preferred embodiment, the signal generating unit further includes a network interface and an address selection module for selecting a communication chip, and the address selection module is in signal connection with the FPGA control module. The network interface is in signal connection with the transmission module.
The network interface is used for connecting a network so as to be convenient for communicating with external equipment. When there are multiple communication chips to be tested, the address selection module may select one or more communication chips for testing in a time period, and select another one or more communication chips for testing in a next time period.
Step D: judging whether an internal register of the communication chip fails or not according to the execution result of the tested communication chip according to a set algorithm, if the internal register fails, entering the next step, and if not, stopping detection;
in the step D, the set algorithm is a decoding algorithm, the decoding algorithm includes a hard decision decoding algorithm, a soft decision decoding algorithm and a hybrid decoding algorithm, the hard decision decoding algorithm demodulates the received real number sequence through the demodulator, then performs hard decision to obtain hard decision 0 and 1 sequences, and finally transmits the obtained hard decision sequence to the hard decision decoder for decision; the soft decision decoding algorithm can be regarded as infinite bit quantization decoding; the hybrid decoding algorithm combines the characteristics of soft decision decoding and hard decision decoding, is a decoding algorithm based on reliability, and utilizes partial channel information to calculate the reliability on the basis of the hard decision decoding. The communication algorithm can well detect the excellence of the register of the communication chip to be detected.
Step E: inputting a functional signal to the communication chip through the signal generating unit, judging whether functional data output by the communication chip is consistent with expected data or not, and indicating that the communication chip is a good chip when the functional data is consistent with the expected data; otherwise, the inconsistent functional data and the expected data are fed back to the signal generating unit for storage and analysis.
In the step E, the function data includes address information, date information, or temperature information. If the function data is date information, the function signal is an array in a format corresponding to the date information, and the expected data is expected date data. After the signal generation unit inputs an array (functional signal) of a date format to the chip to be tested, if the date information compiled by the chip to be tested according to the array is consistent with expected date data, the communication chip is indicated to have normal function and is a good chip; otherwise, the compiling function of the communication chip is abnormal.
In addition, the detection method also feeds back inconsistent functional data and expected data to the signal generation unit for storage and analysis, thereby being beneficial to analyzing the internal reason of the communication chip for outputting error information.
In another embodiment, as shown in fig. 2, the detection method further includes a step F: and when the functional data is consistent with the expected data, judging whether the output current meets a set condition, if so, indicating that the communication chip is a good chip, otherwise, stopping detection.
In the step F, the set condition is ITransfusion system≤0.8ITheory of thingsWherein, ITransfusion systemFor the current output by the communication chip under test, ITheory of thingsTo be a theoretical current, ITheory of thingsThe same as the theoretical current described above. Wherein, ITransfusion systemThe test can be carried out by a multimeter, and if the tested communication chip has a plurality of output power supplies, the average value is taken. It is to be understood that the set condition may be a temperature condition, a voltage condition, or a size condition, etc.
In summary, in the detection method of the present application, not only the read-write function of the communication chip to be tested is tested, but also the functional performance of the communication chip is detected by inputting a functional signal to the communication chip by the signal generation unit, so that the performance of the communication chip can be detected more comprehensively.
The foregoing illustrates and describes the principles, general features, and advantages of the present invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are given by way of illustration of the principles of the present invention, and that various changes and modifications may be made without departing from the spirit and scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (10)
1. A detection method of a communication chip is characterized by comprising the following steps,
step A: reading ID information in the communication chip to be tested, and respectively checking whether the contact between the communication chip to be tested and a power supply is normal or not and whether the communication between the communication chip and a signal generating unit is normal or not; if the two are normal, executing the next step; if not, connecting the line again;
and B: reading the output current of a power supply, comparing the output current with a theoretical current, and if the output current is greater than the theoretical current, indicating that a circuit is short-circuited, and adjusting the output current; if the output current is less than or equal to the theoretical current, indicating that the circuit current is normal, and executing the next step;
and C: executing read-write operation on the communication chip by using a signal generating unit to detect whether the read-write function of the communication chip is normal, if so, entering the next step, otherwise, stopping detection;
step D: judging whether an internal register of the communication chip fails or not according to the execution result of the tested communication chip according to a set algorithm, if the internal register fails, entering the next step, and if not, stopping detection;
step E: inputting a functional signal to the communication chip through the signal generating unit, judging whether functional data output by the communication chip is consistent with expected data or not, and indicating that the communication chip is a good chip when the functional data is consistent with the expected data; otherwise, the inconsistent functional data and the expected data are fed back to the signal generating unit for storage and analysis.
2. The method for detecting a communication chip according to claim 1, wherein in the step a, the ID information includes a rated voltage, a rated current, a timing and a functional description of the communication chip.
3. The method for detecting a communication chip according to claim 2, wherein in the step B, the theoretical current I isTheory of things=IForehead (forehead)n/4, wherein ITheory of thingsIs theoretical current of chip，IForehead (forehead)Is rated current of chipAnd n is the pin number of the chip.
4. The method for detecting a communication chip of claim 1, wherein in the step C, the signal generating unit includes a transmission module, a power module, an FPGA control module, a program storage module, and a communication interface module in signal connection with the communication chip to be detected, the transmission module, the FPGA control module, and the program storage module are respectively electrically connected with the power module, and the transmission module, the program storage module, and the communication interface module are respectively in signal connection with the FPGA control module.
5. The detection method of the communication chip as claimed in claim 4, wherein the signal generation unit further comprises an address selection module for selecting the communication chip, and the address selection module is in signal connection with the FPGA control module.
6. The detecting method of the communication chip as claimed in claim 5, wherein the signal generating unit further comprises a network interface, and the network interface is in signal connection with the transmission module.
7. The method for detecting a communication chip according to claim 6, further comprising the step of F: and when the functional data is consistent with the expected data, judging whether the output current meets a set condition, if so, indicating that the communication chip is a good chip, otherwise, stopping detection.
8. The method for detecting a communication chip according to claim 7, wherein in said step F, said setting condition is ITransfusion system≤0.8ITheory of thingsWherein, ITransfusion systemFor the current output by the communication chip under test, ITheory of thingsIs a theoretical current.
9. The method for detecting a communication chip of claim 1, wherein in the step D, the setting algorithm is a decoding algorithm.
10. The method for detecting a communication chip according to claim 1, wherein in the step E, the function data includes address information, date information, or temperature information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110456596.6A CN113098632B (en) | 2021-04-27 | 2021-04-27 | Detection method of communication chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110456596.6A CN113098632B (en) | 2021-04-27 | 2021-04-27 | Detection method of communication chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113098632A CN113098632A (en) | 2021-07-09 |
| CN113098632B true CN113098632B (en) | 2022-05-27 |
Family
ID=76680096
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110456596.6A Active CN113098632B (en) | 2021-04-27 | 2021-04-27 | Detection method of communication chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113098632B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2004201740A1 (en) * | 2000-02-15 | 2004-05-13 | Silverbrook Research Pty Ltd | Validation chip |
| JP2008286740A (en) * | 2007-05-21 | 2008-11-27 | Renesas Technology Corp | Semiconductor integrated circuit, and testing method therefor |
| CN106526454A (en) * | 2016-11-24 | 2017-03-22 | 上海精密计量测试研究所 | ATE-based method for testing FPGA configuration chip |
| CN110515031A (en) * | 2019-09-27 | 2019-11-29 | 广东电网有限责任公司 | A kind of electric energy meter detection equipment |
| CN112462248A (en) * | 2021-01-06 | 2021-03-09 | 浙江杭可仪器有限公司 | Test signal output system and use method thereof |
-
2021
- 2021-04-27 CN CN202110456596.6A patent/CN113098632B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2004201740A1 (en) * | 2000-02-15 | 2004-05-13 | Silverbrook Research Pty Ltd | Validation chip |
| JP2008286740A (en) * | 2007-05-21 | 2008-11-27 | Renesas Technology Corp | Semiconductor integrated circuit, and testing method therefor |
| CN106526454A (en) * | 2016-11-24 | 2017-03-22 | 上海精密计量测试研究所 | ATE-based method for testing FPGA configuration chip |
| CN110515031A (en) * | 2019-09-27 | 2019-11-29 | 广东电网有限责任公司 | A kind of electric energy meter detection equipment |
| CN112462248A (en) * | 2021-01-06 | 2021-03-09 | 浙江杭可仪器有限公司 | Test signal output system and use method thereof |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA和FT245的芯片功能测试装置的设计与实现;凌伟等;《科学技术与工程》;20121228(第36期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113098632A (en) | 2021-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110634530B (en) | Chip testing system and method | |
| US7797584B2 (en) | SATA interface tester and testing method | |
| KR20080007544A (en) | Test apparatus and test method | |
| US7015714B2 (en) | Testing device for printed circuit boards | |
| CN101996121B (en) | Universal serial bus (USB) port testing device and testing method | |
| US8356215B2 (en) | Testing apparatus and method for analyzing a memory module operating within an application system | |
| US20130111268A1 (en) | Testing device capable of simulating plugging and unplugging operations and method thereof | |
| CN113098632B (en) | Detection method of communication chip | |
| CN113270136B (en) | Control method and control system for testing Nand-flash bad block | |
| CN110570897B (en) | Memory detection system, memory detection method and error mapping table establishing method | |
| CN111459730A (en) | PCH (physical channel) end parameter adjusting method and system under Whitley platform | |
| US8103927B2 (en) | Field mounting-type test apparatus and method for testing memory component or module in actual PC environment | |
| KR101963811B1 (en) | Instruction-based Built Off Self-Test Circuit Apparatus | |
| CN114280456A (en) | Method, device and system for ELFR test of chip | |
| CN113009315A (en) | Interface conversion circuit, chip test system and method | |
| CN110781043B (en) | Quality detection method and device for storage product, storage medium and equipment | |
| CN113409873A (en) | Erasing and writing interference test system and method and execution device | |
| CN114187957A (en) | Memory test system and use method thereof | |
| US9104654B2 (en) | Method and device for efficient trace analysis | |
| CN115240749A (en) | Test method of RAM chip | |
| CN117558331B (en) | Method and device for detecting address stability of high-density test chip | |
| US20110156742A1 (en) | Chip Testing Circuit | |
| CN113407372B (en) | Method and system for detecting memory of computer system independent of operating system | |
| KR102229416B1 (en) | Method and Apparatus for Compressing Memory Test Data | |
| CN201107774Y (en) | SPI detection card |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |