CN116244701A - System and method for configuring digital-analog heterogeneous redundancy starting mode - Google Patents
System and method for configuring digital-analog heterogeneous redundancy starting mode Download PDFInfo
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Abstract
A digital-analog heterogeneous redundant start-up mode configuration system and method, the system includes a digital start-up mode capturer for capturing digital start-up mode configuration information from an input digital signal; the analog-digital converter is used for measuring an input analog signal, converting the analog signal into a digital signal and obtaining an analog signal sampling value; the analog starting mode acquirer is used for acquiring analog starting mode configuration information from the analog signal sampling value; the starting mode checking mode detector is used for determining a starting mode checking mode according to the analog signal sampling value; and the starting mode checker is used for checking the digital starting mode configuration information and the analog starting mode configuration information according to the starting mode checking mode. The system and the method for configuring the digital-analog heterogeneous redundant starting mode improve the functional safety and the fault diagnosis rate of the system starting mode configuration, and a user can adjust the starting mode according to the requirements or the safety level of the using scene function.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a highly reliable digital-analog heterogeneous redundancy starting mode configuration system and method for a multi-core heterogeneous system chip (SoC) and a Microcontroller (MCU).
Background
During system startup, the processor mostly needs to determine the startup mode according to startup mode configuration pins. Conventional start-up mode configurations fall into two main categories: 1) Configuring a start mode by adopting a group of digital input output pins (DIO); 2) The start-up mode is configured by adjusting the amplitude of the input voltage, current signals using one or more analog signal pins (AIOs).
To detect failure of the start-up mode selection circuit, the selection of the start-up mode is typically protected by means of parity or ECC checking. An additional input signal is needed to be added as verification information of the starting mode configuration by adopting a digital signal input mode; the analog signal input method needs to improve the accuracy of the analog signal to represent more verification information.
Common cause failure of the starting mode detection circuit can not be effectively avoided by adopting a pure digital starting mode or an analog starting mode, for example, by adopting an analog starting mode selection mode, if the analog-digital conversion circuit fails, the starting mode selection information and the starting mode verification information can be erroneously sampled, so that the fault diagnosis rate of the starting mode sampling circuit is reduced.
Disclosure of Invention
In order to solve the defects of the prior art, the invention aims to provide a digital-analog heterogeneous redundancy starting mode configuration system and a method, which simultaneously support digital signal and analog starting mode configuration, and can adjust the starting mode according to the requirements of safety level of using scene functions on the basis of ensuring the safety of the system starting mode configuration function.
In order to achieve the above object, the present invention provides a digital-analog heterogeneous redundancy start-up mode configuration system, comprising,
a digital start mode capturer for capturing digital start mode configuration information from an input digital signal;
the analog-digital converter is used for measuring an input analog signal, converting the analog signal into a digital signal and obtaining an analog signal sampling value;
the analog starting mode acquirer is used for acquiring analog starting mode configuration information from the analog signal sampling value;
the starting mode checking mode detector is used for determining a starting mode checking mode according to the analog signal sampling value;
and the starting mode checker is used for checking the digital starting mode configuration information and the analog starting mode configuration information according to the starting mode checking mode.
Further, the method further comprises the following steps: and the input selection module is used for setting an input starting mode.
Further, the digital start mode capturer captures and latches the digital start mode configuration information after the initial power-up of the processor is completed.
Further, the analog-to-digital converter is one or more.
Further, the analog start mode capturer is used for starting the analog-digital converter to measure the input analog signal; and converting the analog signal sampling value output by the analog-digital converter into analog starting configuration information.
Further, the analog start mode capturer intercepts a set bit number from high bits of an analog signal sampling value output by the analog-to-digital converter as analog start configuration information.
Further, the start mode checking mode detector selects the high bit of the analog signal sampling value output by the analog-digital converter as the selection bit according to the set bit, and the remaining bit of the analog signal sampling value is used as the start mode selection information.
Further, the starting mode checking mode comprises the steps of not checking the starting mode, performing parity check on the starting mode, performing 1bit error check on the starting mode and starting a 1bit error correction function, and performing 2bit error check on the starting mode and starting the 1bit error correction function.
Further, the starting mode checker selects one of the digital starting mode configuration information or the analog starting mode configuration information as the checking data of the starting mode according to the starting mode checking mode, and checks the other starting mode configuration information.
In order to achieve the above object, the present invention further provides a method for configuring a digital-to-analog redundancy start mode, which adopts the system for configuring a digital-to-analog redundancy start mode as described above, comprising:
selecting a starting mode;
capturing and locking digital start mode configuration information;
measuring an input analog signal, and capturing configuration information of an analog starting mode from an analog signal sampling value;
determining a starting mode verification mode according to the analog signal sampling value;
and according to the starting mode verification mode, verifying the digital starting mode configuration information and the analog starting mode configuration information.
Further, the step of capturing the configuration information of the analog starting mode from the sampling value of the analog signal further comprises:
and intercepting a set bit number from high bits of an analog signal sampling value output by the analog-digital converter as analog starting configuration information.
Further, the step of determining the verification mode of the starting mode according to the analog signal sampling value further includes:
and selecting high bits of the analog signal sampling value output by the analog-digital converter as selection bits according to the set bits, and using the remaining bits as starting mode selection information.
Further, the starting mode checking mode comprises the steps of not checking the starting mode, performing parity check on the starting mode, performing 1bit error check on the starting mode and starting a 1bit error correction function, and performing 2bit error check on the starting mode and starting the 1bit error correction function.
Further, the step of verifying the digital start mode configuration information and the analog start mode configuration information according to the start mode verification manner further includes: and selecting one of the digital starting mode configuration information or the analog starting mode configuration information as the starting mode verification data to verify the other starting mode configuration information according to the starting mode verification mode.
In order to achieve the above purpose, the present invention further provides a chip, which includes the above digital-analog heterogeneous redundancy start-up mode configuration system.
To achieve the above object, the present invention also provides an electronic device, including a memory and a processor, where the memory stores computer instructions, the processor employs a chip as described above, and when the processor is configured to execute the instructions to perform the steps of the digital-to-analog heterogeneous redundancy start-up mode configuration method as described above.
To achieve the above object, the present invention also provides a computer-readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the digital-to-analog redundancy start-up mode configuration method as described above.
Compared with the prior art, the system and the method for configuring the digital-analog heterogeneous redundancy starting mode have the following technical effects:
meanwhile, the configuration of the digital signal and the analog starting mode is supported, the configuration information of the digital starting mode and the configuration information of the analog starting mode are checked, and the functional safety of the configuration of the system starting mode is improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate the invention and together with the embodiments of the invention, and do not limit the invention. In the drawings:
FIG. 1 is a schematic diagram illustrating an embodiment of a digital-to-analog redundancy start-up mode configuration system according to the present invention;
FIG. 2 is a schematic diagram of a configuration of a further embodiment of a digital-to-analog redundancy start-up mode configuration system according to the present invention;
FIG. 3 is a flow chart of a method for configuring a digital-to-analog redundancy start-up mode according to the present invention;
fig. 4 is a schematic structural view of an electronic device according to the present invention.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present application are shown in the drawings, it is to be understood that the present application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the present application. It should be understood that the drawings and examples of the present application are for illustrative purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present application is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "based on" is based at least in part on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below.
It should be noted that references to "one" or "a plurality" in this application are intended to be illustrative rather than limiting, and those of ordinary skill in the art will appreciate that "one or more" is intended to be interpreted as "one or more" unless the context clearly indicates otherwise. "plurality" is understood to mean two or more.
In the embodiment of the invention, the following steps are included: heterogeneous redundancy. The redundant system is composed of two devices with different performances, models, functions, principles and the like, wherein one device is in an operation state and the other device is in a standby state. In general, the redundant system has better performance of devices in normal running state and complete functions, while the devices which are usually used as spare devices have only partial functions, such as sequential control functions, etc., so the redundant structure is also called incomplete redundancy.
Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings.
Example 1
Fig. 1 is a schematic structural diagram of an embodiment of a digital-to-analog redundancy start-up mode configuration system according to the present invention, as shown in fig. 1, the digital-to-analog redundancy start-up mode configuration system of the present embodiment includes,
digital boot mode capturer 10 captures and latches digital boot mode configuration information from digital input pins (dio_0 through dio_n) at a particular time of processor boot (typically after initial power up of the processor) for use by boot mode verifier 50.
An analog-to-digital converter (ADC) 20 receives an instruction from the analog start-up mode capturer 30, measures an analog signal inputted from an analog input pin (aio_0), and transmits an analog signal sampling value to the analog start-up mode capturer 30 and the start-up mode verification mode detector 40.
The analog start mode capturer 30 starts the analog-digital converter 20 to measure the analog signal input by the io_0 in the processor start stage, and converts the analog signal sampling value output by the analog-digital converter 20 into corresponding analog start mode configuration information for use by the start mode checker 50.
The start-up pattern verification mode detector 40 is configured to analyze the analog signal sampling value output by the analog-to-digital converter 20, select a corresponding start-up pattern verification mode according to the analysis result, and send the selected start-up pattern verification mode to the start-up pattern verifier 50.
In the embodiment of the present invention, the start mode checking mode detector 40 uses the high bit information of the analog signal sampling value as the selection bit and uses the rest bits as the start mode selection information.
The start-up mode checker 50 checks the digital start-up mode configuration information of the digital start-up mode capturer 10 and the analog start-up mode configuration information of the analog start-up mode capturer 30 according to the check mode output from the start-up mode check mode detector 40, and then outputs a final start-up mode or check error information.
In the embodiment of the present invention, the start mode checker 50 selects analog or digital start mode information as start mode information according to the start mode checking mode detected by the start mode checking mode detector 40, and performs checking calculation by using the other start mode information as check data of the start mode, and outputs the final start mode after checking, and if an error is detected, reports a checking error. In the embodiment of the present invention, the start mode checker 50 selects one of the digital start mode configuration information and the analog start mode configuration information as the check data of the start mode according to the start mode check mode sent by the start mode check mode detector 40, and checks the other start mode configuration information, so that the digital start mode configuration information and the analog start mode configuration information can be checked with each other, thereby improving the functional security of the system start mode configuration.
An input selection module 60 for setting the input start mode.
In the embodiment of the present invention, the input selection module 60 may select the analog start mode input, the digital start mode input, or the simultaneous input of the analog start mode input and the digital start mode according to the requirement of the user or the requirement of the security level of the application scene function.
In the embodiment of the present invention, the input selection module 60 outputs an analog signal to the analog-to-digital converter (ADC) 20 and simultaneously sends a digital signal to the digital start-up mode capturer 10 when the start-up mode is to be verified.
Example 2
Fig. 2 is a schematic structural diagram of still another embodiment of a digital-to-analog redundancy start-up mode configuration system according to the present invention, as shown in fig. 2, the digital-to-analog redundancy start-up mode configuration system of the present embodiment includes:
digital start mode capturer:
after the initial power-up of the processor is completed, the configuration of the digital start mode is captured from the digital input pins (DIO_0 to DIO_N), and the captured digital start mode configuration information (DBM [ N:0 ]) of n+1bit is latched for the processor.
Analog-to-digital converter ADC:
the analog signal input by the analog input pin (aio_0) is measured, and the analog signal is converted into a digital signal and output.
In the embodiment of the invention, if the requirement of the starting mode selection pins is higher than the precision of the ADC, the starting mode selection pins are required to be grouped, and a plurality of ADCs are used for measuring a plurality of analog digital pins.
Analog start mode capturer:
the ADC is started to measure the analog signal input by AIO_0 in the starting stage of the processor to obtain an analog signal sampling value ASV [ P:0] of (P+1) bit;
the measurement result (analog signal sampling value ASV [ P:0 ]) is converted into M+1 bit analog start mode configuration information (ABM [ M:0 ]), and the configuration information is sent to a start mode checker.
In the embodiment of the invention, the adopted conversion method is as follows: and intercepting the high P-M bit of the ASV as the configuration information of the analog starting mode, thereby avoiding the influence of ADC sampling errors on the starting mode selection.
A start mode verification mode detector:
selecting and determining a verification mode through analysis of an ADC analog signal sampling result;
in the embodiment of the invention, the high-order information of the ASV is used as the selection bit, and the rest bits are used as the starting mode selection information. For example, ASV is a 6bit data, and the verification method is determined as follows:
the upper two bits (bit 5, bit 4) of the ASV are used as selection bits and the check mode is encoded, and the check code is as follows:
b00, not checking the starting mode;
b01, parity check is carried out on the starting mode (1 bit check bit is needed);
b10, performing 1bit error check on the starting mode and starting a 1bit error correction function (7-4 Hamming codes are adopted, and 3bit check bits are needed);
b11, performing two-bit error check on the starting mode and starting a 1-bit error correction function (adopting 8-4 Hamming codes and requiring 4-bit check bits).
A start mode checker:
the start mode checker selects corresponding data from the analog start mode configuration information (ABM [ M:0 ]) and the digital start mode configuration information (DBM [ N:0 ]) according to the check mode detected by the start mode check mode detector for checking. After the verification is completed, the final start mode (SBM [ X:0 ]) is output for the system. Reporting the system controller if an Error (ERR) is detected. For example, ASV is 6bit data, the upper two bits of ASV are encoded as check mode, and the lower four bits ABM [3:0] are configuration information of analog starting mode. DBM [3:0] configures verification information for 4bit digital start mode. And according to different verification modes, the starting mode verifier selects different DBM data to verify the ABM. The different verification code starting mode verification modes sent by the starting mode verification mode detector are as follows:
b00: if the start mode is not verified, SBM [3:0] =ABM [3:0] and the verification error flag ERR is forced to 0
b01, parity checking the starting mode, wherein SBM [3:0] = ABM [3:0], and simultaneously calculating a parity check value P of the ABM, and ERR=0 if P=DBM [ 0]; err=1 if P is not equal to DBM [0 ]. Only one digital initiation mode IO is needed to check in this mode, and the IO resources of the system are saved. But the functional security level of this mode is relatively low due to the relatively low diagnostic coverage of the parity check
b10, performing 1bit error check on the starting mode, starting a 1bit error correction function (adopting 7-4 Hamming codes and requiring 3bit check bits), and performing check and error correction on the ABM [3:0] by using the DBM [2:0] = ABM [3:0 ]. Since 7-4 hamming codes can only find 1bit errors and repair ERR is forced to 0, the pattern cannot be found if more than 1bit errors occur. In this mode, a 3bit digital start-up mode IO is required for verification, requiring the use of more digital IO resources. Since the diagnostic coverage of the 7-4 hamming code check is relatively high, the functional security level of this mode is relatively high
b11, performing two-bit error check on the starting mode, starting a 1-bit error correction function (adopting 8-4 Hamming codes and needing 4-bit check bits), and performing check and error correction on the ABM [3:0] by using the DBM [3:0] = ABM [3:0 ]. Err=0 if there is no error or a 1bit error occurs; err=1 if a 2bit error is detected. In this mode, a 4bit digital start-up mode IO is required for verification, requiring the use of more digital IO resources. The diagnostic coverage of the 8-4 hamming code check is further improved compared to the 7-4 hamming code, which mode has a relatively higher level of functional security.
In the embodiment of the invention, the starting mode checker adopts the starting mode checking mode to check the simulation starting mode configuration information and the digital starting mode configuration information, so that the digital-analog heterogeneous redundancy starting mode configuration system has the self-adaptive adjusting function safety level function and the system IO resource occupation state adjustable function.
An input selection module:
the analog start-up mode input, the digital start-up mode input, or both the analog start-up mode input and the digital start-up mode input are implemented by a plurality of analog switches (AS 0, AS1 … ASM), digital switches (DS 0, DS1 … DSM), and digital-to-analog converters.
In the embodiment of the invention, the input selection module outputs an analog signal to an analog-to-digital converter (ADC) when the start mode needs to be checked, and simultaneously sends a digital signal to the digital start mode capturer.
Example 3
Fig. 3 is a flowchart of a method for configuring a digital-to-analog redundancy start-up mode according to the present invention, and the method for configuring a digital-to-analog redundancy start-up mode according to the present invention will be described in detail with reference to fig. 3.
First, in step 301, an analog startup mode or a digital startup mode is selected according to a user's requirement or a requirement of a security level of an application scenario function.
In the embodiment of the present invention, the input selection module 60 implements selection of the analog start mode and the digital start mode through a plurality of analog switches (AS 0, AS1 … ASM), digital switches (DS 0, DS1 … DSM), and digital-to-analog converters.
In step 302, digital start-up mode configuration information is captured and locked.
In an embodiment of the present invention, the digital start-up mode capturer 10 captures and locks the digital start-up mode configuration information from the digital input pins (io_0 to io_n) and sends it to the start-up mode checker 50.
After the initial power-up of the processor is completed, the configuration of the digital start mode is captured from the digital input pins (dio_0 to dio_n), and the captured digital start mode configuration information (DBM [ N:0 ]) of n+1bit is latched at the same time, and the digital start mode configuration information (DBM [ N:0 ]) is transmitted to the start mode checker 50.
In step 303, the input analog signal is measured and analog start-up mode configuration information is captured from the analog signal sample values.
In the embodiment of the present invention, the analog start mode capturer 30 starts the analog-to-digital converter 20 to measure the analog signal input by AIO_0 in the processor start stage, so as to obtain the analog signal sampling value ASV [ P:0] of the (P+1) bit;
the measurement result (analog signal sampling value ASV [ P:0 ]) is converted into M+1 bit analog start mode configuration information (ABM [ M:0 ]), and the configuration information is sent to a start mode checker.
In the embodiment of the present invention, the analog start mode capturer 30 intercepts the high P-Mbit of the ASV as the configuration information of the analog start mode, so as to avoid the influence of the ADC sampling error on the start mode selection.
In step 304, a verification mode of the start mode is determined according to the analog signal sampling value.
In the embodiment of the present invention, the start mode verification mode detector 40 selects and determines a verification mode by analyzing the sampling result of the ADC analog signal;
in the embodiment of the present invention, the start mode checking mode detector 40 uses the high-order information of the ASV as the selection bits, and the remaining bits as the start mode selection information. For example, ASV is a 6bit data, and the verification method is determined as follows:
the upper two bits (bit 5, bit 4) of the ASV are used as selection bits and the check mode is encoded:
b00, not checking the starting mode;
b01, parity check is carried out on the starting mode (1 bit check bit is needed);
b10, performing 1bit error check on the starting mode and starting a 1bit error correction function (7-4 Hamming codes are adopted, and 3bit check bits are needed);
b11, 2bit error check is carried out on the starting mode, and a 1bit error correction function is started (4 bit check bits are needed by adopting 8-4 Hamming codes).
In step 305, the digital start-up mode configuration information and the analog start-up mode configuration information are checked.
In the embodiment of the present invention, the start-up mode checker 50 selects corresponding data from the analog start-up mode configuration information (ABM: 0) and the digital start-up mode configuration information (DBM: 0) according to the check mode detected by the start-up mode check mode detector 40 for checking. After the verification is completed, the final start mode (SBM [ X:0 ]) is output for the system. Reporting the system controller if an Error (ERR) is detected.
For example, ASV is 6bit data, the upper two bits of ASV are encoded as check mode, and the lower four bits ABM [3:0] are configuration information of analog starting mode. DBM [3:0] configures verification information for 4bit digital start mode. And according to different verification modes, the starting mode verifier selects different DBM data to verify the ABM. The different verification code starting mode verification modes sent by the starting mode verification mode detector are as follows: :
b00: if the start mode is not verified, SBM [3:0] =ABM [3:0] and the verification error flag ERR is forced to 0
b01, parity checking the starting mode, wherein SBM [3:0] = ABM [3:0], and simultaneously calculating a parity check value P of the ABM, and ERR=0 if P=DBM [ 0]; err=1 if P is not equal to DBM [0 ]. Only one digital initiation mode IO is needed to check in this mode, and the IO resources of the system are saved. But the functional security level of this mode is relatively low due to the relatively low diagnostic coverage of the parity check
b10, performing 1bit error check on the starting mode, starting a 1bit error correction function (adopting 7-4 Hamming codes and requiring 3bit check bits), and performing check and error correction on the ABM [3:0] by using the DBM [2:0] = ABM [3:0 ]. Since 7-4 hamming codes can only find 1bit errors and repair ERR is forced to 0, the pattern cannot be found if more than 1bit errors occur. In this mode, a 3bit digital start-up mode IO is required for verification, requiring the use of more digital IO resources. Since the diagnostic coverage of the 7-4 hamming code check is relatively high, the functional security level of this mode is relatively high
b11, performing two-bit error check on the starting mode, starting a 1-bit error correction function (adopting 8-4 Hamming codes and needing 4-bit check bits), and performing check and error correction on the ABM [3:0] by using the DBM [3:0] = ABM [3:0 ]. Err=0 if there is no error or a 1bit error occurs; err=1 if a 2bit error is detected. In this mode, a 4bit digital start-up mode IO is required for verification, requiring the use of more digital IO resources. The diagnostic coverage of the 8-4 hamming code check is further improved compared to the 7-4 hamming code, which mode has a relatively higher level of functional security.
In the embodiment of the invention, the starting mode verification mode is adopted to verify the analog starting mode configuration information and the digital starting mode configuration information, so that the digital-analog heterogeneous redundancy starting mode configuration system has the self-adaptive adjusting function safety level function and the system IO resource occupation state adjustable function.
Example 4
The invention also provides a chip, which comprises the digital-analog heterogeneous redundancy starting mode configuration system, so that common-cause failure of a starting mode detection circuit can be avoided, and the fault diagnosis rate of a starting mode sampling circuit can be improved.
Example 5
In the embodiment of the present application, there is further provided an electronic device, fig. 4 is a schematic structural diagram of the electronic device according to the embodiment of the present application, and as shown in fig. 4, the electronic device of the present application includes a processor 401, and a memory 402, where,
the processor 401 employs the chip of the embodiment described above.
The memory 402 stores a computer program which, when read by the processor 401 for execution, performs the steps in the embodiment of the digital-to-analog redundancy start-up mode configuration method described above.
Example 6
In an embodiment of the present application, there is also provided a computer readable storage medium having a computer program stored therein, wherein the computer program is configured to perform the steps in the embodiment of the digital-to-analog redundancy start-up mode configuration method as described above when run.
In embodiments of the present application, the computer-readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (RandomAccess Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
Those of ordinary skill in the art will appreciate that: the foregoing description is only a preferred embodiment of the present invention, and the present invention is not limited thereto, but it is to be understood that modifications and equivalents of some of the technical features described in the foregoing embodiments may be made by those skilled in the art, although the present invention has been described in detail with reference to the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (17)
1. A digital to analog redundancy start-up mode configuration system, comprising:
a digital start mode capturer for capturing digital start mode configuration information from an input digital signal;
the analog-digital converter is used for measuring an input analog signal, converting the analog signal into a digital signal and obtaining an analog signal sampling value;
the analog starting mode acquirer is used for acquiring analog starting mode configuration information from the analog signal sampling value;
the starting mode checking mode detector is used for determining a starting mode checking mode according to the analog signal sampling value;
and the starting mode checker is used for checking the digital starting mode configuration information and the analog starting mode configuration information according to the starting mode checking mode.
2. The digital to analog redundancy start-up mode configuration system of claim 1, further comprising: and the input selection module is used for setting an input starting mode.
3. The digital to analog redundancy enable mode configuration system of claim 1, wherein said digital enable mode capturer captures and latches digital enable mode configuration information after initial power up of the processor is completed.
4. The digital to analog redundancy start-up mode configuration system of claim 1, wherein the analog to digital converter is one or more.
5. The digital to analog heterogeneous redundant start-up mode configuration system of claim 1, wherein the analog start-up mode capturer is configured to start up an analog signal input by the analog to digital converter measurement; and converting the analog signal sampling value output by the analog-digital converter into analog starting configuration information.
6. The system according to claim 1, wherein the analog start-up mode capturer intercepts a set number of bits from high-order bits of an analog signal sampling value output from the analog-to-digital converter as the analog start-up configuration information.
7. The system according to claim 1, wherein the start-up mode checking mode detector selects high-order bits of the analog signal sampling value outputted from the analog-to-digital converter as selection bits according to a set number of bits, and the remaining-order bits are used as start-up mode selection information.
8. The system according to claim 1, wherein the mode of checking the start mode includes not checking the start mode, parity checking the start mode, 1bit error checking the start mode and starting a 1bit error correction function, and 2bit error checking the start mode and starting a 1bit error correction function.
9. The system according to claim 1, wherein the startup mode checker selects one of the digital startup mode configuration information or the analog startup mode configuration information as the startup mode check data according to the startup mode check mode, and checks the other startup mode configuration information.
10. A digital-to-analog redundancy start-up mode configuration method, employing the digital-to-analog redundancy start-up mode configuration system of any one of claims 1-9, comprising:
selecting a starting mode;
capturing and locking digital start mode configuration information;
measuring an input analog signal, and capturing configuration information of an analog starting mode from an analog signal sampling value;
determining a starting mode verification mode according to the analog signal sampling value;
and according to the starting mode verification mode, verifying the digital starting mode configuration information and the analog starting mode configuration information.
11. The method of claim 10, wherein the step of capturing analog start-up mode configuration information from analog signal sample values further comprises:
and intercepting a set bit number from high bits of an analog signal sampling value output by the analog-digital converter as analog starting configuration information.
12. The method for configuring a digital-to-analog redundancy start-up mode according to claim 10, wherein the step of determining a start-up mode verification method according to the analog signal sampling value further comprises:
and selecting high bits of the analog signal sampling value output by the analog-digital converter as selection bits according to the set bits, and using the remaining bits as starting mode selection information.
13. The method for configuring a digital-to-analog redundancy start-up mode according to claim 12, wherein the start-up mode checking mode includes checking no start-up mode, checking parity of start-up mode, checking 1bit error of start-up mode and starting 1bit error correction function, and checking 2bit error of start-up mode and starting 1bit error correction function.
14. The method for configuring a digital to analog redundancy start-up mode according to claim 10, wherein said step of verifying said digital start-up mode configuration information and said analog start-up mode configuration information according to said start-up mode verification means further comprises: and selecting one of the digital starting mode configuration information or the analog starting mode configuration information as the starting mode verification data to verify the other starting mode configuration information according to the starting mode verification mode.
15. A chip comprising the digital-to-analog redundancy start-up mode configuration system of any one of claims 1-9.
16. An electronic device comprising, a memory having stored therein computer instructions and a processor employing the chip of claim 15, when the processor is arranged to execute the instructions to perform the steps of the digital-to-analog redundancy initiation mode configuration method of any one of claims 10-14.
17. A computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the digital to analog redundancy start-up mode configuration method of any of claims 10 to 14.
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