CN117544164A - Method, equipment and medium for correcting closed loop stability based on open loop control - Google Patents
Method, equipment and medium for correcting closed loop stability based on open loop control Download PDFInfo
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Abstract
The application relates to the technical field of computers and provides a closed-loop stability correction method, device and medium based on open-loop control. The method comprises the following steps: correcting a first loop bandwidth of the first loop system in an open loop state; determining a first ratio of the zero frequency to the first loop bandwidth and a second ratio of the pole frequency to the first loop bandwidth based on the phase margin; the capacitance value of the zero capacitance is corrected based on the first ratio and the reference capacitance value, and the capacitance value of the pole capacitance is corrected based on the second ratio and the reference capacitance value. Therefore, the loop system is operated in an open loop state and the closed loop stability is corrected, so that the correction time is shortened and the control flow is simplified.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method, an apparatus, and a medium for correcting closed loop stability based on open loop control.
Background
In the prior art, a loop system such as a phase-locked loop system is operated in a closed loop condition to correct a stability parameter of the phase-locked loop system, but this necessarily involves a closed loop frequency characteristic and a closed loop control of the loop system, thus resulting in a long correction time and a complicated control flow.
Therefore, the application provides a correction method, device and medium for closed loop stability based on open loop control, which can realize correction of closed loop stability under the open loop condition and solve the technical problems in the prior art by utilizing the open loop frequency characteristic and the open loop control of a loop system.
Disclosure of Invention
In a first aspect, the present application provides a method of correcting closed loop stability based on open loop control. The correction method comprises the following steps: correcting a first loop bandwidth of a first loop system in an open loop state, wherein a main loop of the first loop system includes a phase detector for generating a first charge pump current based on a first input signal frequency when the first loop system is in the open loop state, a charge pump for generating a first control voltage signal based on the first charge pump current when the first loop system is in the open loop state, and a generator for generating a first clock signal based on the first control voltage signal when the first loop system is in the open loop state, the first clock signal not being fed back to the phase detector when the first loop system is in the open loop state; determining a first ratio of zero frequency to the first loop bandwidth and a second ratio of pole frequency to the first loop bandwidth based on a phase margin; correcting the capacitance value of a zero capacitance based on the first ratio and a reference capacitance value, and correcting the capacitance value of a pole capacitance based on the second ratio and the reference capacitance value, wherein the zero capacitance and the pole capacitance are connected between the charge pump and the generator in parallel, a switched capacitor circuit or a reference resistor is connected between the zero capacitance and the main loop in series, the switched capacitor circuit is equivalent to the reference resistor according to the first input signal frequency, and the reference capacitance value is the capacitance value of the switched capacitor circuit.
According to the first aspect of the application, the loop system is operated in the open loop state and the closed loop stability is corrected, so that the open loop frequency characteristic and open loop control of the loop system can be utilized, and the correction time is shortened and the control flow is simplified.
In a possible implementation manner of the first aspect of the present application, the phase detector is further configured to generate a second charge pump current based on a second input signal frequency and a second clock signal frequency when the first loop system is in a closed loop state, the charge pump is configured to generate a second control voltage signal based on the second charge pump current when the first loop system is in the closed loop state, and the generator is configured to generate the third clock signal based on the second control voltage signal when the first loop system is in the closed loop state, the second clock signal being identical to the third clock signal or obtained by dividing the third clock signal by frequency.
In a possible implementation manner of the first aspect of the present application, the first input signal frequency is the same as or different from the second input signal frequency.
In a possible implementation manner of the first aspect of the present application, the switched capacitor circuit is serially connected between the zero capacitor and the main loop, the switched capacitor circuit includes a first switch, a second switch and a first capacitor, a capacitance value of the first capacitor is the reference capacitance value, the first switch and the second switch are serially connected between the zero capacitor and the main loop, one end of the first capacitor is grounded, and the other end of the first capacitor is connected between the first switch and the second switch.
In a possible implementation manner of the first aspect of the present application, the frequency of the first switch control signal for controlling the first switch and the frequency of the second switch control signal for controlling the second switch are both the first input signal frequency, and the first switch control signal is opposite in phase to the second switch control signal.
In a possible implementation manner of the first aspect of the present application, the reference resistor is connected in series between the zero capacitor and the main loop, and the reference resistor is a physical resistor.
In a possible implementation manner of the first aspect of the present application, when the priority of the first loop bandwidth is higher than the priority of the phase margin, the reference resistor is connected in series between the zero capacitance and the main loop and the reference resistor is a physical resistor; the switched capacitor circuit is serially connected between the zero capacitor and the main loop when the priority of the first loop bandwidth is lower than the priority of the phase margin.
In a possible implementation form of the first aspect of the present application, the generator is a voltage controlled oscillator.
In a possible implementation manner of the first aspect of the present application, the first loop bandwidth is corrected based on a gain of the voltage controlled oscillator and a current value of the first charge pump current.
In a possible implementation manner of the first aspect of the present application, the correcting the first loop bandwidth is insensitive to a capacitance value of the zero capacitance and a capacitance value of the pole capacitance.
In a possible implementation manner of the first aspect of the present application, the reference capacitance value is a capacitance value of the switched-capacitor circuit, which is determined by a successive comparison logic algorithm or a closed-loop test algorithm and is equivalent to the reference resistance according to the first input signal frequency.
In a possible implementation manner of the first aspect of the present application, the reference resistor is connected in series between the zero capacitor and the main loop, and the first input signal frequency is an ultra-high frequency with respect to the first loop bandwidth.
In a possible implementation manner of the first aspect of the present application, the first loop system is a phase locked loop.
In a second aspect, embodiments of the present application further provide a computer device, where the computer device includes a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements a method according to any implementation manner of any one of the foregoing aspects when the computer program is executed.
In a third aspect, embodiments of the present application also provide a computer-readable storage medium storing computer instructions that, when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
In a fourth aspect, embodiments of the present application also provide a computer program product comprising instructions stored on a computer-readable storage medium, which when run on a computer device, cause the computer device to perform a method according to any one of the implementations of any one of the above aspects.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a closed-loop stability correction method based on open-loop control according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a first loop system in an open loop state according to a first embodiment provided in the examples of the present application;
FIG. 3 is a schematic diagram of a first loop system in an open loop state according to a second embodiment provided by the examples of this application;
FIG. 4 is a schematic diagram of a switched capacitor circuit equivalent to a reference resistor according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a computing device according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
It should be understood that in the description of this application, "at least one" means one or more than one, and "a plurality" means two or more than two. In addition, the words "first," "second," and the like, unless otherwise indicated, are used solely for the purposes of description and are not to be construed as indicating or implying a relative importance or order.
Fig. 1 is a flow chart of a method for correcting closed loop stability based on open loop control according to an embodiment of the present application. As shown in fig. 1, the correction method includes the following steps.
Step S110: correcting a first loop bandwidth of a first loop system in an open loop state, wherein a main loop of the first loop system includes a phase detector for generating a first charge pump current based on a first input signal frequency when the first loop system is in the open loop state, a charge pump for generating a first control voltage signal based on the first charge pump current when the first loop system is in the open loop state, and a generator for generating a first clock signal based on the first control voltage signal when the first loop system is in the open loop state, the first clock signal not being fed back to the phase detector when the first loop system is in the open loop state.
Step S120: a first ratio of the zero frequency relative to the first loop bandwidth and a second ratio of the pole frequency relative to the first loop bandwidth are determined based on the phase margin.
Step S130: correcting the capacitance value of a zero capacitance based on the first ratio and a reference capacitance value, and correcting the capacitance value of a pole capacitance based on the second ratio and the reference capacitance value, wherein the zero capacitance and the pole capacitance are connected between the charge pump and the generator in parallel, a switched capacitor circuit or a reference resistor is connected between the zero capacitance and the main loop in series, the switched capacitor circuit is equivalent to the reference resistor according to the first input signal frequency, and the reference capacitance value is the capacitance value of the switched capacitor circuit.
In the field of high-speed data communication, a phase-locked loop system is generally applied to realize a frequency-locking and phase-locking function and recover a data signal and a clock signal from a high-speed serial signal. Phase-locked loop systems and similar loop systems include both open loop and closed loop modes of operation. In the open loop state, the loop system is based on open loop control and has corresponding open loop frequency characteristics, wherein the open loop control refers to a control process with only forward action and no reverse connection between the control device and the controlled object, namely the open loop control system. In the closed-loop state, the loop system is based on closed-loop control and has corresponding closed-loop frequency characteristics, wherein the closed-loop control refers to a control process of directly or indirectly feeding back an output quantity to an input end to form a closed loop, namely, a control device and a controlled object have forward action and reverse connection, namely, the closed-loop control system. Loop systems such as phase locked loops are in practice operated in a closed loop state to provide functions such as frequency tracking, phase locking, etc. The actual performance of the loop system may vary from the intended performance, subject to various factors such as process conditions, device aging, etc. For example, the capacitance value of the critical capacitor in the loop system and the system bandwidth of the loop system may deviate from the expected value due to the influence of the process angle condition, the working temperature, the working voltage and the like in the preparation process, so that the system stability is affected. In order to ensure the normal operation of the system and minimize errors such as bit errors and bit errors, it is necessary to correct the closed-loop stability of the loop system, for example, by correcting one or more loop parameters or parameters of critical components of the loop system so that the closed-loop stability of the entire loop system meets the design objective. However, if a loop system such as a phase locked loop system is operated in a closed loop state to correct a stability parameter of the phase locked loop system, this necessarily involves a closed loop frequency characteristic and a closed loop control of the loop system, thus resulting in a long correction time and a complicated control flow. Therefore, the correction method of closed loop stability based on open loop control shown in fig. 1 realizes the operation of the loop system in the open loop state and the correction of closed loop stability, so that the open loop frequency characteristic and the open loop control of the loop system can be utilized, which is beneficial to shortening the correction time and simplifying the control flow, and is described in detail below.
Referring to fig. 1, in step S110, a first loop bandwidth of a first loop system in an open loop state is corrected. Here, the main loop of the first loop system includes a phase detector for generating a first charge pump current based on a first input signal frequency when the first loop system is in the open loop state, a charge pump for generating a first control voltage signal based on the first charge pump current when the first loop system is in the open loop state, and a generator for generating a first clock signal based on the first control voltage signal when the first loop system is in the open loop state. In addition, the first clock signal is not fed back to the phase detector when the first loop system is in the open loop state. In this way, the first clock signal is not fed back to the phase detector in the open loop state of the first loop system, so that the open loop frequency characteristic and the open loop control flow of the first loop system in the open loop state can be utilized. In the process of correcting the first loop bandwidth of the first loop system in the open loop state, because only the open loop frequency characteristic and the open loop control flow are involved, the calculation of the first loop bandwidth only needs the gain of the generator and the current value of the first charge pump current, and is insensitive to the zero capacitance and the pole capacitance of the first loop system. In other words, by correcting the first loop bandwidth of the first loop system in the open loop state, the open loop frequency characteristic and the open loop control flow of the first loop system can be utilized, so that the influence of the change of the loop parameters such as the capacitance values of the zero capacitor and the pole capacitor on the calculation of the first loop bandwidth is reduced as much as possible, and the capacitance values of the loop parameters such as the zero capacitor and the pole capacitor may deviate from the expected values due to the influence of the process corner condition, the operating temperature, the operating voltage, etc. in the preparation process, which means that the correction of the first loop bandwidth of the first loop system in the open loop state performed in the step S110 is not influenced by the process corner condition, the operating temperature, the operating voltage, etc. and is beneficial to improving the stability and the flexibility of the system.
With continued reference to fig. 1, at step S120, a first ratio of the zero frequency to the first loop bandwidth and a second ratio of the pole frequency to the first loop bandwidth are determined based on the phase margin. Here, the phase margin is an important parameter for measuring loop stability. In general, the greater the phase margin, the better the loop system stability. The feedback loop of the loop system needs to have a phase margin large enough to ensure stable operation of the system under load conditions, but too high a phase margin may cause a decrease in response speed of the system to load changes, thereby being unfavorable for meeting the requirements of high-speed digital communication and communication protocols and the like on response speed. Therefore, the balance between the system stability and the response speed is comprehensively considered when the loop system is designed, and the requirements of the designed loop system on the response speed, such as high-speed digital communication, communication protocols and the like, which are required to be dealt with in practical application are considered. In step S110, a first loop bandwidth of the first loop system in an open loop state is corrected, and then, in step S120, a first ratio of a zero frequency to the first loop bandwidth and a second ratio of a pole frequency to the first loop bandwidth are determined based on a phase margin by using the corrected first loop bandwidth, thereby providing a reference for subsequent correction. Here, the zero frequency and the pole frequency are both based on the phase margin, and the distribution of each of the zero frequency and the pole frequency with respect to the first loop bandwidth is relatively constant, increasing or decreasing in the same proportion in the system stability analysis. In other words, the first ratio of the zero frequency to the first loop bandwidth remains unchanged and the second ratio of the pole frequency to the first loop bandwidth remains unchanged, such that the distribution of the zero frequency and the pole frequency over the first loop bandwidth, respectively, is relatively unchanged when the first loop bandwidth increases or decreases.
With continued reference to fig. 1, in step S130, the capacitance value of the zero capacitance is corrected based on the first ratio and the reference capacitance value, and the capacitance value of the pole capacitance is corrected based on the second ratio and the reference capacitance value. The zero capacitor and the pole capacitor are connected between the charge pump and the generator in parallel, the switch capacitor circuit or the reference resistor is connected between the zero capacitor and the main loop in series, the switch capacitor circuit is equivalent to the reference resistor according to the frequency of the first input signal, and the reference capacitor value is the capacitance value of the switch capacitor circuit. Here, the zero capacitance corresponds to the zero frequency and the pole capacitance corresponds to the pole frequency. The relative positions of the zero frequency and the pole frequency in the first loop bandwidth can be controlled by changing the capacitance values of the zero capacitance and the pole capacitance, so that the phase margin and the stability parameters of the first loop system are controlled. Therefore, in step S110, the first loop bandwidth of the first loop system in the open loop state is corrected, then, in step S120, a first ratio of the zero frequency to the first loop bandwidth and a second ratio of the pole frequency to the first loop bandwidth are determined based on the phase margin, and then, in step S130, the capacitance value of the zero capacitance is corrected using the determined first ratio and the capacitance value of the pole capacitance is corrected using the determined second ratio, so that it is possible to realize correction of the loop parameter of the first loop system according to the design requirement of the first loop system (correction of the first loop bandwidth of the first loop system in the open loop state, correction of the capacitance value of the zero capacitance and also correction of the capacitance value of the pole capacitance). And the characteristic of a circuit structure that a switch capacitor circuit or a reference resistor is connected between the zero capacitor and the main loop in series is utilized, so that the equivalent closed loop stability correction under open loop control is realized. Therefore, the correction method of closed loop stability based on open loop control shown in fig. 1 includes improvement of combination of software and hardware, on one hand, by correcting the first loop bandwidth of the first loop system in the open loop state and determining the first ratio and the second ratio based on the phase margin, the open loop frequency characteristic and the open loop control of the first loop system are utilized to simplify the flow; on the other hand, by disposing a switched capacitor circuit or a reference resistor connected in series between the zero-point capacitor and the main loop, and using the reference resistor and the reference capacitor value, the correction of the closed-loop stability under the open-loop control is made equivalent to the correction of the closed-loop stability under the closed-loop control; therefore, by introducing the circuit structure characteristic that the switch capacitor circuit or the reference resistor is connected between the zero capacitor and the main loop in series, the complex control flow for correcting the closed loop stability under the closed loop control is avoided, the first loop system can be fully opened to operate, the loop system is operated under the open loop state and the correction of the closed loop stability is realized, and the open loop frequency characteristic and the open loop control of the loop system can be utilized, so that the correction time is shortened and the control flow is simplified. With continued reference to fig. 1, it should be appreciated that a switched capacitor circuit comprising a physical capacitance whose capacitance value is a reference capacitance value may be used and is equivalent to a reference resistance; alternatively, the reference capacitance value may be calculated using a physical resistance that does not include a physical capacitance as the reference resistance and using a switched capacitor circuit equivalent to the physical resistance.
In a possible implementation manner, the phase detector is further configured to generate a second charge pump current based on a second input signal frequency and a second clock signal frequency when the first loop system is in a closed loop state, the charge pump is configured to generate a second control voltage signal based on the second charge pump current when the first loop system is in the closed loop state, and the generator is configured to generate the third clock signal based on the second control voltage signal when the first loop system is in the closed loop state, the second clock signal being identical to the third clock signal or obtained by dividing the third clock signal. Thus, correction of the closed loop stability of the first loop system is completed under open loop control, and then frequency locking and phase locking of the second input signal frequency can be completed through the first loop system under closed loop control. The second clock signal is the same as the third clock signal or is obtained by dividing the third clock signal depending on whether the frequency divider is used for the frequency dividing operation. In some embodiments, the first input signal frequency is the same as or different from the second input signal frequency. By introducing a switched capacitor circuit or a reference resistor connected in series between the zero capacitor and the main loop, as mentioned above, a complex control flow for correction of closed loop stability under closed loop control is avoided. Here, the switched capacitor circuit is equivalent to the reference resistor in terms of the first input signal frequency. When the second input signal frequency is different from the first input signal frequency and the difference is within a certain range, the influence on the system stability is limited, the first input signal frequency can be used for correcting the closed loop stability of the first loop system under open loop control, and then the first loop system can be used for completing frequency locking and phase locking of the second input signal frequency under closed loop control. When the second input signal frequency is the same as the first input signal frequency, this means that the correction of the closed loop stability under the open loop control and the frequency locking under the closed loop control are performed sequentially with the same input signal frequency or the same reference signal frequency.
In one possible implementation manner, the switch capacitor circuit is connected in series between the zero capacitor and the main loop, the switch capacitor circuit includes a first switch, a second switch and a first capacitor, a capacitance value of the first capacitor is the reference capacitance value, the first switch and the second switch are connected in series between the zero capacitor and the main loop, one end of the first capacitor is grounded, and the other end of the first capacitor is connected between the first switch and the second switch. In some embodiments, the frequency of the first switch control signal for controlling the first switch and the frequency of the second switch control signal for controlling the second switch are both the first input signal frequency, and the first switch control signal is opposite in phase to the second switch control signal. Therefore, by introducing the circuit structure characteristic that the switch capacitor circuit or the reference resistor is connected between the zero capacitor and the main loop in series, the complex control flow for correcting the closed loop stability under the closed loop control is avoided, the first loop system can be fully opened to operate, the loop system is operated under the open loop state and the correction of the closed loop stability is realized, and the open loop frequency characteristic and the open loop control of the loop system can be utilized, so that the correction time is shortened and the control flow is simplified. In addition, with the first and second switch control signals, this means that the switched capacitor circuit can be implemented equivalent to the reference resistance in terms of the first input signal frequency.
In one possible implementation, the reference resistor is connected in series between the zero capacitance and the main loop, the reference resistor being a physical resistor. In this way, the reference capacitance value can be calculated using a physical resistance that does not include a physical capacitance as a reference resistance and using a switched capacitor circuit equivalent to the physical resistance.
In one possible implementation, when the priority of the first loop bandwidth is higher than the priority of the phase margin, the reference resistor is connected in series between the zero capacitance and the main loop and the reference resistor is a physical resistor; the switched capacitor circuit is serially connected between the zero capacitor and the main loop when the priority of the first loop bandwidth is lower than the priority of the phase margin. As mentioned above, by disposing a switched capacitor circuit or a reference resistor connected in series between the zero-point capacitor and the main loop, and using the reference resistor and the reference capacitor value, the correction of the closed-loop stability under the open-loop control is made equivalent to the correction of the closed-loop stability under the closed-loop control; therefore, by introducing the circuit structure characteristic that the switch capacitor circuit or the reference resistor is connected between the zero capacitor and the main loop in series, the complex control flow for correcting the closed loop stability under the closed loop control is avoided, the first loop system can be fully opened to operate, the loop system is operated under the open loop state and the correction of the closed loop stability is realized, and the open loop frequency characteristic and the open loop control of the loop system can be utilized, so that the correction time is shortened and the control flow is simplified. A switched capacitor circuit comprising a physical capacitance whose capacitance value is a reference capacitance value may be used and is equivalent to a reference resistance; alternatively, the reference capacitance value may be calculated using a physical resistance that does not include a physical capacitance as the reference resistance and using a switched capacitor circuit equivalent to the physical resistance. If a switched capacitor circuit of a physical capacitance is used and the switched capacitor circuit is equivalent to a reference resistance, the capacitance value of the physical capacitance may vary with variations in process angle, temperature, voltage. In the closed-loop stability analysis of a loop system, the measurement of the zero frequency is influenced by the change of the capacitance value of the zero capacitor along with the change of the process angle, the temperature and the voltage, and the measurement of the pole frequency is influenced by the change of the capacitance value of the pole capacitor along with the change of the process angle, the temperature and the voltage. Therefore, by introducing the switch capacitance circuit comprising the physical capacitor, the influence caused by the change of the capacitance value of the physical capacitor along with the change of the process angle, the temperature and the voltage can be utilized to offset the influence of the change of the capacitance value of the zero capacitor along with the change of the process angle, the temperature and the voltage so as to more accurately measure the zero frequency, and offset the influence of the change of the capacitance value of the pole capacitor along with the change of the process angle, the temperature and the voltage so as to more accurately measure the pole frequency, thereby more effectively meeting the design requirement of the phase margin. If a physical resistance that does not contain a physical capacitance is used as the reference resistance and a switched-capacitor circuit equivalent to the physical resistance is used to calculate the reference capacitance value, the system bandwidth, i.e., the first loop bandwidth, can be measured more accurately because the physical resistance is insensitive to temperature variations. Thus, depending on whether the priority of the first loop bandwidth is higher or lower than the priority of the phase margin in the system stability analysis, a more appropriate deployment may be selectively employed. When the priority of the first loop bandwidth is higher than the priority of the phase margin, the reference resistor is connected in series between the zero point capacitor and the main loop and is a physical resistor, so that the measurement effect of the first loop bandwidth is better. When the priority of the first loop bandwidth is lower than the priority of the phase margin, the switch capacitor circuit is connected between the zero capacitor and the main loop in series, so that the measurement effect of the phase margin comprising the zero frequency and the pole frequency is better. In practical applications, some communication protocols, such as the peripheral component interconnect express (Peripheral Component Interconnect Express, PCIe) protocol, are sensitive to changes in phase margin, and therefore in applications employing PCIe protocols or PCIe devices, the priority of the first loop bandwidth is lower than the priority of the phase margin. In memory interface applications, such as double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SRAM) and high bandwidth memory, the requirements for system bandwidth are stringent, so in the context of DDR and high bandwidth memory applications, the priority of the first loop bandwidth is higher than the priority of the phase margin. In this way, the product requirement and the application scenario can be combined, so that the priority of the first loop bandwidth is higher or lower than the priority of the phase margin in the system stability analysis, and a more suitable deployment mode is further selectively adopted.
In one possible implementation, the generator is a voltage controlled oscillator. In some embodiments, the first loop bandwidth is corrected based on a gain of the voltage controlled oscillator and a current value of the first charge pump current. In some embodiments, the correcting the first loop bandwidth is insensitive to both the capacitance value of the zero capacitance and the capacitance value of the pole capacitance. In this way, the first clock signal is not fed back to the phase detector in the open loop state of the first loop system, so that the open loop frequency characteristic and the open loop control flow of the first loop system in the open loop state can be utilized. In correcting the first loop bandwidth of the first loop system in the open loop state, because only the open loop frequency characteristic and the open loop control flow are involved, the first loop bandwidth is corrected based on the gain of the voltage controlled oscillator and the current value of the first charge pump current, and is insensitive to the zero capacitance and the pole capacitance of the first loop system. In other words, by correcting the first loop bandwidth of the first loop system in the open loop state, the open loop frequency characteristic and the open loop control flow of the first loop system can be utilized, so that the influence of the change of loop parameters such as the capacitance values of the zero capacitor and the pole capacitor on the calculation of the first loop bandwidth is reduced as much as possible, and the capacitance values of the loop parameters such as the zero capacitor and the pole capacitor may deviate from the expected values due to the influence of the process angle condition, the working temperature, the working voltage and the like in the preparation process, which means that the first loop bandwidth of the first loop system in the open loop state is corrected without the influence of the process angle condition, the working temperature, the working voltage and the like, and the stability and the flexible adaptability of the system are facilitated.
In one possible embodiment, the reference capacitance value is a capacitance value of the switched-capacitor circuit equivalent to the reference resistance according to the first input signal frequency determined by a successive comparison logic algorithm or a closed-loop test algorithm. In this way, an indirect measurement of the reference capacitance value is achieved.
In one possible implementation, the reference resistor is connected in series between the zero capacitance and the main loop, and the first input signal frequency is ultra-high frequency with respect to the first loop bandwidth. Thus, the first input signal frequency satisfies a certain constraint. If a switched capacitor circuit is used to equivalent reference resistance, i.e. the switched capacitor circuit is connected in series between the zero capacitor and the main loop, the first input signal frequency is required to be within a certain frequency range. If a physical resistor, i.e. the reference resistor, is connected in series between the zero capacitance and the main loop, the first input signal frequency is required to be very high frequency with respect to the first loop bandwidth.
In one possible implementation, the first loop system is a phase locked loop. It should be appreciated that in the field of high-speed data communications, etc., phase-locked loop systems are commonly employed to implement frequency-locked phase-locking functions and recover data signals and clock signals from high-speed serial signals. The first loop system may be a phase-locked or any similar loop system providing a frequency-locked phase-locked function.
Fig. 2 is a schematic diagram of a first loop system in an open loop state according to a first embodiment provided in an embodiment of the present application. As shown in fig. 2, the main loop of the first loop system includes a phase detector 210, a charge pump 212, and a generator 214. The phase detector 210 is configured to generate a first charge pump current 222 based on a first input signal frequency 220 when the first loop system is in the open loop state, the charge pump 212 is configured to generate a first control voltage signal 224 based on the first charge pump current 222 when the first loop system is in the open loop state, and the generator 214 is configured to generate a first clock signal 226 based on the first control voltage signal 224 when the first loop system is in the open loop state. It can be seen that the first clock signal 226 is not fed back to the phase detector 210 when the first loop system is in the open loop state. The first loop system shown in fig. 2 performs correction of closed loop stability under open loop control, and specifically includes: correcting a first loop bandwidth of the first loop system in an open loop state; determining a first ratio of zero frequency to the first loop bandwidth and a second ratio of pole frequency to the first loop bandwidth based on a phase margin; the capacitance value of the zero capacitance 230 is corrected based on the first ratio and the reference capacitance value, and the capacitance value of the pole capacitance 232 is corrected based on the second ratio and the reference capacitance value. Wherein the zero capacitance 230 and the pole capacitance 232 are connected in parallel between the charge pump 212 and the generator 214. A switched capacitor circuit 234 is connected in series between the zero capacitor 230 and the main loop. The switched-capacitor circuit 234 is equivalent to a reference resistance according to the first input signal frequency 220, the reference capacitance value being a capacitance value of the switched-capacitor circuit 234.
Fig. 3 is a schematic diagram of a first loop system in an open loop state according to a second embodiment provided in the examples of the present application. Fig. 3 differs from fig. 2 in that in fig. 3 a reference resistor 236 is connected in series between the zero capacitor 230 and the main loop, the reference resistor 236 being a physical resistor. Other details in fig. 3 correspond to those of fig. 2 and are not described in detail herein.
Referring to fig. 2 and 3 described above, a switched capacitor circuit 234 comprising a physical capacitance whose capacitance value is a reference capacitance value may be used and the switched capacitor circuit 234 is equivalent to a reference resistor 236; alternatively, a physical resistance that does not include a physical capacitance may be used as the reference resistance 236 and the switched capacitor circuit 234 equivalent to the physical resistance may be used to calculate the reference capacitance value.
Fig. 4 is a schematic diagram of a switched capacitor circuit equivalent to a reference resistor according to an embodiment of the present application. As shown in fig. 4, the switched capacitor circuit 234 includes a first switch 244, a second switch 246, and a first capacitor 242. The capacitance value of the first capacitor 242 is the reference capacitance value, and the first switch 244 and the second switch 246 are connected in series between the zero capacitance and the main loop. One end of the first capacitor 242 is grounded, and the other end of the first capacitor 242 is connected between the first switch 244 and the second switch 246. In some embodiments, the frequency of the first switch control signal for controlling the first switch 244 and the frequency of the second switch control signal for controlling the second switch 246 are both the first input signal frequency, and the first switch control signal is in opposite phase to the second switch control signal. Therefore, by introducing the circuit structure characteristic that the switch capacitor circuit or the reference resistor is connected between the zero capacitor and the main loop in series, the complex control flow for correcting the closed loop stability under the closed loop control is avoided, the first loop system can be fully opened to operate, the loop system is operated under the open loop state and the correction of the closed loop stability is realized, and the open loop frequency characteristic and the open loop control of the loop system can be utilized, so that the correction time is shortened and the control flow is simplified. In addition, with the first and second switch control signals, this means that the switched capacitor circuit can be implemented equivalent to the reference resistance in terms of the first input signal frequency.
Fig. 5 is a schematic structural diagram of a computing device according to an embodiment of the present application, where the computing device 500 includes: one or more processors 510, a communication interface 520, and a memory 530. The processor 510, communication interface 520, and memory 530 are interconnected by a bus 540. Optionally, the computing device 500 may further include an input/output interface 550, where the input/output interface 550 is connected to an input/output device for receiving parameters set by a user, etc. The computing device 500 can be used to implement some or all of the functionality of the device embodiments or system embodiments described above in the embodiments of the present application; the processor 510 can also be used to implement some or all of the operational steps of the method embodiments described above in the embodiments of the present application. For example, specific implementations of the computing device 500 performing various operations may refer to specific details in the above-described embodiments, such as the processor 510 being configured to perform some or all of the steps of the above-described method embodiments or some or all of the operations of the above-described method embodiments. For another example, in the embodiment of the present application, the computing device 500 may be used to implement some or all of the functions of one or more components in the apparatus embodiments described above, and the communication interface 520 may be used in particular for communication functions and the like necessary for implementing the functions of these apparatuses, components, and the processor 510 may be used in particular for processing functions and the like necessary for implementing the functions of these apparatuses, components.
It should be appreciated that the computing device 500 of fig. 5 may include one or more processors 510, and that the plurality of processors 510 may cooperatively provide processing power in a parallelized connection, a serialized connection, a serial-parallel connection, or any connection, or that the plurality of processors 510 may constitute a processor sequence or processor array, or that the plurality of processors 510 may be separated into primary and secondary processors, or that the plurality of processors 510 may have different architectures such as employing heterogeneous computing architectures. In addition, the computing device 500 shown in FIG. 5, the associated structural and functional descriptions are exemplary and not limiting. In some example embodiments, computing device 500 may include more or fewer components than shown in fig. 5, or combine certain components, or split certain components, or have a different arrangement of components.
Processor 510 may have a variety of specific implementations, for example, processor 510 may include one or more combinations of a central processing unit (central processing unit, CPU), a graphics processor (graphic processing unit, GPU), a neural network processor (neural-network processing unit, NPU), a tensor processor (tensor processing unit, TPU), or a data processor (data processing unit, DPU), and embodiments of the present application are not limited in particular. Processor 510 may also be a single-core processor or a multi-core processor. Processor 510 may be a combination of a CPU and a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (field-programmable gate array, FPGA), general-purpose array logic (generic array logic, GAL), or any combination thereof. The processor 510 may also be implemented solely with logic devices incorporating processing logic, such as an FPGA or digital signal processor (digital signal processor, DSP) or the like. The communication interface 520 may be a wired interface, which may be an ethernet interface, a local area network (local interconnect network, LIN), etc., or a wireless interface, which may be a cellular network interface, or use a wireless local area network interface, etc., for communicating with other modules or devices.
The memory 530 may be a nonvolatile memory such as a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. Memory 530 may also be volatile memory, which may be random access memory (random access memory, RAM) used as external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). Memory 530 may also be used to store program code and data such that processor 510 invokes the program code stored in memory 530 to perform some or all of the operational steps of the method embodiments described above, or to perform corresponding functions in the apparatus embodiments described above. Moreover, computing device 500 may contain more or fewer components than shown in FIG. 5, or may have a different configuration of components.
The bus 540 may be a peripheral component interconnect express (peripheral component interconnect express, PCIe) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, a unified bus (Ubus or UB), a computer quick link (compute express link, CXL), a cache coherent interconnect protocol (cache coherent interconnect for accelerators, CCIX), or the like. The bus 540 may be classified into an address bus, a data bus, a control bus, and the like. The bus 540 may include a power bus, a control bus, a status signal bus, and the like in addition to a data bus. But is shown with only one bold line in fig. 5 for clarity of illustration, but does not represent only one bus or one type of bus.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. The present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. The computer program product includes one or more computer instructions. When loaded or executed on a computer, produces a flow or function in accordance with embodiments of the present application, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line), or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be accessed by a computer or data storage devices, such as servers, data centers, etc. that contain one or more collections of available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, tape), optical media, or semiconductor media. The semiconductor medium may be a solid state disk, or may be a random access memory, flash memory, read only memory, erasable programmable read only memory, electrically erasable programmable read only memory, register, or any other form of suitable storage medium.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. Each flow and/or block of the flowchart and/or block diagrams, and combinations of flows and/or blocks in the flowchart and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the application can be sequentially adjusted, combined or deleted according to actual needs; the modules in the system of the embodiment of the application can be divided, combined or deleted according to actual needs. Such modifications and variations of the embodiments of the present application are intended to be included herein, if they fall within the scope of the claims and their equivalents.
Claims (15)
1. A method for correcting closed loop stability based on open loop control, the method comprising:
correcting a first loop bandwidth of a first loop system in an open loop state, wherein a main loop of the first loop system includes a phase detector for generating a first charge pump current based on a first input signal frequency when the first loop system is in the open loop state, a charge pump for generating a first control voltage signal based on the first charge pump current when the first loop system is in the open loop state, and a generator for generating a first clock signal based on the first control voltage signal when the first loop system is in the open loop state, the first clock signal not being fed back to the phase detector when the first loop system is in the open loop state;
Determining a first ratio of zero frequency to the first loop bandwidth and a second ratio of pole frequency to the first loop bandwidth based on a phase margin;
correcting the capacitance value of a zero capacitance based on the first ratio and a reference capacitance value, and correcting the capacitance value of a pole capacitance based on the second ratio and the reference capacitance value, wherein the zero capacitance and the pole capacitance are connected between the charge pump and the generator in parallel, a switched capacitor circuit or a reference resistor is connected between the zero capacitance and the main loop in series, the switched capacitor circuit is equivalent to the reference resistor according to the first input signal frequency, and the reference capacitance value is the capacitance value of the switched capacitor circuit.
2. The correction method according to claim 1, characterized in that the phase detector is further configured to generate a second charge pump current based on a second input signal frequency and a frequency of a second clock signal when the first loop system is in a closed loop state, the charge pump being configured to generate a second control voltage signal based on the second charge pump current when the first loop system is in the closed loop state, the generator being configured to generate a third clock signal based on the second control voltage signal when the first loop system is in the closed loop state, the second clock signal being identical to the third clock signal or being frequency-divided by the third clock signal.
3. Correction method according to claim 2, characterized in that the first input signal frequency is the same or different from the second input signal frequency.
4. The correction method according to claim 1, wherein the switched capacitor circuit is connected in series between the zero point capacitor and the main loop, the switched capacitor circuit includes a first switch, a second switch, and a first capacitor, a capacitance value of the first capacitor is the reference capacitance value, the first switch and the second switch are connected in series between the zero point capacitor and the main loop, one end of the first capacitor is grounded, and the other end of the first capacitor is connected between the first switch and the second switch.
5. The correction method according to claim 4, wherein a frequency of a first switch control signal for controlling the first switch and a frequency of a second switch control signal for controlling the second switch are both the first input signal frequency, and the first switch control signal is opposite in phase to the second switch control signal.
6. The correction method according to claim 1, characterized in that the reference resistor is connected in series between the zero capacitance and the main loop, the reference resistor being a physical resistor.
7. The correction method according to claim 1, wherein when the priority of the first loop bandwidth is higher than the priority of the phase margin, the reference resistor is connected in series between the zero point capacitance and the main loop and the reference resistor is a physical resistor; the switched capacitor circuit is serially connected between the zero capacitor and the main loop when the priority of the first loop bandwidth is lower than the priority of the phase margin.
8. The correction method according to claim 1, characterized in that the generator is a voltage controlled oscillator.
9. The correction method according to claim 8, wherein the first loop bandwidth is corrected based on a gain of the voltage controlled oscillator and a current value of the first charge pump current.
10. The correction method according to claim 9, characterized in that correcting the first loop bandwidth is insensitive to both the capacitance value of the zero capacitance and the capacitance value of the pole capacitance.
11. The correction method according to claim 1, wherein the reference capacitance value is a capacitance value of the switched-capacitor circuit equivalent to the reference resistance according to the first input signal frequency determined by a successive comparison logic algorithm or a closed loop test algorithm.
12. The correction method according to claim 1, characterized in that the reference resistor is connected in series between the zero point capacitance and the main loop, and the first input signal frequency is an ultra-high frequency with respect to the first loop bandwidth.
13. Correction method according to any one of claims 1 to 12, characterized in that the first loop system is a phase locked loop.
14. A computer device, characterized in that it comprises a memory, a processor and a computer program stored on the memory and executable on the processor, which processor implements the method according to any of claims 1 to 13 when executing the computer program.
15. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 1 to 13.
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