CN116896375A - Ultra-low power instant locking phase-locked loop (PLL) - Google Patents

Abstract

Systems and methods reduce the lock time of an all-digital phase-locked loop (ADPLL) type II circuit by performing steps that include: receiving a reference signal having a reference frequency; and setting a Digitally Controlled Oscillator (DCO) to a target frequency that is greater than the reference frequency. The DCO generates an output signal for generating a feedback signal. Determining an initial phase difference between the reference signal and the feedback signal using a time-to-digital converter; and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce a lock time of the ADPLL circuit such that the ADPLL circuit reaches a steady state condition in ten or less cycles of the reference signal.

Description

Ultra-low power instant locking phase-locked loop (PLL)

The inventors:

Cheng-Hsien Hung

Chun-Wei Hsu

ChunCheng Chou

cross Reference to Related Applications

The present application is based on the priority of co-pending and commonly assigned U.S. provisional patent application No. 63/328,358 entitled "ULTRA-LOW POWER INSTANT LOCK PHASE LOCK LOOP (PLL) [ ULTRA-low power instant lock phase-locked loop (PLL) ]" by the inventors filed on day 4 and 7 of 2022 as required by 35u.s.c. ≡119 (e) and U.S. non-provisional patent application No. 18/113,601 entitled "ULTRA-LOW POWER INSTANT LOCK PHASE LOCK LOOP (PLL) [ ULTRA-low power instant lock phase-locked loop (PLL) ]" by the inventors filed on day 23 of 2023 as "Cheng-Hsien, chun-Wei Hsu and Chun Chou. Each reference mentioned in this patent document is incorporated herein by reference in its entirety.

Background

Technical Field

The present disclosure relates generally to circuits. More specifically, the present disclosure relates to systems and methods for improving performance parameters in circuits including PLLs.

Background

PLL's are widely used in applications such as RF demodulators, spectrum analyzers, and frequency synthesizers. Phase and frequency locking by using a PLL advantageously reduces switching times, for example when transitioning from a transmit mode to a receive mode, and vice versa. Ultimately, this helps to increase data throughput and reduce power consumption of the circuit. While operating at low bandwidth helps suppress unwanted noise typically caused by a Voltage Controlled Oscillator (VCO), low bandwidth PLLs inherently have higher lock times or settling times. Thus, circuit designers are often faced with a tradeoff between bandwidth requirements and other performance metrics. It would therefore be desirable to overcome these limitations by providing a system and method that allows a designer to optimize critical design metrics in a circuit that utilizes a PLL, while achieving fast lock and good phase noise performance, ideally at low power and without sacrificing bandwidth.

Drawings

Reference will now be made to embodiments of the application, examples of which are illustrated in the accompanying drawings. The drawings are intended to be illustrative, and not limiting. While the application is generally described in the context of these embodiments, it will be understood that it is not intended to limit the scope of the application to these particular embodiments. The items in the drawings are not drawn to scale.

Fig. 1 is a simplified circuit diagram of an exemplary system implementation in a broadband optical communication link according to various embodiments of the present disclosure.

Fig. 1 is a simplified block diagram of a conventional analog type II PLL.

Fig. 2 illustrates a simplified block diagram of an all-digital phase-locked loop (ADPLL) circuit according to various embodiments of the present disclosure.

FIG. 3 is a graph illustrating an exemplary reduced post settling time using a locking procedure in accordance with various embodiments of the present disclosure.

Fig. 4 is a flowchart of an illustrative process for reducing lock time in a PLL circuit in accordance with various embodiments of the disclosure.

Detailed Description

In the following description, for purposes of explanation, specific details are set forth in order to provide an understanding of the present application. It will be apparent, however, to one skilled in the art that the application may be practiced without these details. Furthermore, those skilled in the art will appreciate that the embodiments of the application described below may be implemented in a variety of ways, such as a process, an apparatus, a system, a device, or a method, on a tangible computer readable medium.

The components or modules shown in the figures illustrate exemplary embodiments of the application and are intended to avoid obscuring the application. It should also be understood that throughout this discussion, components may be described as separate functional units that may include sub-units, but those skilled in the art will recognize that various components or portions thereof may be divided into separate components or may be integrated together, including integrated in a single system or component. It should be noted that the functions or operations discussed herein may be implemented as components. The components may be implemented in software, hardware, or a combination thereof.

Furthermore, connections between components or systems within the figures are not intended to be limited to direct connections. Rather, the data between these components may be modified, reformatted, or otherwise changed by intermediate components. Moreover, additional connections or fewer connections may be used. It should also be noted that the terms "coupled," "connected," or "communicatively coupled" are to be understood as including direct connections, indirect connections via one or more intermediary devices, and wireless connections.

Reference throughout this specification to "one embodiment," "a preferred embodiment," "an embodiment," or "embodiments" means that a particular feature, structure, characteristic, or function described in connection with the embodiment is included in at least one embodiment and may be included in more than one embodiment of the present application. Moreover, appearances of the phrases in various places in the specification are not necessarily all referring to the same embodiment or embodiments.

Certain terminology is used throughout this specification in various places for the purpose of description and should not be taken in a limiting sense. The service, function or resource is not limited to a single service, function or resource; the use of these terms may refer to a group of related services, functions, or resources, which may be distributed or aggregated.

The terms "include," "comprising," "includes," and "including" are to be construed as open-ended terms and any listed items thereafter are examples and are not intended to be limited to the listed items. Any headings used herein are for organizational purposes only and are not to be used to limit the scope of the description or the claims. Each reference mentioned in this patent document is incorporated herein by reference in its entirety.

It should be noted that the embodiments described herein are presented in the context of a differential broadband high frequency amplifier, but those skilled in the art will recognize that the teachings of the present disclosure are not limited to these applications and may be used in other contexts as well.

In this document, the terms "block" and "building block" refer to any circuit component, as well as any combination of circuit components that form a sub-circuit.

Fig. 1 is a simplified block diagram of a conventional analog type II PLL circuit. PLL circuit 100 includes PFD 102 that generates an error signal, charge pump 104 that amplifies the error signal generated by PFD 102, loop filter (LPF) 106, VCO 108, and divider circuit 110. The output of VCO 108 is fed back to the input of PFD 102 via a feedback control loop. PFD 102 further receives a reference clock signal (denoted REF CLK) at its input.

Although PLL circuit 100 in fig. 1 cannot directly control the phase of VCO 108, circuit 100 may adjust the phase of VCO 108 (e.g., by adjusting the frequency) until frequency and phase lock is achieved. Thus, in operation, by adjusting the frequency of VCO 108 to maintain a phase match, PFD 102 converges to a 0 degree phase relationship between the reference clock signal and VCO 108.

As with other analog type II PLLs, the PLL circuit 100 has a detector configuration that outputs a signal proportional to the phase difference between two input signals when the input signals have the same frequency. The lock time of PLL circuit 100 is generally inversely proportional to the loop bandwidth. The low loop bandwidth advantageously suppresses noise caused by the reference clock and circuit components other than VCO 108. However, this noise reduction comes at the cost of significantly extending the lock time, which negatively affects the length of the time interval between data packets, or the time between receiving and transmitting data packets. However, shorter lock times and shorter time intervals between data packets are desirable to increase the effective data rate of the communication system.

It is therefore highly desirable to have PLL circuit solutions that promote fast locking. The various embodiments herein utilize a "one-shot" or instant locking mechanism, i.e., a locking scheme that advantageously produces a near zero settling time.

Fig. 2 illustrates a simplified block diagram of an ADPLL circuit according to various embodiments of the present disclosure. As depicted, ADPLL circuit 200 includes two input signals: a reference clock signal 201 and a feedback signal 211. The circuit 200 further includes a TDC 202, a digital phase compensation circuit 204, a digital LPF 206, a Digitally Controlled Oscillator (DCO) 208, and a frequency divider circuit 210.

In operation, the TDC 202 may be used as a PFD that detects a deviation of the phase of the DCO 208 from the phase of the reference clock signal 201, for example, by quantifying the relative time difference in the rising edges of the two input signals 201 and 211. Based on this relative time difference, which by definition is greater than zero, the TDC 202 generates a non-negative error signal 203 representing the phase difference or digital phase error between the input signals 201, 211. In an embodiment, the digital LPF 206 is implemented as a low pass filter that attenuates the high frequency and phase noise contained in the error signal 203 and places the DCO 208 in frequency and phase lock by adjusting the phase of the phase compensation signal 205 to lock to the phase of the reference clock signal 201. The digital LPF 206 may generate a control signal 207 (e.g., a digital code representing a fractional frequency) that may be used to control the frequency of the DCO 208, for example, by: the variable clock signal is changed to alter the relative time difference (i.e., phase) between the rising edges to reduce any detected phase difference until a steady state (locked condition) is achieved, which causes the frequency of the DCO 208 to match the frequency of the reference clock 201.

In an embodiment, DCO 208 may be implemented as a variable phase device that uses a free-running crystal oscillator to generate a variable clock signal (e.g., through the use of an LC tank circuit that includes one or more digitally controlled varactors). The variable clock signal may be divided down by a divider circuit 210 and fed back into the TDC 202, which in an embodiment compares the phase of the clock signal 209 with a reference phase of a reference clock signal 201 (which typically operates at a lower frequency than the DCO 208) to generate a digital word (digital word) representing the phase error 203.

It should be noted that while ADPLL circuit 200 in fig. 2 is depicted as a digital circuit that includes only low-footprint and low-power digital components, it is understood that ADPLL circuit 200 may include any number of analog components. It is further appreciated that instant locking using the various embodiments presented herein can help shorten the response time of an overall system including ADPLL circuit 200 in applications other than communication applications. Individual blocks in ADPLL circuit 200 may include a digital interface that may be communicatively coupled to one or more other blocks. For example, a digital interface may be used as a control interface to allow adjustment of one or more circuit parameters (such as initial circuit conditions), as discussed in more detail below.

Various embodiments of the present disclosure take advantage of the fact that: once the initial conditions of some or all of the individual blocks are known, a near zero lock time (i.e., an instant lock condition) of the ADPLL circuit 200 may be achieved. In detail, in an embodiment, immediate lock may be obtained by defining initial circuit conditions for a plurality of building blocks within a loop. These conditions may be selected so that the relevant building block may exhibit its steady state condition relatively quickly, which greatly helps reduce settling time and enables phase and frequency locking faster than otherwise. Initial conditions appropriate for individual building blocks may cause some blocks to have settling times nine times faster than the rate of the reference clock. Thus, each individual building block may achieve a settling time of near zero (e.g., within one to five cycles or periods of the reference clock 201), for example, whenever a set point of the ADPLL circuit 200 is changed. It should be noted that the bandwidth of the reference clock 201 is typically greater than the loop bandwidth, thus making the reference clock nine times faster than the loop itself, for example.

Ideally, to lock the phase and frequency in the ADPLL circuit 200, a lock condition is set for all building blocks in the loop. For example, to lock the phase, the phase difference between the output of DCO 208 and reference clock 201 should be zero. In practice, however, it is often difficult to determine the exact operating conditions of all of the building blocks within the circuit. For example, the initial phase difference between the output of DCO 208 and reference clock 201 is typically non-zero. In fact, unlike the initial condition of other digital blocks that may be determined, the initial phase difference may be unknown and the user may not be able to control the initial phase.

Thus, in an embodiment, the initial condition of one or more blocks is obtained, for example by means of measurement or calibration, while other blocks may be assigned an arbitrary fixed initial condition. In an embodiment, to account for process and environmental variations, calibration may be employed to determine appropriate settings to achieve desired target conditions. For example, the TDC 202 may measure and record a phase difference between the output 211 of the divider circuit 210 and the phase of the reference clock 201. The phase compensation circuit 204 may then use the measurement result to set the phase difference to an arbitrarily selected value, preferably a zero value, which may then be provided as an input to the digital LPF 206, forcing the zero value to be the initial condition of the digital LPF 206, which is not facilitated by an analog circuit such as the circuit depicted in fig. 1.

In an embodiment, ADPLL circuit 200 may be implemented according to an architecture that allows the lock condition of all blocks in the loop in circuit 200 to be predetermined. For example, ADPLL circuit 200 may be implemented as a higher order loop for zeroing out or compensating for most loop conditions. For a type II PLL implementation, such as that shown in fig. 2, the digital LPF 206 input will converge to zero once the lock is achieved. At lock, the phase difference between the phase of the phase ADPLL circuit 200 at the output 209 and the phase of the reference clock 201 remains unchanged. In lock, zero phase difference is expected at the input of the TDC 202 unless no offset is added to the TDC 202 or the phase compensation circuit 204.

In an embodiment, to quickly stabilize the ADPLL circuit 200, the loop frequency may first be locked, for example, by setting the DCO 208 to the desired frequency. To account for process and environmental variations, the DCO 208 may be calibrated (e.g., in an open loop configuration) to determine a digital code. The appropriate digital code may be generated, for example, by using a frequency encoder that performs a closed loop of the desired locking frequency within a predetermined accuracy range. It will be appreciated that a calibration procedure suitable for one or more blocks in the ADPLL circuit 200 may be automatically performed during the power-up phase of the ADPLL circuit 200, for example, to achieve linearity of the frequency modulation and to improve linearity of the TDC 202.

In an embodiment, the initial, known or random phase difference or phase error received, measured or detected at the TDC 202 may be zeroed out in the digital domain by the phase compensation circuit 204 before being provided to the digital loop filter 206 to ultimately zero out the phase error in the higher order PLL 200. It will be appreciated that the digital phase compensation circuit 204 that obtains the initial phase difference may be integrated into the TDC 202 and may be used to measure and encode the initial phase difference, for example, as an offset, delay, or shift. In an embodiment, the digital phase compensation circuit 204 may take the initial phase difference of the value, treat it as zero, and lock it to that value in the next clock cycle. In other words, the digital phase compensation circuit 204 may treat the measured initial phase difference as a zero phase difference such that once the appropriate digital code is applied to the DCO 208 to lock the frequency, the ADPLL circuit 200 achieves immediate locking.

Advantageously, the zeroed initial phase difference eliminates the need to build in a relatively large margin for the ADPLL circuit 200, as the output 203 of the TDC 202 can be used to directly achieve the desired lock condition. In addition, the output frequency of DCO 208 is controlled by reference clock 201, i.e., the loop frequency is unchanged, as any errors will be corrected by the loop itself. Further, embodiments herein ensure that the lock-in time remains fairly short even if no immediate lock-in can be achieved for a desired period of time under certain operating conditions (e.g., due to the presence of unwanted phase noise, noise caused by current injection at the circuit node, or other variations).

In summary, instant locking using the various embodiments presented herein may advantageously increase data throughput by reducing the switching interval (and thus power consumption) between transmit and receive modes. It should be noted that in embodiments, the ADPLL circuit may be implemented in a frequency divider-less architecture, particularly in high frequency applications, which may be used to advantageously reduce power consumption, for example, by eliminating delays that would otherwise result from a circuit including a frequency divider.

FIG. 3 is a graph illustrating an exemplary settling time using a locking procedure in accordance with various embodiments of the present disclosure. As depicted, the PLL frequency tends to stabilize after undergoing two distinct phases: the sharp phase is followed by the steady phase. Intuitively, setting the initial condition of the circuit to be at or close enough to the steady state condition of the circuit advantageously reduces the jerk phase. Thus, unlike existing circuits, PLL circuits according to various embodiments need only correct at most relatively small phase and/or frequency errors before reaching the desired steady state condition, which significantly reduces the lock time of ADPLL circuit 200.

Fig. 4 is a flowchart of an illustrative process for reducing lock time of a type II ADPLL circuit in accordance with various embodiments of the disclosure. In an embodiment, the process 400 may begin at step 402 with receiving a reference signal having a reference frequency at a TDC circuit, for example, from a reference clock or DTC circuit.

At step 404, the DCO, which may be implemented in an ADPLL circuit and generates an output signal, may be set to a target frequency, e.g., a target frequency that is a multiple higher than a reference frequency.

At step 406, the DCO may generate a feedback signal in response to receiving the output signal related to the DCO.

At step 408, an initial phase difference between the reference clock signal and the output signal may be determined using the TDC circuit.

Finally, at step 410, a digital phase compensation circuit that adjusts the initial phase difference to a substantially zero phase difference to reduce the lock time of the ADPLL circuit may be used such that the ADPLL circuit reaches a steady state condition in ten or less cycles of the reference signal.

Those skilled in the art will recognize that, in this context: (1) certain steps may optionally be performed; (2) The steps may not be limited to the specific order set forth herein; (3) certain steps may be performed in a different order; and (4) some steps may be accomplished simultaneously.

It will be appreciated that the stop conditions may include: (1) a set number of iterations have been performed; (2) a certain amount of processing time has been reached; (3) Convergence (e.g., the difference between successive iterations is less than a threshold); (4) divergence (e.g., performance degradation); (5) acceptable results have been achieved; and (6) all data has been processed.

Aspects of the application may be encoded on one or more non-transitory computer-readable media with instructions for one or more processors or processing units to cause steps to be performed. It should be noted that the one or more non-transitory computer readable media should include volatile memory and non-volatile memory. It should be noted that alternative implementations are possible, including hardware implementations or software/hardware implementations. The hardware implemented functions may be implemented using Application Specific Integrated Circuits (ASICs), programmable arrays, digital signal processing circuitry, or the like. Accordingly, the terms in any claims are intended to cover both software and hardware implementations. Similarly, the term "one or more computer-readable media" as used herein includes software and/or hardware or a combination thereof having a program of instructions embodied thereon. In view of these alternatives to the embodiments, it will be appreciated that the figures and accompanying description provide functional information that would be required by one skilled in the art to write program code (i.e., software) and/or fabricate circuits (i.e., hardware) to perform the required processing.

It should be noted that embodiments of the present application may further relate to computer products with a non-transitory tangible computer-readable medium that have computer code thereon for performing various computer-implemented operations. The media and computer code may be those specially designed and constructed for the purposes of the present application, or they may be of the kind well known or available to those having skill in the relevant arts. Examples of tangible computer readable media include, but are not limited to: magnetic media such as hard disks; optical media such as CD-ROM and holographic devices; a magneto-optical medium; and hardware devices that are specially configured for storing or for storing and executing program code, such as ASICs, programmable Logic Devices (PLDs), flash memory devices, and ROM and RAM devices. Examples of computer code include machine code, such as produced by a compiler, and files containing higher level code that are executed by a computer using an interpreter. Embodiments of the application may be implemented in whole or in part as machine-executable instructions in program modules that are executed by a processing device. Examples of program modules include libraries, programs, routines, objects, components, and data structures. In a distributed computing environment, program modules may be located in a local, remote, or both environment.

Those skilled in the art will recognize that no computing system or programming language is critical to the practice of the application. Those skilled in the art will also recognize that the various elements described above may be physically and/or functionally divided into sub-modules or combined together.

Those skilled in the art will appreciate that the foregoing examples and embodiments are exemplary and not limiting to the scope of the present disclosure. All permutations, enhancements, equivalents, combinations and modifications thereto that will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings are intended to be included within the true spirit and scope of the present disclosure. It should also be noted that the elements of any claim may be arranged in a variety of ways, including having a variety of dependencies, configurations, and combinations.

Claims (10)

1. An all-digital phase-locked loop (ADPLL) circuit, comprising:

a time-to-digital converter (TDC) comprising a first input and a second input, the TDC generating a quantized output representing a phase difference between the first input and the second input;

a digital phase compensation circuit that performs a step that includes generating an adjusted quantized output that represents a substantially zero phase difference between the first input and the second input;

a Digitally Controlled Oscillator (DCO) that generates a DCO output signal in response to receiving the adjusted quantized output and a target frequency; and

a feedback path that couples the DCO output signal to the second input using a feedback signal.

2. The ADPLL of claim 1, further comprising a snapshot circuit coupled to the second input, the snapshot circuit sub-sampling the DCO output signal to generate a first clock signal having a first clock frequency that is lower than a reference frequency of a reference signal.

3. The ADPLL of claim 2, wherein the snapshot circuit sub-samples the DCO output signal in response to receiving a rising edge of the DCO output signal operating at the target frequency and a rising edge of a reference signal including the reference frequency.

4. The APLL of claim 1, wherein the feedback path comprises a frequency divider that generates the feedback signal in response to receiving the DCO output signal.

5. The APLL of claim 1, wherein the DCO obtains the target frequency from a calibration using an open loop circuit configuration.

6. A method for reducing lock time of an all-digital phase-locked loop (ADPLL) circuit of type II, the method comprising:

receiving a reference signal having a reference frequency;

setting a Digital Controlled Oscillator (DCO) to a target frequency that is a multiple higher than the reference frequency, the DCO generating an output signal;

generating a feedback signal using the output signal;

determining an initial phase difference between the reference signal and the feedback signal using a time-to-digital converter (TDC); and

the digital initial phase compensation circuit is used to adjust the initial phase difference to a substantially zero phase difference to reduce the lock time of the ADPLL circuit so that the ADPLL circuit reaches a steady state condition in ten or less cycles of the reference signal.

7. The method of claim 11, wherein the initial phase difference is defined by a time difference between rising edges of the feedback signal closest to the rising edge of the reference signal.

8. The method of claim 11, wherein the target frequency is obtained from a calibration using an open loop circuit configuration.

9. The method of claim 13, wherein the calibrating generates a digital code that causes the DCO to operate at the target frequency.

10. The method of claim 11, wherein the DCO output signal is divided by a divider located in the feedback path.