CN116149243B - High-precision time sequence control method and device - Google Patents

Abstract

The embodiment of the invention provides a high-precision time sequence control method and device, which are applied to the technical field of time sequence control of electronic equipment. The high-precision time sequence control device comprises a crystal oscillator, an analog-to-digital converter, a digital phase-locked loop, a digital-to-analog converter and a timing controller which are sequentially coupled. The timing controller is also coupled to the analog-to-digital converter. Wherein, the crystal oscillator is used for: a local clock signal is generated. The analog-to-digital converter is used for: the local clock signal is converted into a first digital signal. The sampling clock signal is input from the timing controller and converted into a second digital signal. The digital phase-locked loop is used for: and obtaining a third digital signal according to the first digital signal and the second digital signal. The digital-to-analog converter is used for: and obtaining a reference clock signal according to the third digital signal. The timing controller is used for: a sampling clock signal and a plurality of timing control signals are derived from the reference clock signal.

Description

High-precision time sequence control method and device

Technical Field

The present invention relates to the field of electronic device timing control technologies, and in particular, to a high-precision timing control method and apparatus.

Background

In an electronic device, there are different timings between different execution operations. In general, the timing controller generates a plurality of timing control signals through a local time signal, so that the generated plurality of timing control signals respectively control different modules to execute responsive functional operations. But with the development of technology. Control logic for electronic devices tends to be complex and faster. This will have higher demands on the number of timing control signals generated, clock accuracy, etc. The local clock signal is usually realized in the form of crystal oscillator, etc., which has unavoidable frequency offset, etc. due to the problems of technology, materials, etc. And the lower the cost is, the larger the frequency deviation of the local clock signal generated by the crystal oscillator is, and the larger the interference of time sequence control is.

Disclosure of Invention

The embodiment of the invention provides a high-precision time sequence control method and a high-precision time sequence control device, which improve the precision of clock signals and further improve the precision of time sequence control.

In order to achieve the above purpose, the embodiment of the present invention adopts the following technical scheme:

in a first aspect, a high-precision timing control apparatus is provided, the high-precision timing control apparatus includes a crystal oscillator, an analog-to-digital converter, a digital phase-locked loop, a digital-to-analog converter, and a timing controller coupled in sequence; the timing controller is also coupled with the analog-to-digital converter; wherein,,

The crystal oscillator is used for: generating a local clock signal;

the analog-to-digital converter is used for: converting the local clock signal into a first digital signal; inputting a sampling clock signal from the timing controller and converting the sampling clock signal into a second digital signal;

the digital phase-locked loop is used for: obtaining a third digital signal according to the first digital signal and the second digital signal;

the digital-to-analog converter is used for: obtaining a reference clock signal according to the third digital signal;

the timing controller is used for: a sampling clock signal and a plurality of timing control signals are derived from the reference clock signal.

In one possible implementation, the digital-to-analog converter includes an analog voltage source circuit, a digital gating circuit; wherein,,

the analog voltage source circuit is used for: outputting a plurality of analog voltages with different voltage values to a plurality of power supply terminals of the digital gating circuit;

the digital gating circuit is used for: the digital gating circuit is controlled to output a reference clock signal according to the plurality of analog voltages according to the third digital signal.

In one possible implementation, an analog voltage source circuit includes a reference voltage circuit, an enhancement voltage circuit, a first operational amplifier, a second operational amplifier, and a resistor string; the output end of the reference voltage circuit is respectively coupled with the first operational amplifier and the second operational amplifier; the output end of the first operational amplifier is coupled with the first end of the resistor string; output end of the second operational amplifier coupled to the second end of the resistor string; the boost voltage circuit is coupled with the resistor string; wherein,,

The reference voltage circuit is used for: outputting a first reference analog voltage to a first operational amplifier and outputting a second reference analog voltage to a second operational amplifier;

the boost voltage circuit is used for: outputting an enhanced voltage to the middle section of the resistor string;

the resistor string is used for: the plurality of resistor ends of the resistor string output a plurality of analog voltages according to the enhanced voltage, the first reference analog voltage and the second reference analog voltage.

In one possible embodiment, the first input and the second input of the boost voltage circuit are coupled to a reference voltage circuit, respectively; the boost voltage circuit is used for: the boost voltage is output to the resistor string according to the first reference analog voltage and the second reference analog voltage.

In one possible embodiment, the apparatus further comprises a detection controller; the detection controller is coupled with the output end of the digital-to-analog converter; wherein,,

the detection controller is used for: obtaining a compensation clock signal according to the reference clock signal; the frequency and the amplitude of the compensating clock signal are equal to those of the leakage clock signal of the digital-to-analog converter, and the phase of the compensating clock signal is opposite to that of the leakage clock signal;

the compensated clock signal is incorporated into the local clock signal and a first digital signal is derived based on the local clock signal in which the compensated clock signal is incorporated.

In one possible embodiment, the high-precision timing control apparatus may further include a shaping circuit. The crystal oscillator outputs the local clock signal to the shaping circuit, and outputs the local clock signal to the analog-to-digital converter after shaping processing by the shaping circuit.

In one possible embodiment, the high-precision timing control apparatus further includes a power supply circuit. The power supply circuit comprises an amplitude detection circuit, a comparison circuit and an adjustable power supply. Input end of amplitude detection circuit the output of the digital-to-analog converter is coupled. The output end of the amplitude detection circuit is coupled with the first input end of the comparison circuit, and the second input end of the comparison circuit inputs the comparison reference voltage. The output of the comparison circuit is coupled to the controlled terminal of the adjustable power supply. The output end of the adjustable power supply is coupled with the power receiving end of the numerical control oscillator. The amplitude detection comparison circuit is used for detecting the amplitude of the reference clock signal output by the digital-to-analog converter and outputting amplitude voltage according to the amplitude. The comparison circuit is used for outputting control voltage according to the comparison result and the reference voltage and the amplitude voltage, and the control voltage is used for controlling the power supply voltage output by the adjustable power supply to the numerical control oscillator. In embodiments of the present invention, the supply of a conventional oscillator is typically implemented based on an LDO linear regulator. A fixed voltage is output to the oscillator via the LDO to power the oscillator. However, due to the influence of the production process and the production voltage of the oscillator, the starting gain, the starting oscillation time and the oscillation amplitude of the oscillator are greatly different, and a certain starting time is needed to stabilize the locked frequency required by the phase-locked loop. In the embodiment of the invention, the amplitude of the output reference clock signal is detected by the amplitude detection circuit, and the magnitude of the power supply voltage output to the numerical control oscillator is fed back and regulated according to the comparison result between the amplitude voltage and the comparison reference voltage, so that the output clock signal is stabilized at a fixed frequency after the oscillation starts, and the time sequence control is more accurate.

In a second aspect, the embodiment of the invention also provides a high-precision time sequence control method, which is based on a high-precision time sequence control device; the apparatus includes a timing controller. The method comprises the following steps:

converting the local clock signal into a first digital signal; obtaining a sampling clock signal from the timing controller and converting the sampling clock signal into a second digital signal;

obtaining a third digital signal according to the first digital signal and the second digital signal;

obtaining a reference clock signal according to the third digital signal;

the timing controller outputs a sampling clock signal and a plurality of timing control signals according to the reference clock signal.

In one possible implementation manner, the obtaining the third digital signal according to the first digital signal and the second digital signal includes:

generating a plurality of analog voltages with different voltage values;

and selecting a plurality of analog voltages according to the third digital signal to obtain a reference clock signal.

In one possible embodiment, the apparatus further comprises a resistor string. The generating a plurality of analog voltages having different voltage values includes:

outputting a first reference analog voltage to a first end of the resistor string and outputting a second reference analog voltage to a second end of the resistor string;

Outputting an enhanced voltage to the middle section of the resistor string;

the plurality of resistor ends of the resistor string output a plurality of analog voltages according to the enhanced voltage, the first reference analog voltage and the second reference analog voltage.

In one possible embodiment, the outputting the boost voltage to the middle end of the resistor string includes:

the boost voltage is output to the middle section of the resistor string according to the first reference analog voltage and the second reference analog voltage.

In one possible embodiment, the method further comprises,

obtaining a compensation clock signal according to the reference clock signal; the frequency and the amplitude of the compensating clock signal are equal to those of the leakage clock signal of the digital-to-analog converter, and the phase of the compensating clock signal is opposite to that of the leakage clock signal;

the compensated clock signal is incorporated into the local clock signal and a first digital signal is derived based on the local clock signal in which the compensated clock signal is incorporated.

The embodiment of the application has at least the following beneficial effects:

(1) The clock signal directly provided by the crystal oscillator is used for generating different time sequence control signals, and unavoidable frequency deviation exists due to the crystal oscillator. So that the generated clock control signal will also have a frequency offset. In the application scene of high-precision time sequence control, the local clock signal generated by the crystal oscillator is calibrated and stabilized through the digital phase-locked loop, and a more accurate reference clock signal is obtained. Different time sequence control signals are generated through the reference clock signals so as to meet the application requirements of high-precision time sequence control.

(2) When a digital phase-locked loop is used for calibration. An analog-to-digital converter is required to be provided at the input of the digital phase-locked loop to convert the local clock signal into a corresponding digital signal. And a digital-to-analog converter is arranged at the output end of the digital phase-locked loop to convert the third digital signal output by the digital phase-locked loop into a reference clock signal. In the application scene, the digital-to-analog converter has the problems of settling time limitation, clock distortion and the like. In a resistive digital-to-analog converter, the settling time limit is mainly manifested in that the digital-to-analog conversion rate of the digital-to-analog converter is limited by the amount of load carrying capacity of the digital-to-analog converter for analog voltages that are analog-to-digital converted. The embodiment of the application provides the load carrying capacity of the digital-to-analog converter by arranging the enhanced voltage circuit in the resistive digital-to-analog converter, thereby reducing the settling time. The clock distortion is mainly expressed as that the digital-to-analog converter is influenced by the process, the device parameters and the like, and clock leakage exists. When the digital-to-analog converter is used for the first time, the digital-to-analog converter is detected by the detection controller, so that parameters of clock leakage of the digital-to-analog converter are obtained, corresponding compensation clock signals are generated to compensate the parameters, the influence of the clock leakage of the digital-to-analog converter on the reference clock signals is removed, and the precision of the reference clock signals is higher.

(3) In the process of the digital phase-locked loop operation, a numerical control oscillator is arranged in the digital phase-locked loop. The function of locking the phase is realized by an oscillation signal generated by the numerical control oscillator. A fixed voltage is typically provided to a digitally controlled oscillator by a low dropout linear regulator (LDO). However, after the numerically controlled oscillator receives a fixed voltage, a certain oscillation starting time is required to output an oscillation signal with stable amplitude. The starting time of the numerical control oscillator is longer, and the starting amplitude, the starting gain and the like are also larger under the influence of the process, the parameters and the like. The embodiment of the application sets the reference voltage and the comparison circuit. The oscillation amplitude is rapidly detected by the amplitude detection circuit in the oscillation starting time, the oscillation amplitude is compared with the reference voltage, the voltage output by the LDO is regulated according to the comparison result, and the voltage output by the LDO is rapidly regulated by a loop self-feedback mode, so that the digital controlled oscillator rapidly reaches the oscillation stable state.

Drawings

Fig. 1 is a schematic structural diagram of a high-precision timing control device according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another high-precision timing control apparatus according to an embodiment of the present invention;

Fig. 3 is a schematic diagram of a digital-to-analog converter according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a second digital-to-analog converter according to another embodiment of the present invention;

fig. 5 is a schematic diagram of a digital-to-analog converter according to another embodiment of the present invention;

fig. 6 is a schematic diagram of a digital-to-analog converter according to another embodiment of the present invention;

FIG. 7 is a schematic diagram of a high-precision timing control apparatus according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a power supply circuit according to an embodiment of the present invention;

FIG. 9 is a flow chart of a high-precision timing control method according to an embodiment of the present invention;

fig. 10 is a flowchart of another high-precision timing control method according to an embodiment of the present invention.

Detailed Description

It should be noted that the terms "first," "second," and the like in the embodiments of the present invention are used for distinguishing between similar features and not necessarily for indicating a relative importance, quantity, or sequence.

The terms "exemplary" or "such as" and the like, as used in relation to embodiments of the present invention, are used to denote examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

The terms "coupled" and "connected" in accordance with embodiments of the invention are to be construed broadly, and may refer, for example, to a physical direct connection, or to an indirect connection via electronic devices, such as, for example, electrical resistance, inductance, capacitance, or other electrical devices.

In an electronic device, there are different timings between different execution operations. In general, the timing controller generates a plurality of timing control signals through a local time signal, so that the generated plurality of timing control signals respectively control different modules to execute responsive functional operations. But with the development of technology. Control logic for electronic devices tends to be complex and faster. This will have higher demands on the number of timing control signals generated, clock accuracy, etc. The local clock signal is usually realized in the form of crystal oscillator, etc., which has unavoidable frequency offset, etc. due to the problems of technology, materials, etc. And the lower the cost is, the larger the frequency deviation of the local clock signal generated by the crystal oscillator is, and the larger the interference of time sequence control is.

For this purpose, the embodiment of the present invention provides a high-precision timing control device, as shown in fig. 1, where the high-precision timing control device 1000 includes a crystal oscillator 100, an analog-to-digital converter 200, a digital phase-locked loop 300, a digital-to-analog converter 400, and a timing controller 500 that are sequentially coupled; the timing controller 500 is also coupled to the analog-to-digital converter 400. Wherein:

The crystal oscillator 100 is used for: a local clock signal is generated. The analog-to-digital converter 100 is used for: converting the local clock signal into a first digital signal; the sampling clock signal is input from the timing controller 500 and converted into a second digital signal. The digital phase-locked loop 300 is used to: and obtaining a third digital signal according to the first digital signal and the second digital signal. The digital-to-analog converter 400 is used to: and obtaining a reference clock signal according to the third digital signal. The timing controller 500 is configured to: a sampling clock signal and a plurality of timing control signals are derived from the reference clock signal.

In an embodiment of the present invention, the local clock signal is generated by the crystal oscillator 100. The phase-locked loop is used for feeding back an input clock signal as a sampling clock signal to the phase-locked loop, inputting a local clock signal as a reference clock signal, obtaining an output sampling clock signal through the input sampling clock signal and the local clock signal, and continuously feeding back the output sampling clock signal, so that a constant phase difference is kept between the local clock signal and the sampling clock signal, or the phases of the local clock signal and the sampling clock signal are equal. In the embodiment of the present invention, the clock signal is processed in the digital domain, and the digital phase-locked loop 300 is sampled, so that the analog-to-digital converter 200 is required to be disposed at the input end of the digital phase-locked loop 300, so as to convert the input local clock signal and sampling clock signal into corresponding digital signals, and then input the corresponding digital signals into the digital phase-locked loop 300. Meanwhile, a digital-to-analog converter 400 is also required to be disposed at the output end of the digital phase-locked loop 300 to convert the third digital signal outputted from the digital phase-locked loop 300 into the reference clock signal. The timing controller 500 then generates a sampling clock signal and a plurality of timing control signals based on the reference clock signal. The sampling clock signal is a clock signal obtained by frequency division from the reference clock signal. The plurality of timing control signals are timing control signals generated based on the reference clock signal, and clock information between the plurality of timing control signals may be the same or different. In the embodiment of the present invention, the precision of the local clock signal is improved by the digital phase-locked loop 300, so that the precision of the generated timing control signal is improved. Compared with the analog phase-locked loop, the digital phase-locked loop can realize a complex control algorithm, can also perform more complex digital filtering operation, and has higher running speed and the like.

Illustratively, as shown in fig. 2, the digital phase locked loop 300 includes a digital phase detector 310, a loop filter 320, and a digitally controlled oscillator 330. In an embodiment of the present invention, the analog-to-digital converter 200 outputs a digital signal to the digital phase detector 310. The digital phase detector 310 outputs an operation result according to the input first digital signal and second digital signal. The result of this operation represents the phase difference of the two clock signals input. After the loop filter 320 filters the operation result, the digitally controlled oscillator 330 is controlled to output a third digital signal corresponding to the clock signal based on the polarity and the absolute value of the operation result. And then obtains a reference clock signal corresponding to the third digital signal based on the digital-to-analog converter 400.

However, in the manner of using the digital phase locked loop 300 to improve the accuracy of the clock signal, the digital-to-analog converter 400 has problems such as quantization noise, nonlinearity, settling time limitation, and clock distortion.

For settling time limitation, it is possible that the digital-to-analog converter 400 has a finite settling time, i.e., the time required for the output voltage to reach its steady state value after a digital input code change. Settling time can affect the stability and lock time of the digital phase locked loop 300. This settling time limitation problem is referred to as the load carrying capacity of digital to analog converter 400.

As shown in fig. 3, the digital-to-analog converter 400 includes an analog voltage source circuit 410, a digital gating circuit 420; wherein the analog voltage source circuit 410 is configured to: a plurality of analog voltages having different voltage values are output to a plurality of power supply terminals of the digital gate circuit 420. The digital gating circuit 420 is configured to: the digital gating circuit 420 is controlled to output a reference clock signal according to a plurality of analog voltages according to the third digital signal. In an embodiment of the present invention, a plurality of analog voltages having different voltage values are received through the digital gating circuit 420. Digital gating circuit 420 includes a plurality of selection switches therein, each of which receives one or more analog voltages. And each of the selection switches corresponds to one bit of the inputted third digital signal. The corresponding selection switch is controlled to be turned on or off by each bit of the third digital signal to control the digital-to-analog converter 400 to output an analog voltage signal with a corresponding voltage magnitude, thereby realizing the conversion of the third digital signal into a reference clock signal in the form of an analog signal.

Illustratively, as shown in fig. 4, the digital-to-analog converter 400 is exemplified as a resistive digital-to-analog converter. The analog voltage source circuit 410 includes a reference voltage circuit 411, an enhancement voltage circuit 412, a first operational amplifier 413, a second operational amplifier 414, and a resistor string 415. The output of the reference voltage circuit 411 is coupled to a first operational amplifier 413 and a second operational amplifier 414, respectively. An output of the first operational amplifier 413 is coupled to a first end of the resistor string 415. An output of the second operational amplifier 414 is coupled to a second terminal of the resistor string 415. The boost voltage circuit 412 is coupled to a resistor string 415. Wherein, reference voltage circuit 411 is used for: the first reference analog voltage is output to the first operational amplifier 413, and the second reference analog voltage is output to the second operational amplifier 414. The boost voltage circuit 412 is configured to: the boost voltage is output to the middle segment of the resistor string 415. Resistor string 415 is used to: the plurality of resistor terminals of the resistor string 415 output a plurality of analog voltages according to the boost voltage, the first reference analog voltage, and the second reference analog voltage.

In the embodiment of the present invention, as shown in fig. 4, reference analog voltages of two benchmarks are output through a reference voltage circuit 411. And output to the first and second ends of the resistor string 415 through corresponding operational amplifiers, respectively. After the two reference analog voltages are divided by the resistor on the transmission path, a plurality of analog voltages with voltage values between the first reference analog voltage and the second reference analog voltage are obtained. A corresponding analog voltage may be output at the port of each resistor of the resistor string 415, and the value of the analog voltage gradually transits from the first reference analog voltage to the second reference analog voltage, thereby obtaining a plurality of analog voltages with different voltage values. The analog voltage is then output to the digital gating circuit 420, and a corresponding one or more analog voltage outputs are selected to form the reference clock signal according to the third digital signal that is actually input. In practical applications, however, processing the clock signal requires a relatively high operating speed of the digital-to-analog converter 400. In each digital-to-analog conversion process, the first reference analog voltage is input to the resistor string 415 through the first operational amplifier 413, and if the analog voltage needs to be output from the resistor port of the middle section of the resistor string 415, the first reference analog voltage and the second reference analog voltage need to be consumed by a certain resistor to reach the resistor port of the middle section. Then the voltage at the resistor port needs to be increased to the desired analog voltage value after a certain time. In the process of high-speed operation, the settling time is limited, and the resistor port may not reach a stable value within the specified settling time of the digital-to-analog conversion, and the port voltage is used as the analog voltage of an ideal value to perform digital-to-analog conversion, so that the accuracy of digital-to-analog conversion is reduced, and the accuracy of generating a timing control signal is affected. Accordingly, as shown in fig. 4, a corresponding boost voltage circuit 412 may be disposed in the digital-to-analog converter 400, and the boost voltage is output to the middle section of the resistor string 415 through the boost voltage circuit 412, so that the voltage at the resistor ports of one or more resistors in the middle section of the resistor string 415 may quickly reach the voltage value of the desired analog voltage.

Illustratively, as shown in FIG. 4, the first and second inputs of the boost voltage circuit 412 are coupled to the reference voltage circuit 411, respectively; the boost voltage circuit 412 is configured to: the boost voltage is output to the resistor string 415 according to the first reference analog voltage and the second reference analog voltage. In an embodiment of the present invention, the voltage value of the boost voltage generated by boost voltage circuit 412 from the first reference analog voltage and the second reference analog voltage is closer to the voltage required by resistor string 415.

Illustratively, as shown in fig. 5, the boost circuit 412 includes a boost amplifier 412A, a first resistor 412B, and a second resistor 412C. The output of the booster amplifier 412A is coupled to a first resistor port of the resistor string 415, which may be any resistor port in the middle of the resistor string 415. The boost amplifier 412A inputs a first reference analog voltage through the first resistor 412B, inputs a second reference analog voltage through the second resistor 412C, and then outputs a boost voltage to the first resistor port. Wherein, the ratio of the resistances of the first resistor 412B and the second resistor 412C is equal to the ratio of the resistances of the first resistor and the second resistor. The first resistance is a resistance between the first resistive port and the first end of the resistor string 415. The second resistance is the resistance between the first resistive port and the second end of the resistor string 415.

Illustratively, as shown in fig. 6, the digital-to-analog converter 400 may include a plurality of resistor strings 415. In the embodiment of the present invention, when a plurality of analog voltages are generated by one resistor string 415, the number of analog voltages required increases as the accuracy of the digital-to-analog converter 400 increases. With the increase of the number of resistors, the settling time limit will be greater, which will limit the application of the resistive digital-to-analog converter 400 in high-precision timing control scenarios. And a plurality of resistor strings 415 are employed, each resistor string 415 inputting a first reference analog voltage and a second reference analog voltage corresponding to the numbers. The number of analog voltages to be generated by a set of the first reference analog voltage and the second reference analog voltage can be reduced so that the voltage of the resistor port of each resistor can reach the voltage value of the ideal analog voltage more quickly. In addition to this, the resistance value of each resistor of the resistor string 415 may be set larger. In the case where the input first reference analog voltage and the second reference analog voltage are unchanged, the voltage value of the analog voltage output by the resistor string 415 is affected by the ratio between the plurality of resistors in the resistor string, regardless of the size of the resistors. However, when the resistance in the resistor string 415 is smaller, the voltage value can be reached faster and the voltage value is smaller, but when the resistance is smaller, the current generated on the resistor string 415 will be larger, which will greatly increase the power consumption of the digital-to-analog converter 400, and when the accuracy of the digital-to-analog converter 400 is higher, the number of resistors is larger, and the power consumption is also larger. However, after the boost voltage circuit 412 is provided, the resistance of the resistor string 415 is limited to a smaller value, and the resistance of the resistor string 415 may be doubled, or the like. At this time, in the application scenario of high precision, the power consumption of the digital-to-analog converter 400 is also lower. The operation of the timing controller 500 has a long time nature. The digital-to-analog converter 400 at this time is more suitable for applications under high precision timing control.

The digital-to-analog converter 400 is affected by a process or the like, and there is also clock leakage that is necessary for the digital-to-analog converter 400 and cannot be eliminated. In the case of high-precision timing control, the clock distortion of the digital-to-analog converter 400 also has a certain influence on the precision. For this purpose, as shown in fig. 7, the high-precision timing control apparatus 1000 further includes a detection controller 600; the detection controller 600 is coupled to an output of the digital-to-analog converter 400. Wherein, the detection controller 600 is used for: acquiring the amplitude and the phase of a leakage clock signal according to the reference clock signal, and obtaining a compensation clock signal; the compensation clock signal is equal in frequency and amplitude to the leakage clock signal of the digital-to-analog converter 400, and is opposite in phase to the leakage clock signal. The compensated clock signal is incorporated into the local clock signal and a first digital signal is derived based on the local clock signal in which the compensated clock signal is incorporated.

Illustratively, the high-precision timing control apparatus 1000 may further include a shaping circuit. The crystal oscillator 100 outputs the local clock signal to the shaping circuit, performs shaping processing by the shaping circuit, and outputs the local clock signal to the analog-to-digital converter 200.

Illustratively, as shown in fig. 8, the high-precision timing control apparatus 1000 further includes a power supply circuit 700. The power supply circuit 700 includes an amplitude detection circuit 710, a comparison circuit 720, and an adjustable power supply 730. An input of the amplitude detection circuit 710 is coupled to an output of the digital-to-analog converter 400. An output of the amplitude detection circuit 720 is coupled to a first input of the comparison circuit 720, and a second input of the comparison circuit 720 inputs a comparison reference voltage. An output of the comparison circuit 720 is coupled to a controlled terminal of an adjustable power supply 730. An output of the adjustable power supply 730 is coupled to a powered terminal of the digitally controlled oscillator 330. The amplitude detection and comparison circuit 710 is used for detecting the amplitude of the reference clock signal output by the digital-to-analog converter 400 and outputting an amplitude voltage according to the amplitude. The comparison circuit 720 is configured to output a control voltage according to the comparison result and the reference voltage and the amplitude voltage, where the control voltage is used to control the magnitude of the supply voltage output by the adjustable power supply 730 to the digitally controlled oscillator 330. In embodiments of the present invention, the supply of a conventional oscillator is typically implemented based on an LDO linear regulator. A fixed voltage is output to the oscillator via the LDO to power the oscillator. However, due to the influence of the production process and the production voltage of the oscillator, the starting gain, the starting oscillation time and the oscillation amplitude of the oscillator are greatly different, and a certain starting time is needed to stabilize the locked frequency required by the phase-locked loop. In the embodiment of the present invention, the amplitude detection circuit 710 detects the amplitude of the output reference clock signal, and the magnitude of the power supply voltage output to the numerically controlled oscillator 330 is feedback-adjusted according to the comparison result between the amplitude voltage and the comparison reference voltage, so that the output clock signal is stabilized at a fixed frequency after the oscillation starts, and the timing control is more accurate.

Based on the high-precision timing control apparatus 1000 described in fig. 1, 2, 3, 4, 5, 6, and 7, one high-precision timing control method as shown in fig. 9 can be performed:

step S1, converting a local clock signal into a first digital signal; the sampling clock signal is derived from the timing controller and converted to a second digital signal.

Illustratively, converting the local clock signal to the first digital signal and converting the sampling clock signal to the second digital signal may be implemented based on the analog-to-digital converter 200 described above.

And S2, obtaining a third digital signal according to the first digital signal and the second digital signal.

Illustratively, the first digital signal and the second digital signal may be subjected to digital phase discrimination based on the digital phase-locked loop 300, and the third digital signal may be generated according to the operation result of the digital phase discrimination.

And step S3, obtaining a reference clock signal according to the third digital signal.

The conversion of the third digital signal into the reference clock signal may be performed, for example, according to the digital-to-analog converter 400 described above.

And S4, outputting a sampling clock signal and a plurality of time sequence control signals according to the reference clock signal.

Illustratively, a frequency divider may be provided in the timing controller 500, by which the reference clock signal is divided to obtain the sampling clock signal. Meanwhile, the timing controller 500 may also generate a plurality of timing control signals based on the reference clock signal according to the precision to control different functional modules to perform corresponding functions at the same time or at different times.

In some possible embodiments, when the method shown in fig. 9 is performed for the first time, the present invention may also perform the method shown in fig. 10 synchronously:

step S1', the phase of the leakage clock signal is obtained according to the frequency of the leakage clock signal.

Illustratively, first, the detection controller 600 needs to determine the frequency of the leakage clock signal. Then, the phase of the leakage clock is determined based on the frequency of the leakage clock signal. Finally, under the condition that the phase and the frequency are determined, the amplitude of the leakage clock signal can be determined. The frequency of the leakage clock signal of the digital-to-analog converter 400 is related to the sampling rate of the digital-to-analog converter 400, and the frequency of the leakage clock signal can be obtained according to the sampling rate of the digital-to-analog converter 400. Alternatively, the frequency of the leakage clock signal of the digital-to-analog converter 400 is typically one-fourth of the sampling rate. A plurality of first test clock signals with the same frequency, the same amplitude and different phases are generated based on the frequency of the leakage clock signal, the plurality of first test clock signals are respectively integrated on the local clock signals, and then the power of a plurality of reference clock signals correspondingly output by the digital-to-analog converter 400 is detected. In the case of fixed frequency and amplitude, the closer the phase of the first test clock signal is to the first test clock signal, the greater the power output by the digital-to-analog converter 400. The detection controller 600 detects the power of the plurality of first test clock signals, and uses the phase corresponding to the first test clock signal with the largest power as the phase of the leakage clock signal.

Step S2', the amplitude of the leakage clock signal is obtained according to the frequency and the phase of the leakage clock signal.

Illustratively, the local clock signal and the sampling clock signal are stopped from being provided to the analog-to-digital converter 200, and the first output power of the digital-to-analog converter 400 is detected at this time. The first output power at this time can be approximately regarded as the output power of the leakage clock signal (but is generally not equal to the ideal output power of the leakage clock signal due to system circuit arrangement and the like). By generating a plurality of second test clock signals, the frequency and phase of the plurality of second test clock signals are equal to the frequency and phase of the leakage clock signal. The magnitudes of the plurality of second test clock signals are different. In case the phase and frequency of the second test clock signal are equal to the leakage clock signal. The plurality of second test clock signals are respectively provided to the analog-to-digital converter 200, and then the second output power of the digital-to-analog converter 400 at this time is detected. When the second output power is equal to twice of the first output power, the amplitude of the second test clock signal corresponding to the second output power at the moment can be confirmed to be the amplitude of the leakage clock signal.

And step S3', obtaining a compensation clock signal according to the frequency, the phase and the amplitude of the leakage clock signal, and combining the compensation clock signal into the local clock signal.

Illustratively, the compensated clock signal is equal in frequency and amplitude and opposite in phase to the leakage clock signal. Clock distortion caused by the leakage clock signal is compensated by compensating the clock signal.

Illustratively, the detection controller 600 may control the magnitude of the local clock signal output by the crystal oscillator 100 to enable the incorporation of the compensated clock signal onto the local clock signal. The detection controller 600 may also control the analog-to-digital converter 200 to superimpose a digital signal corresponding to the compensated clock signal on the first digital signal when outputting the first digital signal of the local clock signal, so as to superimpose the compensated clock signal on the local clock signal.

The processor referred to in the embodiments of the present invention may be a chip. For example, it may be a field programmable gate array (field programmable gate array, FPGA), an application specific integrated chip (application specific integrated circuit, ASIC), a system on chip (SoC), a central processing unit (central processor unit, CPU), a network processor (network processor, NP), a digital signal processing circuit (digital signal processor, DSP), a microcontroller (micro controller unit, MCU), a programmable controller (programmable logic device, PLD) or other integrated chip.

The memory to which embodiments of the present invention relate may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The nonvolatile memory may be a read-only memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an electrically Erasable EPROM (EEPROM), or a flash memory. The volatile memory may be random access memory (random access memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and direct memory bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

It should be understood that, in various embodiments of the present invention, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic thereof, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Those of ordinary skill in the art will appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system, apparatus and module may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple modules or components may be combined or integrated into another device, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, indirect coupling or communication connection of devices or modules, electrical, mechanical, or other form.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physically separate, i.e., may be located in one device, or may be distributed over multiple devices. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in the embodiments of the present invention may be integrated in one device, or each module may exist alone physically, or two or more modules may be integrated in one device.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present invention are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more servers, data centers, etc. that can be integrated with the medium. The usable medium may be a magnetic medium (e.g., a floppy Disk, a hard Disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (6)

1. The high-precision time sequence control device is characterized by comprising a crystal oscillator, an analog-to-digital converter, a digital phase-locked loop, a digital-to-analog converter and a timing controller which are sequentially coupled; the timing controller is further coupled to the analog-to-digital converter; the digital-to-analog converter comprises an analog voltage source circuit and a digital gating circuit; the analog voltage source circuit comprises a reference voltage circuit, an enhancement voltage circuit, a first operational amplifier, a second operational amplifier and a resistor string; the output end of the reference voltage circuit is respectively coupled with the first operational amplifier and the second operational amplifier; an output of the first operational amplifier is coupled to a first end of the resistor string; an output of the second operational amplifier is coupled to a second end of the resistor string; the boost voltage circuit is coupled with the resistor string; wherein,,

The crystal oscillator is used for: generating a local clock signal;

the analog-to-digital converter is used for: converting the local clock signal into a first digital signal; inputting a sampling clock signal from the timing controller and converting the sampling clock signal into a second digital signal;

the digital phase-locked loop is used for: obtaining a third digital signal according to the first digital signal and the second digital signal;

the digital-to-analog converter is used for: obtaining a reference clock signal according to the third digital signal; the method comprises the following steps: the analog voltage source circuit is used for: outputting a plurality of analog voltages with different voltage values to a plurality of power supply terminals of the digital gating circuit; the reference voltage circuit is used for: outputting a first reference analog voltage to the first operational amplifier and outputting a second reference analog voltage to the second operational amplifier; the boost voltage circuit is configured to: outputting an enhanced voltage to a middle section of the resistor string; the resistor string is used for: a plurality of resistor ends of the resistor string output a plurality of analog voltages according to the enhanced voltage, the first reference analog voltage and the second reference analog voltage; the digital gating circuit is used for: controlling the digital gating circuit to output the reference clock signal according to the plurality of analog voltages according to the third digital signal;

The timing controller is used for: and obtaining the sampling clock signal and a plurality of time sequence control signals according to the reference clock signal.

2. The high precision timing control apparatus of claim 1, wherein the first input and the second input of the boost voltage circuit are coupled to the reference voltage circuit, respectively; the boost voltage circuit is configured to: outputting the boost voltage to the resistor string according to the first reference analog voltage and the second reference analog voltage.

3. A high precision timing control apparatus according to claim 1 or 2, characterized in that said apparatus further comprises a detection controller; the detection controller is coupled with the output end of the digital-to-analog converter; wherein,,

the detection controller is used for:

generating a plurality of first test clock signals with the same frequency, the same amplitude and different phases based on the frequency of the leakage clock signal of the digital-to-analog converter, respectively combining the plurality of first test clock signals onto the local clock signal, and then detecting the power of a plurality of reference clock signals correspondingly output by the digital-to-analog converter;

taking the phase corresponding to the first test clock signal with the maximum power as the phase of the leakage clock signal;

Stopping providing the local clock signal and the sampling clock signal to the analog-to-digital converter, and detecting a first output power of the digital-to-analog converter at the moment; generating a plurality of second test clock signals, the frequencies and phases of which are equal to the frequencies and phases of the leakage clock signals; the magnitudes of the plurality of second test clock signals are different; when the second output power is equal to twice of the first output power, the amplitude of the second test clock signal corresponding to the second output power at the moment can be confirmed to be the amplitude of the leakage clock signal;

obtaining a compensation clock signal according to the frequency, the phase and the amplitude of the leakage clock signal; the frequency and amplitude of the compensating clock signal are equal to those of the leakage clock signal of the digital-to-analog converter, and the phase of the compensating clock signal is opposite to that of the leakage clock signal;

the compensated clock signal is incorporated into the local clock signal and the first digital signal is derived based on the local clock signal in which the compensated clock signal is incorporated.

4. A high-precision timing control method, characterized by being based on the high-precision timing control apparatus according to any one of claims 1 to 3; the apparatus includes a timing controller; the method comprises the following steps:

Converting the local clock signal into a first digital signal; obtaining a sampling clock signal from the timing controller and converting the sampling clock signal into a second digital signal;

obtaining a third digital signal according to the first digital signal and the second digital signal;

obtaining a reference clock signal according to the third digital signal; the method comprises the following steps: generating a plurality of analog voltages with different voltage values; outputting a first reference analog voltage to a first end of the resistor string and outputting a second reference analog voltage to a second end of the resistor string; outputting an enhanced voltage to a middle section of the resistor string; a plurality of resistor ends of the resistor string output a plurality of analog voltages according to the enhanced voltage, the first reference analog voltage and the second reference analog voltage; selecting the plurality of analog voltages according to the third digital signal to obtain the reference clock signal;

the timing controller outputs the sampling clock signal and a plurality of timing control signals according to the reference clock signal.

5. The high precision timing control method as set forth in claim 4, wherein said outputting an enhanced voltage to an intermediate terminal of said resistor string comprises:

The boost voltage is output to the middle section of the resistor string according to the first reference analog voltage and the second reference analog voltage.

6. The method for high precision timing control according to claim 4 or 5, further comprising,

generating a plurality of first test clock signals with the same frequency, the same amplitude and different phases based on the frequency of the leakage clock signal of the digital-to-analog converter, respectively combining the plurality of first test clock signals onto the local clock signal, and then detecting the power of a plurality of reference clock signals correspondingly output by the digital-to-analog converter;

taking the phase corresponding to the first test clock signal with the maximum power as the phase of the leakage clock signal;

stopping providing the local clock signal and the sampling clock signal to the analog-to-digital converter, and detecting a first output power of the digital-to-analog converter at the moment; generating a plurality of second test clock signals, the frequencies and phases of which are equal to the frequencies and phases of the leakage clock signals; the magnitudes of the plurality of second test clock signals are different; when the second output power is equal to twice of the first output power, the amplitude of the second test clock signal corresponding to the second output power at the moment can be confirmed to be the amplitude of the leakage clock signal;

Obtaining a compensation clock signal according to the frequency, the phase and the amplitude of the leakage clock signal; the frequency and amplitude of the compensating clock signal are equal to those of the leakage clock signal of the digital-to-analog converter, and the phase of the compensating clock signal is opposite to that of the leakage clock signal;

the compensated clock signal is incorporated into the local clock signal and the first digital signal is derived based on the local clock signal in which the compensated clock signal is incorporated.