CN117544136B - RC relaxation oscillator with adjustable precision - Google Patents
RC relaxation oscillator with adjustable precision Download PDFInfo
- Publication number
- CN117544136B CN117544136B CN202410033095.0A CN202410033095A CN117544136B CN 117544136 B CN117544136 B CN 117544136B CN 202410033095 A CN202410033095 A CN 202410033095A CN 117544136 B CN117544136 B CN 117544136B
- Authority
- CN
- China
- Prior art keywords
- pmos tube
- tube
- electrode
- nmos tube
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000003990 capacitor Substances 0.000 claims description 70
- 238000009966 trimming Methods 0.000 claims description 26
- 238000000034 method Methods 0.000 description 7
- 230000008569 process Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
Abstract
The invention provides an RC relaxation oscillator with adjustable precision, which relates to the technical field of RC oscillators and aims to realize a high-integration and high-precision RC relaxation oscillator, and comprises a reference current generating circuit, an RC charge-discharge branch circuit, a voltage-controlled oscillator, a non-overlapping clock generating module and a frequency division circuit; the constant current output end of the reference current generating circuit is respectively connected to the RC charge-discharge branch circuit, the starting signal output end of the reference current generating circuit is connected to the voltage-controlled oscillator, and the adjustable control voltage output end of the RC charge-discharge branch circuit is connected to the voltage-controlled oscillator; the clock frequency output end of the voltage-controlled oscillator is connected to the input end of the non-overlapping clock generating module through the frequency dividing circuit, and the first clock signal output end and the second clock signal output end of the non-overlapping clock generating module are respectively connected to the third input end and the fourth input end of the RC charge-discharge branch. The invention has the advantages of adjustable precision, high precision and small occupied volume of devices.
Description
Technical Field
The invention relates to the technical field of RC oscillators, in particular to an RC relaxation oscillator with adjustable precision.
Background
With the continuous development of the fields of communication, internet of things, sensors, biomedicine and the like, the requirements on the system on chip (SoC, system on Circuits) chip are higher and higher, so that the system on chip (SoC) and the chip are developed towards lower cost, lower power consumption and more stability. It is an urgent need to provide a high-precision clock module with stable and reliable performance for these electronic systems.
Currently, three oscillators are available for on-chip integrated clock sources: LC oscillator, ring oscillator and RC relaxation oscillator. Compared with the other two on-chip integratable oscillators, the RC relaxation oscillator has smaller temperature coefficient, and compared with the LC oscillator, the RC relaxation oscillator is easier to integrate and has lower cost due to the fact that no on-chip inductance exists. The output clock frequency accuracy of the existing RC oscillator is often low, and is easily influenced by power supply voltage, temperature variation, process deviation and the like.
Thus, realization of a highly integrated and high-precision RC relaxation oscillator is becoming a research hotspot in this field.
Disclosure of Invention
The invention aims to provide an RC relaxation oscillator with adjustable precision, which can realize high-integration and high-precision RC relaxation oscillator.
The embodiment of the invention is realized by the following technical scheme:
an RC relaxation oscillator with adjustable precision comprises a reference current generating circuit, an RC charge-discharge branch, a voltage-controlled oscillator, a non-overlapping clock generating module and a frequency division circuit;
the first output end and the second output end of the reference current generating circuit are respectively connected to the first input end and the second input end of the RC charge-discharge branch, the starting signal output end of the reference current generating circuit is connected to the first input end of the voltage-controlled oscillator, and the adjustable control voltage output end of the RC charge-discharge branch is connected to the second input end of the voltage-controlled oscillator;
the clock frequency output end of the voltage-controlled oscillator is connected to the input end of the non-overlapping clock generation module through the frequency division circuit, and the first clock signal output end and the second clock signal output end of the non-overlapping clock generation module are respectively connected to the third input end and the fourth input end of the RC charge-discharge branch.
Preferably, the reference current generating circuit comprises a first PMOS tube and a fourth resistor;
the source electrode of the first PMOS tube is connected with a first direct current source, and the grid electrode and the drain electrode of the first PMOS tube are both connected to the first end of the fourth resistor;
the source electrode of the first PMOS tube, the grid electrode of the first PMOS tube and the second end of the fourth resistor are respectively a first output end, a second output end and a starting signal output end of the reference current generating circuit.
Preferably, the RC charge-discharge branch circuit includes a plurality of NMOS transistors, a plurality of PMOS transistors, a fourth switch, a plurality of capacitors, a resistor trimming module, and a capacitor charge-discharge current trimming module;
the source electrode of the second PMOS tube is connected with the first output end of the reference current generating circuit and the source electrode of the third PMOS tube; the grid electrode of the second PMOS tube is connected with the second output end of the reference current generating circuit and the grid electrode of the third PMOS tube;
the drain electrode of the second PMOS tube is connected with the drain electrode and the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the first end of the zeroth resistor and the first end of the first capacitor, and the second end of the zeroth resistor and the second end of the first capacitor are respectively connected with the resistor trimming module;
the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube, and the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube;
the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube, the drain electrode node of the second NMOS tube and the third PMOS tube, the grid electrode of the third PMOS tube and the source electrode of the third PMOS tube are respectively connected to a plurality of input ends of the capacitor charge and discharge current size adjustment module;
the first output end of the capacitor charge-discharge current magnitude trimming module is a trimmable voltage output end of the RC charge-discharge branch, the second output end of the capacitor charge-discharge current magnitude trimming module is connected with the first end of the second capacitor and the first end of the third switch, and the second end of the third switch is connected with the first end of the zeroth capacitor and the first end of the fourth switch; the second end of the first capacitor, the second end of the second capacitor, the second end of the zeroth capacitor and the second end of the fourth switch are connected with a second direct current source; the first clock signal output end and the second clock signal output end of the non-overlapping clock generation module are respectively connected with a third switch and a fourth switch.
Preferably, the resistance trimming module comprises a plurality of resistance switch parallel circuits which are sequentially connected in series; the resistor-switch parallel circuit comprises a resistor and a switch which are connected in parallel;
the first end of the resistance switch parallel circuit is connected with the second end of the zeroth resistor, and the second end of the resistance switch parallel circuit is connected with the second end of the first capacitor.
Preferably, the number of the resistance switch parallel circuits is 3.
Preferably, the capacitor charge and discharge current magnitude adjustment module comprises a plurality of PMOS tubes and a plurality of NMOS tubes;
the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are all connected with the source electrode of the third PMOS tube; the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are all connected with the grid electrode of the third PMOS tube;
the source electrode and the drain electrode of the fourth PMOS tube, the source electrode and the drain electrode of the fifth PMOS tube and the source electrode and the drain electrode of the sixth PMOS tube are respectively connected with the source electrode of the seventh PMOS tube, the source electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube;
the drain electrode of the seventh PMOS tube, the drain electrode of the eighth PMOS tube and the drain electrode of the ninth PMOS tube, the drain electrode of the sixth NMOS tube, the drain electrode of the seventh NMOS tube and the drain electrode of the eighth NMOS tube are all connected with the drain electrode of the second NMOS tube and the drain electrode of the third PMOS tube, and a common node between the drain electrode of the second NMOS tube and the drain electrode of the third PMOS tube is a first output end of the capacitor charge-discharge current size adjustment module; the method comprises the steps of carrying out a first treatment on the surface of the
The source electrode of the sixth NMOS tube, the source electrode of the seventh NMOS tube and the source electrode of the eighth NMOS tube are respectively connected with the drain electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube and the drain electrode of the fifth NMOS tube;
the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube are all connected to the grid electrode of the second NMOS tube; the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are connected to the source electrode of the second NMOS tube, and the source electrode of the second NMOS tube is the second output end of the capacitor charge and discharge current size adjustment module.
Preferably, the adjustable control voltage output end of the RC charge-discharge branch is further connected to a third dc source through a filter capacitor.
The technical scheme of the embodiment of the invention has at least the following advantages and beneficial effects:
the RC relaxation oscillator is relatively simple in structure, reduces the increase of the chip area, is low in power consumption, and can be suitable for low-power consumption RC relaxation oscillator circuits;
according to the RC relaxation oscillator, the resistor and the capacitor are added for charge and discharge gear adjustment, so that the influence of temperature change, power supply voltage and process deviation on the frequency of the RC relaxation oscillator is effectively reduced, the adaptability of the RC relaxation oscillator is higher, and the application range is wider;
according to the adjustable setting, the precision of the RC relaxation oscillator is greatly improved, so that the stability and the reliability of the RC relaxation oscillator in the working process are further enhanced;
the invention has reasonable design and simple structure, is easy to manufacture and put into use, has high cost performance, and is convenient to implement and popularize.
Drawings
FIG. 1 is a schematic diagram of an RC relaxation oscillator with adjustable seed accuracy according to embodiment 1 of the present invention;
icon: r0-zero resistor, R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, C0-zero capacitor, C1-first capacitor, C2-second capacitor, cf-filter capacitor, PM 1-first PMOS tube, PM 2-second PMOS tube, PM 3-third PMOS tube, PM 4-fourth PMOS tube, PM 5-fifth PMOS tube, PM 6-sixth PMOS tube, PM 7-seventh PMOS tube, PM 8-eighth PMOS tube, PM 9-ninth PMOS tube, NM 1-first NMOS tube, NM 2-second NMOS tube, NM 3-third NMOS tube, NM 4-fourth NMOS tube, NM 5-fifth NMOS tube, NM 6-sixth NMOS tube, NM 7-seventh NMOS tube, NM 8-eighth NMOS tube.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Example 1
The embodiment provides an RC relaxation oscillator with adjustable precision, referring to FIG. 1, which comprises a reference current generating circuit, an RC charge-discharge branch, a voltage-controlled oscillator, a non-overlapping clock generating module and a frequency division circuit;
the first output end and the second output end of the reference current generating circuit are respectively connected to the first input end and the second input end of the RC charge-discharge branch, the starting signal output end of the reference current generating circuit is connected to the first input end of the voltage-controlled oscillator, and the adjustable control voltage output end of the RC charge-discharge branch is connected to the second input end of the voltage-controlled oscillator;
the clock frequency output end of the voltage-controlled oscillator is connected to the input end of the non-overlapping clock generation module through the frequency division circuit, and the first clock signal output end and the second clock signal output end of the non-overlapping clock generation module are respectively connected to the third input end and the fourth input end of the RC charge-discharge branch.
In this embodiment, the basic working principle is as follows:
firstly, a reference current generating circuit generates current to be input into an RC charge-discharge branch circuit to realize stable bias, and generates a starting signal Set to input a voltage-controlled oscillator to finish starting of the voltage-controlled oscillator and discharge initialization of each capacitor of the voltage-controlled oscillator;
then, the RC charge-discharge branch circuit can generate a tunable control voltage to the voltage-controlled oscillator, and the voltage-controlled oscillator can generate a tunable clock frequency FCLK;
finally, two phase non-overlapping clock signals phi+ and phi-are generated through a non-overlapping clock generation module and a frequency division circuit.
Example 2
This embodiment is based on the preferred embodiment of embodiment 1, and a reference current generating circuit will be mainly described with reference to fig. 1.
In this embodiment, the reference current generating circuit includes a first PMOS tube PM1 and a fourth resistor R4;
the source electrode of the first PMOS tube PM1 is connected with a first direct current source, and the grid electrode and the drain electrode are both connected to the first end of the fourth resistor R4;
the source electrode of the first PMOS tube PM1, the gate electrode of the first PMOS tube PM1, and the second end of the fourth resistor R4 are respectively the first output end, the second output end, and the start signal output end of the reference current generating circuit.
In the embodiment, the fourth resistor R4 with a lower temperature coefficient is used for generating the subthreshold reference current IBAIS and the bias voltage VB, on one hand, constant currents IR and IC are generated to realize stable bias, and on the other hand, a starting signal Set is generated to finish the starting of the voltage-controlled oscillator and the discharge initialization of each capacitor in the circuit.
Example 3
The preferred embodiment of this embodiment is based on embodiment 1, and referring to fig. 1, the RC charge-discharge branch is mainly described further.
In this embodiment, the RC charge-discharge branch includes a plurality of NMOS transistors, a plurality of PMOS transistors, a fourth switch, a plurality of capacitors, a resistor trimming module, and a capacitor charge-discharge current trimming module;
the source electrode of the second PMOS tube PM2 is connected with the first output end of the reference current generation circuit and the source electrode of the third PMOS tube PM 3; the grid electrode of the second PMOS tube PM2 is connected with the second output end of the reference current generating circuit and the grid electrode of the third PMOS tube PM 3;
the drain electrode of the second PMOS tube PM2 is connected with the drain electrode and the grid electrode of the first NMOS tube NM1, the source electrode of the first NMOS tube NM1 is connected with the first end of a zeroth resistor R0 and the first end of a first capacitor C1, and the second end of the zeroth resistor R0 and the second end of the first capacitor C1 are respectively connected with the resistor trimming module;
the drain electrode of the third PMOS tube PM3 is connected with the drain electrode of the second NMOS tube NM2, and the grid electrode of the second NMOS tube NM2 is connected with the grid electrode of the first NMOS tube NM 1;
the grid electrode of the second NMOS tube NM2, the source electrode of the second NMOS tube NM2, the drain electrode node of the second NMOS tube NM2 and the third PMOS tube PM3, the grid electrode of the third PMOS tube PM3 and the source electrode of the third PMOS tube PM3 are respectively connected to a plurality of input ends of the capacitor charge and discharge current magnitude adjustment module;
the first output end of the capacitor charge-discharge current magnitude trimming module is a trimmable control voltage output end of the RC charge-discharge branch, the second output end of the capacitor charge-discharge current magnitude trimming module is connected with the first end of the second capacitor C2 and the first end of the third switch, and the second end of the third switch is connected with the first end of the zeroth capacitor C0 and the first end of the fourth switch; the second end of the first capacitor C1, the second end of the second capacitor C2, the second end of the zeroth capacitor C0 and the second end of the fourth switch are connected with a second direct current source; the first clock signal output end and the second clock signal output end of the non-overlapping clock generation module are respectively connected with a third switch and a fourth switch.
On the other hand, the resistance trimming module comprises a plurality of resistance switch parallel circuits which are sequentially connected in series; the resistor-switch parallel circuit comprises a resistor and a switch which are connected in parallel;
the first end of the resistance switch parallel circuit is connected with the second end of the zeroth resistor R0, and the second end of the resistance switch parallel circuit is connected with the second end of the first capacitor C1.
Preferably, the number of the resistance switch parallel circuits is 3. That is, the first resistor R1, the second resistor R2, and the third resistor R3 are sequentially connected in series to form a resistor series circuit, and the zeroth switch, the first switch, and the second switch are sequentially connected in series to form a switch series circuit;
the first end of the resistor serial circuit and the first end of the switch serial circuit are connected with the second end of the zeroth resistor R0, and the second end of the resistor serial circuit and the second end of the switch serial circuit are connected with the second end of the first capacitor C1;
the node between the zeroth switch and the first switch is connected with the node between the first resistor R1 and the second resistor R2, and the node between the first switch and the second switch is connected with the node between the second resistor R2 and the third resistor R3.
In addition, the capacitor charge-discharge current magnitude trimming module can comprise a plurality of PMOS tubes and a plurality of NMOS tubes;
the source electrode of the fourth PMOS tube PM4, the source electrode of the fifth PMOS tube PM5 and the source electrode of the sixth PMOS tube PM6 are all connected with the source electrode of the third PMOS tube PM 3; the grid electrode of the fourth PMOS tube PM4, the grid electrode of the fifth PMOS tube PM5 and the grid electrode of the sixth PMOS tube PM6 are all connected with the grid electrode of the third PMOS tube PM 3;
the source electrode and the drain electrode of the fourth PMOS tube PM4, the source electrode and the drain electrode of the fifth PMOS tube PM5 and the source electrode and the drain electrode of the sixth PMOS tube PM6 are respectively connected with the source electrode of the seventh PMOS tube PM7, the source electrode of the eighth PMOS tube PM8 and the source electrode of the ninth PMOS tube PM 9;
the drain electrode of the seventh PMOS tube PM7, the drain electrode of the eighth PMOS tube PM8, the drain electrode of the ninth PMOS tube PM9, the drain electrode of the sixth NMOS tube NM6, the drain electrode of the seventh NMOS tube NM7 and the drain electrode of the eighth NMOS tube NM8 are all connected with the drain electrode of the second NMOS tube NM2 and the drain electrode of the third PMOS tube PM3, and a common node between the drain electrode of the second NMOS tube NM2 and the drain electrode of the third PMOS tube PM3 is the first output end of the capacitor charge-discharge current size adjustment module; the method comprises the steps of carrying out a first treatment on the surface of the
The source electrode of the sixth NMOS tube NM6, the source electrode of the seventh NMOS tube NM7 and the source electrode of the eighth NMOS tube NM8 are respectively connected with the drain electrode of the third NMOS tube NM3, the drain electrode of the fourth NMOS tube NM4 and the drain electrode of the fifth NMOS tube NM 5;
the grid electrode of the third NMOS tube NM3, the grid electrode of the fourth NMOS tube NM4 and the grid electrode of the fifth NMOS tube NM5 are all connected to the grid electrode of the second NMOS tube NM 2; the source electrode of the third NMOS tube NM3, the source electrode of the fourth NMOS tube NM4 and the source electrode of the fifth NMOS tube NM5 are all connected to the source electrode of the second NMOS tube NM2, and the source electrode of the second NMOS tube NM2 is the second output end of the capacitor charge-discharge current size adjustment module.
Specifically, itrim0-Itrim2 is a digital trimming code for controlling the sixth NMOS transistor NM6 to the eighth NMOS transistor NM8 to be connected to the corresponding gate, itrim0_n-itrim2_n is a trimming code for controlling the seventh PMOS transistor PM7 to the ninth PMOS transistor PM9, and is connected to the corresponding gate, and the above-mentioned codes are used to control the on-off states of the corresponding PMOS transistors or NMOS transistors, thereby controlling the current on-off states of the branches where they are located. Wherein itrim0_n-itrim2_n is the high-low inverted signal of Itrim0-Itrim2, respectively.
Further, the adjustable control voltage output end of the RC charge-discharge branch is also connected to a third direct current source through a filter capacitor Cf.
In this embodiment, the RC charge-discharge branch is used to complete the charge-discharge process of the capacitor, so as to generate a periodic clock signal. The second to sixth PMOS transistors PM2 to PM6 and the first PMOS transistor PM1 form a current mirror, and the second to fifth NMOS transistors NM2 to NM5 and the first NMOS transistor NM1 form a current mirror, generating a constant current IR and IC. The left Bian Zhilu constant current IR flowing from the drain of the second PMOS tube PM2 generates a reference voltage Vin+ on the resistor.
On the other hand, the right branch is replaced by a switched capacitor structure formed by a third switch, a fourth switch, a zeroth capacitor C0 and a second capacitor C2, and the capacitor is charged and discharged by the IC to generate a sawtooth wave signal Vin+. The third switch and the fourth switch are switching tubes of a switch capacitor, and clutter and burrs on Vin-are filtered by the first capacitor C1.
Meanwhile, the first NMOS tube NM1 and the second NMOS tube NM2 are used as current mode comparators for comparing Vin-with vin+ and amplifying errors, wherein Vin-is a reference voltage generated by constant current IR on resistors R0-R3, vin+ is a voltage generated by charging and discharging IC, so that control voltage VCTRL can be generated, a voltage-controlled oscillator is further controlled to generate corresponding clock signals, and a filter capacitor Cf can realize low-pass filtering to ensure the stability of a system.
In addition, the seventh PMOS tube PM7 to the ninth PMOS tube PM9, the sixth NMOS tube NM6 to the eighth NMOS tube NM8 are used for trimming the charge and discharge current of the zeroth capacitor C0 and the second capacitor C2, so as to trim the voltages at two ends of the capacitors, further trim the control voltage VCTRL, and finally achieve the effect of trimming the output clock frequency.
Similarly, the zeroth switch, the first switch and the second switch can also be used for trimming the resistance value of the loop formed by the first resistor R1 to the third resistor R3, so that the voltage at two ends of the resistor is trimmed, the control voltage VCTRL is further trimmed, and the effect of trimming the output clock frequency is achieved.
In the embodiment, by adjusting the resistor and the charge-discharge current trimming gear simultaneously, the output clock frequency of the oscillator can reach less than 0.5% under various PVT (process, voltage, temperature) combinations, and the precision is as low as about 28 ppm/DEG C under the temperature drift of-55-125 ℃.
The above is only a preferred embodiment of the present invention, and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (4)
1. The RC relaxation oscillator with adjustable precision is characterized by comprising a reference current generation circuit, an RC charge-discharge branch, a voltage-controlled oscillator, a non-overlapping clock generation module and a frequency division circuit;
the first output end and the second output end of the reference current generating circuit are respectively connected to the first input end and the second input end of the RC charge-discharge branch, the starting signal output end of the reference current generating circuit is connected to the first input end of the voltage-controlled oscillator, and the adjustable control voltage output end of the RC charge-discharge branch is connected to the second input end of the voltage-controlled oscillator;
the clock frequency output end of the voltage-controlled oscillator is connected to the input end of the non-overlapping clock generation module through the frequency division circuit, and the first clock signal output end and the second clock signal output end of the non-overlapping clock generation module are respectively connected to the third input end and the fourth input end of the RC charge-discharge branch;
the RC charge-discharge branch circuit comprises a plurality of NMOS tubes, a plurality of PMOS tubes, a fourth switch, a plurality of capacitors, a resistor trimming module and a capacitor charge-discharge current magnitude trimming module;
the source electrode of the second PMOS tube is connected with the first output end of the reference current generating circuit and the source electrode of the third PMOS tube; the grid electrode of the second PMOS tube is connected with the second output end of the reference current generating circuit and the grid electrode of the third PMOS tube;
the drain electrode of the second PMOS tube is connected with the drain electrode and the grid electrode of the first NMOS tube, the source electrode of the first NMOS tube is connected with the first end of the zeroth resistor and the first end of the first capacitor, and the second end of the zeroth resistor and the second end of the first capacitor are respectively connected with the resistor trimming module;
the drain electrode of the third PMOS tube is connected with the drain electrode of the second NMOS tube, and the grid electrode of the second NMOS tube is connected with the grid electrode of the first NMOS tube;
the grid electrode of the second NMOS tube, the source electrode of the second NMOS tube, the drain electrode node of the second NMOS tube and the third PMOS tube, the grid electrode of the third PMOS tube and the source electrode of the third PMOS tube are respectively connected to a plurality of input ends of the capacitor charge and discharge current size adjustment module;
the first output end of the capacitor charge-discharge current magnitude trimming module is a trimmable voltage output end of the RC charge-discharge branch, the second output end of the capacitor charge-discharge current magnitude trimming module is connected with the first end of the second capacitor and the first end of the third switch, and the second end of the third switch is connected with the first end of the zeroth capacitor and the first end of the fourth switch; the second end of the first capacitor, the second end of the second capacitor, the second end of the zeroth capacitor and the second end of the fourth switch are connected with a second direct current source; the first clock signal output end and the second clock signal output end of the non-overlapping clock generation module are respectively connected with a third switch and a fourth switch;
the resistance trimming module comprises a plurality of resistance switch parallel circuits which are sequentially connected in series; the resistor-switch parallel circuit comprises a resistor and a switch which are connected in parallel;
the first end of the resistance switch parallel circuit is connected with the second end of the zeroth resistor, and the second end of the resistance switch parallel circuit is connected with the second end of the first capacitor;
the capacitor charge and discharge current magnitude adjustment module comprises a plurality of PMOS tubes and a plurality of NMOS tubes;
the source electrode of the fourth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are all connected with the source electrode of the third PMOS tube; the grid electrode of the fourth PMOS tube, the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are all connected with the grid electrode of the third PMOS tube;
the source electrode and the drain electrode of the fourth PMOS tube, the source electrode and the drain electrode of the fifth PMOS tube and the source electrode and the drain electrode of the sixth PMOS tube are respectively connected with the source electrode of the seventh PMOS tube, the source electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube;
the drain electrode of the seventh PMOS tube, the drain electrode of the eighth PMOS tube and the drain electrode of the ninth PMOS tube, the drain electrode of the sixth NMOS tube, the drain electrode of the seventh NMOS tube and the drain electrode of the eighth NMOS tube are all connected with the drain electrode of the second NMOS tube and the drain electrode of the third PMOS tube, and a common node between the drain electrode of the second NMOS tube and the drain electrode of the third PMOS tube is a first output end of the capacitor charge-discharge current size adjustment module;
the source electrode of the sixth NMOS tube, the source electrode of the seventh NMOS tube and the source electrode of the eighth NMOS tube are respectively connected with the drain electrode of the third NMOS tube, the drain electrode of the fourth NMOS tube and the drain electrode of the fifth NMOS tube;
the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube and the grid electrode of the fifth NMOS tube are all connected to the grid electrode of the second NMOS tube; the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are connected to the source electrode of the second NMOS tube, and the source electrode of the second NMOS tube is the second output end of the capacitor charge and discharge current size adjustment module.
2. The precision-adjustable RC relaxation oscillator of claim 1, wherein the reference current generation circuit comprises a first PMOS tube and a fourth resistor;
the source electrode of the first PMOS tube is connected with a first direct current source, and the grid electrode and the drain electrode of the first PMOS tube are both connected to the first end of the fourth resistor;
the source electrode of the first PMOS tube, the grid electrode of the first PMOS tube and the second end of the fourth resistor are respectively a first output end, a second output end and a starting signal output end of the reference current generating circuit.
3. An adjustable precision RC relaxation oscillator according to claim 1, wherein the number of said resistive switching parallel circuits is 3.
4. The precision adjustable RC relaxation oscillator of claim 1, wherein said RC charge-discharge branch adjustable control voltage output is further connected to a third dc source through a filter capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410033095.0A CN117544136B (en) | 2024-01-10 | 2024-01-10 | RC relaxation oscillator with adjustable precision |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410033095.0A CN117544136B (en) | 2024-01-10 | 2024-01-10 | RC relaxation oscillator with adjustable precision |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117544136A CN117544136A (en) | 2024-02-09 |
| CN117544136B true CN117544136B (en) | 2024-04-09 |
Family
ID=89786600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410033095.0A Active CN117544136B (en) | 2024-01-10 | 2024-01-10 | RC relaxation oscillator with adjustable precision |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117544136B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158203A (en) * | 2011-04-26 | 2011-08-17 | 杭州芯赛微电子有限公司 | High-accuracy resistance-capacitance (RC) oscillator |
| CN104579254A (en) * | 2014-12-03 | 2015-04-29 | 北京兆易创新科技股份有限公司 | Relaxation oscillator |
| CN109787558A (en) * | 2018-12-28 | 2019-05-21 | 合肥中感微电子有限公司 | Pierce circuit and its method for repairing and regulating |
| CN111697947A (en) * | 2020-06-17 | 2020-09-22 | 长沙锐逸微电子有限公司 | High-precision wide-range relaxation oscillator insensitive to temperature |
| CN111726106A (en) * | 2020-06-19 | 2020-09-29 | 东南大学 | Dual-feedback loop relaxation oscillator |
| CN115425925A (en) * | 2022-08-22 | 2022-12-02 | 上海川土微电子有限公司 | High-precision RC oscillator circuit |
| CN115603709A (en) * | 2022-11-21 | 2023-01-13 | 成都本原聚能科技有限公司（Cn） | Oscillation starting circuit, integrated circuit and chip |
| CN117220648A (en) * | 2023-08-07 | 2023-12-12 | 上海灿瑞微电子有限公司 | RC relaxation oscillator |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105958943B (en) * | 2016-04-21 | 2018-12-04 | 新茂国际科技股份有限公司 | relaxation oscillator |
| US10461724B2 (en) * | 2016-11-22 | 2019-10-29 | Analog Devices Global | Relaxation oscillator with overshoot error integration |
-
2024
- 2024-01-10 CN CN202410033095.0A patent/CN117544136B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102158203A (en) * | 2011-04-26 | 2011-08-17 | 杭州芯赛微电子有限公司 | High-accuracy resistance-capacitance (RC) oscillator |
| CN104579254A (en) * | 2014-12-03 | 2015-04-29 | 北京兆易创新科技股份有限公司 | Relaxation oscillator |
| CN109787558A (en) * | 2018-12-28 | 2019-05-21 | 合肥中感微电子有限公司 | Pierce circuit and its method for repairing and regulating |
| CN111697947A (en) * | 2020-06-17 | 2020-09-22 | 长沙锐逸微电子有限公司 | High-precision wide-range relaxation oscillator insensitive to temperature |
| CN111726106A (en) * | 2020-06-19 | 2020-09-29 | 东南大学 | Dual-feedback loop relaxation oscillator |
| CN115425925A (en) * | 2022-08-22 | 2022-12-02 | 上海川土微电子有限公司 | High-precision RC oscillator circuit |
| CN115603709A (en) * | 2022-11-21 | 2023-01-13 | 成都本原聚能科技有限公司（Cn） | Oscillation starting circuit, integrated circuit and chip |
| CN117220648A (en) * | 2023-08-07 | 2023-12-12 | 上海灿瑞微电子有限公司 | RC relaxation oscillator |
Non-Patent Citations (3)
| Title |
|---|
| Low-power Relaxation Oscillator with Temperature-compensated Thyristor Decision Elements;Marcel Jotschke等;《Analog Integrated Circuits and Signal Processing》;20230903;第116卷;131-144 * |
| 基于CMOS工艺的RC张弛振荡器的研究与设计;陈东侨;《中国优秀硕士学位论文全文数据库信息科技辑》;20230115;I135-1171 * |
| 自校准频率锁定的高稳定性RC振荡器设计;肖如吉;《中国优秀硕士学位论文全文数据库信息科技辑》;20220615;I135-246 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117544136A (en) | 2024-02-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106059538B (en) | A kind of relaxor of included process deviation calibration function | |
| CN107040210B (en) | RC oscillator and DC-DC power chip | |
| CN104124921A (en) | Current mode comparator based low voltage low power consumption CMOS (Complementary Metal Oxide Semiconductors) relaxation oscillator and method | |
| US9190985B2 (en) | Electronic device with switched-capacitor tuning and related method | |
| CN107317568B (en) | Oscillator for eliminating offset voltage of comparator | |
| CN117544136B (en) | RC relaxation oscillator with adjustable precision | |
| JP4390105B2 (en) | Variable capacitance circuit with on / off switch of variable capacitance function, and voltage controlled oscillator using this variable capacitance circuit | |
| CN112953526A (en) | Ring oscillation circuit, method and integrated chip | |
| CN110011644B (en) | Ring oscillator | |
| CN109787558B (en) | Oscillator circuit and trimming method thereof | |
| CN107317580B (en) | High-stability oscillator circuit and implementation method thereof | |
| Lahiri | New canonic active RC sinusoidal oscillator circuits using second-generation current conveyors with application as a wide-frequency digitally controlled sinusoid generator | |
| CN111181491B (en) | Clock generating circuit | |
| CN114185388A (en) | Temperature characteristic adjustable current module, oscillator and circuit | |
| JPH04133113A (en) | Constant-current circuit and oscillation circuit | |
| CN211405972U (en) | CMOS-based temperature compensation FBAR crystal oscillator circuit | |
| CN210431350U (en) | Novel temperature compensation oscillator | |
| CN109245723B (en) | On-chip RC oscillator circuit | |
| CN111224620A (en) | CMOS-based temperature compensation FBAR crystal oscillator circuit and working method | |
| CN110794914A (en) | Band-gap reference voltage generating circuit | |
| CN111106829A (en) | High-precision ring oscillation circuit and micro control system | |
| CN112667013B (en) | Current comparison type clock generation circuit and chip | |
| CN219204467U (en) | Oscillator and battery management system | |
| CN117081546A (en) | Ring oscillation pulse circuit and clock reference circuit | |
| CN217307642U (en) | Wide-voltage-range low-temperature-drift RC oscillating circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |