CN210431350U

CN210431350U - Novel temperature compensation oscillator

Info

Publication number: CN210431350U
Application number: CN201921751852.9U
Authority: CN
Inventors: 黄明程; 刘立明; 杨升启; 陆卫星; 文兴
Original assignee: Shanghai Syncmos Semiconductor Co ltd
Current assignee: Shanghai Syncmos Semiconductor Co ltd
Priority date: 2019-10-17
Filing date: 2019-10-17
Publication date: 2020-04-28
Anticipated expiration: 2029-10-17

Abstract

The utility model discloses a novel temperature compensated oscillator, a serial communication port, include: an oscillation circuit; a reference source coupled to the oscillating circuit; the input end of the low-dropout voltage stabilizing circuit is coupled with the reference source, and the output end of the low-dropout voltage stabilizing circuit is coupled with the oscillating circuit; the reference source comprises a self-bias current source circuit and a folding circuit, wherein the self-bias current source circuit at least comprises a pair of combined resistors with positive and negative temperature coefficients. The utility model discloses just can arrive the constant current who does not rely on voltage and temperature, the clock that produces so as to electric capacity charge-discharge with this electric current is exactly a stable equal duty ratio square wave very little along with voltage and temperature variation.

Description

Novel temperature compensation oscillator

Technical Field

The utility model relates to an oscillator, especially a novel temperature compensation oscillator.

Background

The oscillator is a square wave circuit which generates continuous and stable equal duty ratio and is mainly used for providing basic clock for a system chip.

The types of oscillators are many, including a crystal oscillator with an electronic crystal oscillator element added outside a chip, and an RC oscillator integrated inside the chip.

Usually, the external crystal oscillator can provide a stable clock signal, and is slightly influenced by voltage and temperature. The disadvantage is that an additional crystal oscillator is required, which results in the increase of system cost and the redundancy of circuit.

And the internal integrated RC oscillator of chip can save external component, but because the internal RC oscillator of the characteristic of semiconductor is difficult to make voltage and temperature characteristic, especially temperature characteristic. The oscillation frequency generally varies with voltage and temperature.

Fig. 1 shows a conventional RC oscillator circuit.

The output frequency of the circuit is obtained by the matching ratio of the resistor R379 and the capacitor C45, and the essence is that the output frequency is obtained by the charging and discharging speed of the capacitor C through the current of the resistor R, so that it is easy to see that when the power supply voltage changes, the current for charging the capacitor C through the resistor R changes, and the charging and discharging speed of the capacitor C changes, so that the final output frequency changes.

When the temperature changes, the resistance value of the resistor R and the capacitance value of the capacitor C change along with the change difference of the temperature because the devices such as the capacitor C, the resistor R and the like have a temperature coefficient, so that when the temperature changes, the resistance value of the resistor R and the capacitance value of the capacitor C change, the charging and discharging speed of the capacitor C changes, and finally the output clock frequency fluctuates along with the change of the temperature coefficient.

When the fluctuating clock frequency is applied to a circuit, the requirement of the circuit for the constant basic clock cannot be met at all.

SUMMERY OF THE UTILITY MODEL

It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed.

To above-mentioned problem, the utility model provides a novel temperature compensated oscillator still carries out the charge-discharge through electric capacity, nevertheless guarantees the time stability of charge-discharge, does not receive the influence of power and temperature, has improved performance greatly.

The utility model discloses a novel temperature compensated oscillator, a serial communication port, include:

an oscillation circuit;

a reference source coupled to the oscillating circuit;

the input end of the low-dropout voltage stabilizing circuit is coupled with the reference source, and the output end of the low-dropout voltage stabilizing circuit is coupled with the oscillating circuit;

the reference source comprises a self-bias current source circuit and a folding circuit, wherein the self-bias current source circuit at least comprises a pair of combined resistors with positive and negative temperature coefficients.

Preferably, the utility model further discloses a novel temperature compensation oscillator, which is characterized in that,

the combined resistor comprises a polycrystalline resistor and a well resistor which are connected in series.

the resistance ratio of the polycrystalline resistor to the trap resistor is 3: 1.

the self-bias current source circuit comprises a first PMOS tube PM1, a second PMOS tube PM2, a seventh PMOS tube PM7, a ninth PMOS tube PM9, a fourth NMOS tube NM4, a fifth NMOS tube NM5, a thirteenth NMOS tube NM13, and the combined resistor formed by a first resistor R0 and a second resistor R1, wherein the gates of the first POS tube PM1 and the second PMOS tube PM2 are interconnected, the sources of the first PMOS tube PM1 and the second PMOS tube PM2 are both connected with a voltage source VDD, the drain of the first PMOS tube PM1 is connected with the drain of the fourth NMOS tube NM4, the drain of the second PMOS tube PM2 is connected with the drain of the fifth NMOS tube NM5, the gates of the fourth NMOS tube NM4 and NM5 are interconnected, the source of the fifth NMOS tube 5 is sequentially connected with a first resistor NM 0, a second NMOS resistor NM 69556, a second end NM R53 is connected with the fourth NMOS tube NM 82 4, and the source of the fourth NMOS tube NM 8427 is connected with ground;

the self-bias current source circuit further comprises a seventh PMOS tube PM7, a ninth PMOS tube PM9 and a thirteenth NMOS tube NM13, wherein the sources of the seventh PMOS tube PM7 and the ninth PMOS tube PM9 are connected with the voltage source VDD, the gates of the seventh PMOS tube PM7 and the ninth PMOS tube PM9 are connected with each other and with the drains of the first PMOS tube PM1 and the second PMOS tube PM2, the drain of the seventh PMOS tube PM7 is connected with the drain of the thirteenth NMOS tube NM13, the source of the thirteenth NMOS tube NM13 is grounded GND, the drain of the seventh PMOS tube PM7 outputs a reference voltage vbs, and the drain of the ninth PMOS tube PM9 outputs a reference current Ibs.

the folding circuit further comprises third and fourth PMOS tubes PM3 and PM4 corresponding to the first and second PMOS tubes PM1 and PM2, and first and second NMOS tubes NM1 and NM2 corresponding to the fourth and fifth NMOS tubes NM4 and NM 5;

the source of the third PMOS transistor PM3 is connected to the drain of the second PMOS transistor PM2, the drain of the third PMOS transistor PM3 is connected to the drain of the first NMOS transistor NM1, the source of the fourth POS transistor PM4 is connected to the drain of the first PMOS transistor PM1, the drain of the fourth PMOS transistor PM4 is connected to the drain of the second NMOS transistor NM2, the gates of the third and fourth PMOS transistors PM3 and PM4 are interconnected, the gates of the first, second NMOS transistors NM1 and NM2 are interconnected, the source of the first NMOS transistor NM1 is connected to the drain of the fifth NMOS transistor NM5, and the source of the second NMOS transistor NM2 is connected to the drain of the fourth NMOS transistor NM 4.

the folding circuit further comprises a sixth PMOS transistor PM6, a third NMOS transistor NM3 and an NM10 for providing gate voltages for the third PMOS transistor PM3 and the fourth PMOS transistor PM 4;

the source of the sixth PMOS transistor PM6 is connected to the voltage source VDD, the gate thereof is connected to the drain of the third NMOS transistor NM3, the source of the third NMOS transistor NM3 is connected to the drain of the tenth NMOS transistor NM10, and the source of the tenth NOS transistor NM10 is grounded to GND.

the folding circuit further includes eighth and tenth PMOS transistors PM8 and PM10 and eleventh and twelfth NMOS transistors NM11 and NM12 for supplying gate voltages to the first and second NOS transistors NM1 and NM 2;

the source of the eighth PMOS transistor PM8 is connected to the voltage source VDD, the gate thereof is connected to the drain of the third PMOS transistor PM3, the drain of the eighth PMOS transistor PM8 is connected to the source of the tenth PMOS transistor PM10, the drain of the tenth PMOS transistor PM10 is connected to the drain of the twelfth NMOS transistor NM12, the source of the twelfth NMOS transistor NM12 is connected to the drain of the eleventh NMOS transistor NM11, the gates thereof are connected in common to the gates of the first and second NMOS transistors NM1 and NM2, and the source of the eleventh NMOS transistor NM11 is grounded GND.

the folding circuit further comprises eleventh and twelfth PMOS tubes PM11 and P12, wherein the source of the eleventh PMOS tube PM11 is connected with the drain of the seventh PMOS tube PM7, the drain of the eleventh PMOS tube PM11 is connected with the drain of the thirteenth NMOS tube NM13, the source of the twelfth PMOS tube PM12 is connected with the drain of the ninth PMOS tube PM9, the drain of the twelfth PMOS tube PM12 outputs the reference current Ibs, and the gates of the eleventh and twelfth PMOS tubes PM11 and PM12 are interconnected.

The utility model discloses a compensation oscillator can not rely on the constant current of voltage and temperature, is a stable duty cycle square wave very little along with voltage and temperature variation as the clock to electric capacity charge-discharge production with this electric current.

Drawings

Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. Reference will now be made in detail to the preferred embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Further, although the terms used in the present disclosure are selected from publicly known and used terms, some of the terms mentioned in the specification of the present disclosure may be selected by the applicant at his or her discretion, the detailed meanings of which are described in relevant parts of the description herein. Furthermore, it is required that the present disclosure is understood, not simply by the actual terms used but by the meaning of each term lying within.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed description of the present invention, which is to be read in connection with the accompanying drawings.

FIG. 1 is a circuit diagram of a conventional RC oscillator;

fig. 2 is a block diagram of the oscillator of the present invention;

FIG. 3 is a basic self-biasing current source circuit applied in FIG. 2;

fig. 4 is a detailed circuit diagram of the reference source 11 configured based on the basic self-bias current source circuit in fig. 3.

Reference numerals

11-reference source

12-LDO circuit

13-oscillating circuit

Detailed Description

This specification discloses one or more embodiments that incorporate the features of this invention. The disclosed embodiments are merely illustrative of the invention. The scope of the invention is not limited to the disclosed embodiments. The invention is defined by the appended claims.

References in the specification to "one embodiment," "an example embodiment," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but all embodiments do not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Moreover, it should be understood that the spatial descriptions used herein (e.g., above, below, above, left, right, below, top, bottom, vertical, horizontal, etc.) are for purposes of illustration only, and that an actual implementation of the structures described herein may be spatially arranged in any orientation or manner.

Fig. 2 is a block diagram of the novel temperature compensated oscillator according to the present invention.

The oscillator includes a reference source 11, a low dropout regulation circuit (shown as LDO circuit) 12, and an oscillation circuit 13.

The LDO circuit 12 is used to provide a stable output voltage to the power supply of the subsequent oscillator circuit 13, so as to ensure the stability of the power supply voltage of the oscillator circuit 13, and the output voltage of the LDO circuit 12 is not affected by the system power supply and the temperature. An output terminal of the reference source 11 is connected to an input terminal of the LDO circuit 12, and provides a reference voltage of the LDO circuit 12, and a second output terminal of the reference source 11 is connected to the oscillation circuit 13, and also provides a current source bias of the post-oscillation circuit 13, and provides a cross current bias, which is not affected by the power supply and the temperature.

The operation of the novel oscillator is described below with reference to fig. 2.

The first constant current source I0 and the second constant current source I1 in the oscillating circuit 13 provide constant currents with equal magnitude, when the first MOS transistor N0 is turned off, the second MOS transistor N1 is turned on, and the first constant current source I0 provides constant linear charging for the first capacitor C0.

When the voltage of the first capacitor C0 reaches a fixed threshold, the first MOS transistor N0 is turned on, the second MOS transistor N1 is turned off, the second constant current source I1 provides constant current linear charging for the second capacitor C1, when the voltage of the second capacitor C1 reaches a specific threshold, the second MOS transistor N1 is turned on, the voltage of the second capacitor C1 is released, the first MOS transistor N0 is turned off, the first constant current source I0 starts to charge the first capacitor C0, and the operations are repeated, so that the output terminal CLK obtains a clock square wave with a consistent duty ratio.

Therefore, the circuit is provided with a constant current source which is not influenced by temperature and voltage, and the capacitor is charged and discharged to finally obtain stable clock output which is not influenced by the power supply and temperature change.

Fig. 4 shows a specific circuit composition of the reference source 11 in a preferred embodiment.

The reference source 11 generates a reference voltage Vbs supplied to the LDO circuit 12, and also supplies a capacitor charge/discharge constant current bias Ibs in the post-stage oscillation circuit 13.

The reference source 11 adopts a folding structure to ensure the stability of the voltage and the temperature of the current bias, so that the dependence of the bias current on the voltage is effectively inhibited, and meanwhile, the circuit is formed by combining two different types of resistors R0 and R1, so that the temperature compensation technology is realized.

Specifically, referring to fig. 4, the reference source 11 is a self-biased current source circuit, and a folding circuit is added to the self-biased current source circuit to form a folding self-biased circuit, which is described in detail below with reference to fig. 3.

The self-bias current source circuit is composed of four PMOS tubes PM1, PM2, PM7 and PM9, three NMOS tubes NM4, NM5 and NM13, and two series resistors R0 and R1. Furthermore, gates of the POS transistors PM1 and PM2 are interconnected, sources of the PM1 and PM2 are both connected to the same voltage source VDD, a drain of the PM1 is connected to a drain of the NMOS transistor NM4, a drain of the PM2 is connected to a drain of the NMOS transistor NM5, gates of the two NOMS transistors NM4 and NM5 are interconnected, a source of the NM5 is sequentially connected in series to the first resistor R0 and the second resistor R1, and a second end of the second resistor R1 is connected to a source of the NMOS transistor NM4 and is simultaneously grounded GND.

The self-bias current source circuit further comprises PM7, PM9 and NM13, wherein sources of PM7 and PM9 are connected with the same voltage source VDD, gates of the PM7 and the PM9 are connected with each other and are connected with drains of PM1 and PM2, a drain of PM7 is connected with a drain of NM13, a source of NM13 is grounded GND, a drain of PM7 outputs a reference voltage vbs, and a drain of PM9 outputs a reference current Ibs.

The preferred embodiment shown in fig. 4 is formed by extending a folding circuit on the basis of the self-biased current source circuit. Specifically, in order to increase the resistance of PM1 and PM2 and increase the resistance of NM5 and NM4, PM3 and PM4 corresponding to PM1 and PM2 are added and NM1 and NM2 corresponding to the group of NM4 and NM5 are added in designing the folding circuit. Specifically, the source of PM3 is connected to the drain of PM2, the drain of PM3 is connected to the drain of NM1, the source of PM4 is connected to the drain of PM1, the drain of PM4 is connected to the drain of NM2, and the gates of PM3 and PM4 are interconnected. Similarly, NM1 and NM2 gates are interconnected, NM1 source is connected NM5 drain, NM2 source is connected NM4 drain.

In fig. 4, PM6, NM3, and NM10 provide gate voltages for PM3 and PM 4.

Specifically, PM6 provides gate voltages for PM3 and PM4, NM3 provides gate voltages for NM1 and NM2, and NM10 provides drain voltages for PM3 and PM4, and NM1 and NM 2.

The source of the PM6 is connected to the same voltage source VDD, the gate and the drain are connected and to the drain of NM3, the source of NM3 is connected to the drain of NM10, and the source of NM10 is grounded GND.

Also, the added folding circuit further includes PM8, PM10, NM11, and NM12, and supplies gate voltages to NM1 and NM 2.

Specifically, the source of PM8 is connected to the same voltage source VDD, the gate thereof is connected to the drain of PM3, the drain of PM8 is connected to the source of PM10, the drain of PM10 is connected to the drain of NM12, the source of NM12 is connected to the drain of NM11, the gates thereof are connected in common and to the gates of NM1 and NM2, and the source of NM11 is connected to GND.

In addition, the addition of PM11 and P12 aims to make vbs and Ibs output by PM7 and PM9 respectively smoother, the source of PM11 is connected to the drain of PM7, the drain of PM11 is connected to the drain of NM13, the source of PM12 is connected to the drain of PM9, and the drain of PM12 outputs reference current Ibs, the gates of PM11 and PM12 are interconnected.

Because the reference source 11 adopts a folding structure, the stability of the output reference current Ibs is improved.

And vbs output from the reference source 11 is a more constant reference voltage.

In addition, because the oscillation circuit 13 in the present invention provides the reference voltage VDD _ clk by the LDO circuit 12, the voltage stability of the output is better than conventional and is not affected by the external power source.

It should be further noted that, in the self-biased current source circuit based on the reference source 11, it is conventional to use a resistor to form the self-biased current source circuit, and the improvement of the present invention is to use the combination of the first and second resistors R0 and R1 with two different performances connected in series to realize the temperature compensation function.

The first resistor R0 is a polycrystalline resistor with a negative temperature coefficient, and the second resistor R1 is a trap resistor with a positive temperature coefficient. Since the MOS transistor has a negative temperature coefficient, if the resistance is an ideal resistance, i.e., the resistance value does not change with temperature, the current generated by the reference will have a positive temperature coefficient due to the temperature characteristics of the MOS transistor, i.e., the output current Ibs of the reference source 11 will increase with increasing temperature, so by adjusting the proportional weights of the first and second resistors R0 and R1, the temperature influence of the MOS transistor will be cancelled out as closely as possible by a reasonable combination of the first and second resistors R0 and R1, thereby realizing the output current Ibs insensitive to temperature variation.

If the first and second resistors R0 and R1 are common poly resistors and well resistors in the standard process, then the ideal ratio of these two resistors in this reference architecture circuit is approximately R0: r1 ═ 3: 1.

Therefore, the utility model discloses just can arrive the constant current that does not rely on voltage and temperature, the clock that produces is exactly a stable equal duty ratio square wave along with voltage and the temperature change very little as to electric capacity charge-discharge with this electric current then.

Through practical measurement, the utility model discloses an oscillator can realize that the output frequency 16M down voltage characteristic is within plus-minus 0.5% from 2v to 5.5v frequency change, and the temperature is within 1.5% from 0 to 85 degree frequency change ideal performance.

In summary, the local oscillator circuit is integrated inside the chip, and an internally integrated high performance oscillator designed by adopting a structure of suppressing voltage characteristics and applying a brand new temperature compensation method is used for a clock generation source module inside the system chip.

The previous description of the preferred embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles described herein may be applied to other embodiments without the use of the inventive faculty. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A novel temperature compensated oscillator, comprising:

an oscillation circuit;

a reference source coupled to the oscillating circuit;

2. The novel temperature compensated oscillator of claim 1,

3. The novel temperature compensated oscillator of claim 2,

4. The novel temperature compensated oscillator of claim 3,

5. The novel temperature compensated oscillator of claim 4,

the folding circuit further includes:

third and fourth PMOS transistors PM3 and PM4 corresponding to the first and second PMOS transistors PM1 and PM2, and first and second NMOS transistors NM1 and NM2 corresponding to the fourth and fifth NMOS transistors NM4 and NM 5;

6. The novel temperature compensated oscillator of claim 5, wherein the folding circuit further comprises:

a sixth PMOS transistor PM6, a third NMOS transistor NM3, and a tenth NMOS transistor NM10 for supplying gate voltages to the third and fourth PMOS transistors PM3 and PM 4;

7. The novel temperature compensated oscillator of claim 6, wherein the folded circuit further comprises

Eighth and tenth PMOS transistors PM8 and PM10 and eleventh and twelfth NMOS transistors NM11 and NM12 for supplying gate voltages to the first and second NOS transistors NM1 and NM 2;

8. The novel temperature compensated oscillator of claim 7, wherein the folding circuit further comprises:

eleventh and twelfth PMOS tubes PM11 and P12, wherein the source of the eleventh PMOS tube PM11 is connected to the drain of the seventh PMOS tube PM7, the drain of the eleventh PMOS tube PM11 is connected to the drain of the thirteenth NMOS tube NM13, the source of the twelfth PMOS tube PM12 is connected to the drain of the ninth PMOS tube PM9, the drain of the twelfth PMOS tube PM12 outputs the reference current Ibs, and the gates of the eleventh and twelfth PMOS tubes PM11 and PM12 are interconnected.