CN117542817A - Semiconductor packaging structure and manufacturing method thereof - Google Patents
Semiconductor packaging structure and manufacturing method thereof Download PDFInfo
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- CN117542817A CN117542817A CN202410015791.9A CN202410015791A CN117542817A CN 117542817 A CN117542817 A CN 117542817A CN 202410015791 A CN202410015791 A CN 202410015791A CN 117542817 A CN117542817 A CN 117542817A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 229910052751 metal Inorganic materials 0.000 claims abstract description 91
- 239000002184 metal Substances 0.000 claims abstract description 91
- 238000007747 plating Methods 0.000 claims abstract description 47
- 229910052737 gold Inorganic materials 0.000 claims abstract description 45
- 239000010931 gold Substances 0.000 claims abstract description 45
- 230000000295 complement effect Effects 0.000 claims abstract description 31
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 17
- 230000000153 supplemental effect Effects 0.000 claims abstract description 14
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 137
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 229910052759 nickel Inorganic materials 0.000 description 9
- 229910052763 palladium Inorganic materials 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 6
- 230000032798 delamination Effects 0.000 description 5
- 238000007598 dipping method Methods 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000003213 activating effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 238000002791 soaking Methods 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011247 coating layer Substances 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000006479 redox reaction Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000013008 thixotropic agent Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02333—Structure of the redistribution layers being a bump
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to the technical field of semiconductor packaging, and discloses a semiconductor packaging structure and a manufacturing method thereof. The disclosed semiconductor packaging structure comprises a packaging structure main body, a complementary metal interconnection layer and a nickel-palladium-gold plating layer; the packaging structure main body is provided with a second opening and a third opening which are communicated, the caliber of the second opening is larger than that of the third opening, the second insulating medium layer is arranged on one side of the first insulating medium layer, which is far away from the chip, and part of main body metal interconnection is filled in the second opening; the supplemental metal interconnect layer and the nickel palladium gold plating layer are interconnected and located within the third opening. The disclosed manufacturing method comprises the following steps: forming a primary metal layer in the third opening; microetching the primary metal layer to obtain a complementary metal interconnection layer; an operation of obtaining a nickel-palladium-gold plating layer is performed on the supplemental metal interconnect layer. The structure and the manufacturing method provided by the invention can effectively solve the problem that the second insulating medium layer and the metal interconnection layer are separated, and have better reliability.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and a manufacturing method thereof.
Background
With the development of chips to high integration, the chip package size is smaller and smaller, and the chip bonding plays an important role in realizing high-efficiency and high-quality package. The current nickel-palladium-gold plating process is a main implementation mode applied to chip bonding in semiconductor packaging, and is characterized in that palladium is replaced on the surface of copper through chemical reaction to serve as a thixotropic agent for chemical nickel reaction, and then a layer of nickel is plated on the basis of palladium core; then generating a palladium layer on the nickel layer through oxidation-reduction reaction; finally, the layer is subjected to displacement reaction with nickel through the tiny gaps of the palladium layer, and a layer of gold is plated on the surface of the palladium layer, so that the IC chip is electrically connected with the outside.
The nickel-palladium plating and gold plating process mainly comprises the steps of degreasing, microetching, presoaking, activating, post-dipping, nickel plating, palladium plating and gold plating. The chemical reaction is adopted to carry out nickel plating palladium gold on the surface of copper, so that the micro-etching process is required to carry out slight etching on the surface of copper to remove oxide on the surface of copper, and the etching thickness is about 0.5 mu m for better plating effect and improving the bonding force of the plating. After the microetching process is performed, a part of copper below the insulating medium layer is etched to form an Undercut (Undercut), and when the subsequent process is performed, moisture, solvents and the like easily enter an Undercut region (such as a region A in fig. 1), so that the insulating medium layer is separated and layered, and the product performance is affected.
In view of this, the present application is specifically proposed.
Disclosure of Invention
The object of the present invention consists, for example, in providing a semiconductor package and a method for its manufacture, aimed at improving at least one of the problems mentioned in the background.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a semiconductor package structure, comprising a package structure body, a complementary metal interconnect layer, and a nickel-palladium-gold plating layer;
the packaging structure main body comprises a chip, a first insulating medium layer, a main body metal interconnection layer and a second insulating medium layer;
one surface of the chip is provided with a Pad opening, and a Pad is arranged in the Pad opening;
the first insulating medium layer is arranged on one surface of the chip, provided with the Pad opening, and is provided with a first opening, and the position of the first opening corresponds to the position of the Pad opening;
the main metal interconnection layer is provided with a first interconnection part and a second interconnection part which are connected, the second interconnection part is arranged on one side of the first insulating medium layer far away from the chip, and the first interconnection part passes through the first opening and is connected with the Pad;
the middle part of the second insulating medium layer is provided with a second opening and a third opening which are communicated, the caliber of the second opening is larger than that of the third opening, the second insulating medium layer is arranged on one side of the first insulating medium layer far away from the chip, and the second interconnection part is positioned in the second opening;
the complementary metal interconnection layer and the nickel-palladium-gold plating layer are connected with each other and located in the third opening, and the complementary metal interconnection layer is connected with the second interconnection part.
In an alternative embodiment, the thickness of the chip is 100-775 μm.
In an alternative embodiment, the aperture of the Pad opening is 32-100 μm.
In an alternative embodiment, the thickness of the first insulating dielectric layer is 3-15 μm.
In an alternative embodiment, at least one of the following features (1) - (7) is included:
(1) The thickness of the first interconnection part is the same as that of the first insulating medium layer, and the thickness of the second interconnection part is 3-10 mu m;
(2) The caliber of the first opening is 20-80 mu m, and the first interconnection part fills the first opening;
(3) The caliber of the second opening is 40-120 mu m, and the second interconnection part fills the second opening;
(4) The thickness of the second insulating medium layer is 5-20 mu m;
(5) The thickness of the complementary metal interconnection layer is 1-5 mu m;
(6) The thickness of the nickel-palladium-gold plating layer is 2-15 mu m;
(7) The supplemental metal interconnect layer and the nickel palladium gold plating layer fill the third opening.
In an alternative embodiment, the aperture of the first opening is smaller than the aperture of the Pad opening.
In an alternative embodiment, the caliber of the third opening is 30-100 μm, and the complementary metal interconnection layer and the nickel-palladium-gold plating layer fill up the third opening.
In an alternative embodiment, the bulk metal interconnect layer is made of copper, aluminum, silver, or gold; the material of the complementary metal interconnection layer is copper, aluminum, silver or gold;
alternatively, the material of the main metal interconnection layer and the complementary metal interconnection layer is copper.
In an optional embodiment, the first insulating medium layer is made of PI photoresist, silicon dioxide or silicon nitride; the second insulating medium layer is made of PI photoresist, silicon dioxide or silicon nitride.
In a second aspect, the present invention provides a method for manufacturing a semiconductor package according to any one of the preceding embodiments, comprising:
obtaining a packaging structure main body, and forming a primary metal layer in the third opening;
microetching the primary metal layer to obtain a complementary metal interconnection layer;
an operation of obtaining a nickel-palladium-gold plating layer is performed on the supplemental metal interconnect layer.
The beneficial effects of the embodiment of the invention include, for example:
according to the structure provided by the invention, in the manufacturing process, the primary metal layer is formed in the third opening, the primary metal layer bears the influence of the microetching process on the coating in the nickel-palladium-gold coating forming process to form the complementary metal interconnection layer, and because the complementary metal interconnection layer is positioned in the third opening and is different from the main metal interconnection layer positioned in the second opening, only the edge of the complementary metal interconnection layer is connected with the inner wall of the third opening, no undercut is formed, and the problem that the insulating medium layer falls off and delaminates after the subsequent operation of obtaining the nickel-palladium-gold coating is avoided.
Therefore, the semiconductor packaging structure provided by the embodiment of the invention has the advantages that the metal interconnection layer and the second insulating medium layer have good combination property, and the product has good reliability, good conductivity and strong machining property. The manufacturing method of the semiconductor packaging structure provided by the embodiment of the invention can not cause layering phenomenon of the metal interconnection layer and the second insulating medium layer when the nickel-palladium-gold plating layer is formed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a semiconductor package structure according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a package structure main body of a semiconductor package structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a semiconductor package structure with thickness of each layer and size of an opening according to an embodiment of the present invention.
Icon: 100-a semiconductor package structure; 101-packaging a structural body; 102-a supplemental metal interconnect layer; 103-nickel palladium gold plating; 110-chip; a 111-Pad opening; 112-Pad; 120-a first insulating dielectric layer; 121-a first opening; 130-a bulk metal interconnect layer; 131-a first interconnect; 132-a second interconnect; 140-a second insulating dielectric layer; 141-a second opening; 142-third opening.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
As shown in fig. 1 and 2, an embodiment of the present invention provides a semiconductor package 100, which includes a package body 101, a complementary metal interconnect layer 102, and a nickel-palladium-gold plating layer 103;
the package structure body 101 includes a chip 110, a first insulating dielectric layer 120, a body metal interconnect layer 130, and a second insulating dielectric layer 140;
one surface of the chip 110 is provided with a Pad opening 111, and a Pad112 is arranged in the Pad opening 111;
the first insulating dielectric layer 120 is disposed on the surface of the chip 110 where the Pad opening 111 is formed, the first insulating dielectric layer 120 has a first opening 121, and the position of the first opening 121 corresponds to the position of the Pad opening 111;
the main metal interconnection layer 130 has a first interconnection portion 131 and a second interconnection portion 132 connected, the second interconnection portion 132 is disposed on a side of the first insulating dielectric layer 120 away from the chip 110, and the first interconnection portion 131 is connected to the Pad112 through the first opening 121;
the middle part of the second insulating medium layer 140 is provided with a second opening 141 and a third opening 142 which are communicated, the caliber of the second opening 141 is larger than that of the third opening 142, the second insulating medium layer 140 is arranged on one side of the first insulating medium layer 120 far away from the chip 110, and the second interconnection part 132 is positioned in the second opening 141;
the supplemental metal interconnect layer 102 and the nickel-palladium-gold plating layer 103 are connected to each other and are located within the third opening 142, and the supplemental metal interconnect layer 102 is connected to the second interconnect 132.
The embodiment of the invention also provides a manufacturing method of the semiconductor packaging structure 100, which comprises the following steps:
obtaining a package structure body 101, and forming a primary metal layer in the third opening 142;
microetching the primary metal layer to obtain a complementary metal interconnection layer 102;
an operation of obtaining a nickel-palladium-gold plating layer 103 is performed on the supplemental metal interconnect layer 102.
In the manufacturing process, by forming the primary metal layer in the third opening 142, the primary metal layer bears the influence of the microetching process on the coating in the forming process of the nickel-palladium-gold plating layer 103 to form the complementary metal interconnection layer 102, and since the complementary metal interconnection layer 102 is positioned in the third opening 142 and is different from the main metal interconnection layer 130 positioned in the second opening 141, only the edge of the complementary metal interconnection layer 102 is connected with the inner wall of the third opening 142, no undercut is formed, and the problem of falling and layering of the insulating medium layer does not occur after the subsequent operation of obtaining the nickel-palladium-gold plating layer 103 is carried out.
Therefore, the metal interconnection layer and the second insulating dielectric layer 140 of the semiconductor package structure 100 provided by the embodiment of the invention have better combination property and good product performance. In the method for manufacturing the semiconductor package structure 100 according to the embodiment of the present invention, the formation of the nickel-palladium-gold plating layer 103 does not cause delamination between the metal interconnection layer and the second insulating dielectric layer 140.
Specifically, the operation of obtaining the nickel-palladium-gold plating layer 103 is, for example: sequentially performing pre-soaking, activating, post-soaking, nickel plating, palladium plating and gold plating.
As shown in fig. 1 to 3, in order to ensure excellent performance of the semiconductor package structure 100, the following arrangement may be made:
optionally, the thickness h of the chip 110 is 100-775 μm (e.g., 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, or 775 μm);
optionally, the aperture a of the Pad opening 111 is 32-100 μm (e.g., 32 μm, 50 μm, 80 μm, or 100 μm);
optionally, the thickness h of the first insulating dielectric layer 120 1 3 to 15 μm (e.g., 3 μm, 5 μm, 8 μm, 10 μm, or 15 μm);
optionally, the thickness of the first interconnection 131 is the same as the thickness of the first insulating dielectric layer 120, and the thickness h of the second interconnection 132 2 3 to 10 μm (e.g., 3 μm, 5 μm, 8 μm or 10 μm);
optionally, the caliber b of the first opening 121 is 20-80 μm (20 μm, 30 μm, 50 μm, 60 μm or 80 μm), and the first interconnection 131 fills the first opening 121;
optionally, the aperture c of the second opening 141 is 40-120 μm (e.g. 40 μm, 60 μm, 80 μm, 100 μm or 120 μm), and the second interconnect 132 fills the second opening 141;
optionally, the thickness h of the second insulating dielectric layer 140 3 3 to 20 μm (e.g., 3 μm, 5 μm, 8 μm, 10 μm, 15 μm, or 20 μm);
optionally, the thickness h of the supplemental metal interconnect layer 102 4 1 to 5 μm (e.g., 1 μm, 3 μm, or 5 μm);
optionally, the thickness h of the nickel-palladium-gold plating layer 103 5 2 to 15 μm (e.g., 2 μm, 5 μm, 8 μm, 10 μm or 15 μm);
optionally, the aperture of the first opening 121 is smaller than the aperture of the Pad opening 111.
Optionally, the material of the bulk metal interconnect layer 130 is copper, aluminum, silver, or gold; the material of the supplemental metal interconnect layer 102 is copper, aluminum, silver, or gold.
Specifically, the material of the bulk metal interconnect layer 130 and the supplemental metal interconnect layer 102 is copper.
Optionally, the material of the first insulating medium layer 120 is PI photoresist, silicon dioxide or silicon nitride; the second insulating dielectric layer 140 is made of PI photoresist, silicon dioxide or silicon nitride.
Examples
The present embodiment provides a manufacturing method of the semiconductor package structure 100, including:
obtaining a packaging structure main body 101, wherein in the packaging structure main body 101, the thickness h of a chip 110 is 400 mu m, the caliber a of a Pad opening 111 is 50 mu m, and the thickness h of a first insulating medium layer 120 1 Thickness h of second interconnect 132 is 5 μm 2 The diameter b of the first opening 121 is 50 μm, the diameter c of the second opening 141 is 80 μm, and the thickness h of the second insulating dielectric layer 140 is 5 μm 3 Thickness h of supplemental metal interconnect layer 102 is 14 μm 4 Thickness h of nickel-palladium-gold plating layer 103 of 4 μm 5 Is 5 μm.
Forming a primary metal layer (thickness 5 μm) in the third opening 142;
microetching the primary metal layer to obtain a complementary metal interconnect layer 102 (thickness 4 μm);
the operations of pre-dipping, activation, post-dipping, nickel plating, palladium plating, gold plating were sequentially performed on the supplemental metal interconnect layer 102 to obtain a nickel-palladium-gold plating layer 103 (thickness 5 μm).
Comparative example
This comparative example is substantially identical to the example, and differs only in that: the microetching process is performed directly on the surface of the second interconnect 132 without providing the primary metal layer.
Experimental example
500 semiconductor packages 100 were each fabricated according to the methods provided in examples and comparative examples, and whether or not delamination of the metal interconnect layer and the insulating dielectric layer occurred was detected, which indicates failure, and the failure rate was recorded in table 1.
Table 1 failure rate statistics for examples and comparative examples
As can be seen from table 1, the failure rate of the semiconductor package structure 100 manufactured by the manufacturing method provided by the embodiment of the invention is 0%, that is, the phenomenon of layering of the metal interconnection layer and the insulating medium layer does not occur in the manufacturing process; the reject ratio of the comparative example is as high as 70%, namely, the phenomenon that the metal interconnection layer and the insulating medium layer are layered is highly likely to occur in the manufacturing process.
It was found by observation that the region where the delamination phenomenon occurs in the comparative example is the transition region of the top wall of the second opening 141 and the side wall of the third opening 142, i.e., region a in fig. 1. It can be stated that the present invention can solve the above-described region layering phenomenon by disposing the complementary metal interconnection layer 102 above the body metal interconnection layer 130 in the third opening 142.
In summary, in the manufacturing process of the semiconductor package structure 100 provided by the present invention, the primary metal layer is formed in the third opening 142, and the primary metal layer bears the effect of the microetching process on the coating layer in the forming process of the nickel-palladium-gold plating layer 103 to form the complementary metal interconnection layer 102, and since the complementary metal interconnection layer 102 is located in the third opening 142, unlike the main metal interconnection layer 130 located in the second opening 141, the complementary metal interconnection layer 102 is only connected with the inner wall of the third opening 142 at the edge, and no undercut is formed, and the problem of delamination of the insulating medium layer after the subsequent operations of pre-dipping, activating, post-dipping, nickel plating, palladium plating and gold plating is avoided.
Therefore, the semiconductor package structure 100 provided by the embodiment of the invention has better combination of the metal interconnection layer and the second insulating medium layer 140, good product reliability, good conductivity and strong machining performance. The manufacturing method of the semiconductor package structure 100 provided in the embodiment of the invention does not cause delamination between the metal interconnection layer and the second insulating dielectric layer 140 when the nickel-palladium-gold plating layer 103 is formed.
The present invention is not limited to the above embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (10)
1. The semiconductor packaging structure is characterized by comprising a packaging structure main body, a complementary metal interconnection layer and a nickel-palladium-gold plating layer;
the packaging structure main body comprises a chip, a first insulating medium layer, a main body metal interconnection layer and a second insulating medium layer;
one surface of the chip is provided with a Pad opening, and a Pad is arranged in the Pad opening;
the first insulating medium layer is arranged on one surface of the chip, provided with the Pad opening, and is provided with a first opening, and the position of the first opening corresponds to the position of the Pad opening;
the main metal interconnection layer is provided with a first interconnection part and a second interconnection part which are connected, the second interconnection part is arranged on one side of the first insulating medium layer far away from the chip, and the first interconnection part is connected with the Pad through the first opening;
the middle part of the second insulating medium layer is provided with a second opening and a third opening which are communicated, the caliber of the second opening is larger than that of the third opening, the second insulating medium layer is arranged on one side, far away from the chip, of the first insulating medium layer, and the second interconnection part is positioned in the second opening;
the complementary metal interconnection layer and the nickel-palladium-gold plating layer are connected with each other and located in the third opening, and the complementary metal interconnection layer is connected with the second interconnection part.
2. The semiconductor package according to claim 1, wherein the thickness of the chip is 100-775 μm.
3. The semiconductor package according to claim 1, wherein the aperture of the Pad opening is 32-100 μm.
4. The semiconductor package according to claim 1, wherein the thickness of the first insulating dielectric layer is 3-15 μm.
5. The semiconductor package according to claim 1, comprising at least one of the following features (1) - (7):
(1) The thickness of the first interconnection part is the same as that of the first insulating medium layer, and the thickness of the second interconnection part is 3-10 mu m;
(2) The caliber of the first opening is 20-80 mu m, and the first interconnection part fills the first opening;
(3) The caliber of the second opening is 40-120 mu m, and the second interconnection part fills the second opening;
(4) The thickness of the second insulating medium layer is 5-20 mu m;
(5) The thickness of the complementary metal interconnection layer is 1-5 mu m;
(6) The thickness of the nickel-palladium-gold plating layer is 2-15 mu m;
(7) The supplemental metal interconnect layer and the nickel palladium gold plating fill the third opening.
6. The semiconductor package according to claim 1, wherein the aperture of the first opening is smaller than the aperture of the Pad opening.
7. The semiconductor package according to claim 1, wherein the aperture of the third opening is 30-100 μm, and the complementary metal interconnect layer and the nickel-palladium-gold plating layer fill the third opening.
8. The semiconductor package according to claim 1, wherein the bulk metal interconnect layer is made of copper, aluminum, silver or gold; the material of the complementary metal interconnection layer is copper, aluminum, silver or gold;
alternatively, the material of the main metal interconnection layer and the supplementary metal interconnection layer is copper.
9. The semiconductor package according to claim 1, wherein the first insulating dielectric layer is made of PI photoresist, silicon dioxide or silicon nitride; the second insulating medium layer is made of PI photoresist, silicon dioxide or silicon nitride.
10. The method for manufacturing a semiconductor package according to any one of claims 1 to 9, comprising:
obtaining the packaging structure main body, and forming a primary metal layer in the third opening;
microetching the primary metal layer to obtain the complementary metal interconnection layer;
and carrying out an operation of obtaining the nickel-palladium-gold plating layer on the complementary metal interconnection layer.
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| US20070031697A1 (en) * | 2005-08-04 | 2007-02-08 | Test Haward R | Copper-metallized integrated circuits having electroless thick copper bond pads |
| TW201110842A (en) * | 2009-09-15 | 2011-03-16 | Unimicron Technology Corp | Solder pad structure for printed circuit boards and fabrication method thereof |
| CN106558566A (en) * | 2015-09-30 | 2017-04-05 | 瑞萨电子株式会社 | The method of semiconductor device and manufacture semiconductor device |
| CN109216307A (en) * | 2017-06-29 | 2019-01-15 | 瑞萨电子株式会社 | Semiconductor devices and its manufacturing method |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070031697A1 (en) * | 2005-08-04 | 2007-02-08 | Test Haward R | Copper-metallized integrated circuits having electroless thick copper bond pads |
| TW201110842A (en) * | 2009-09-15 | 2011-03-16 | Unimicron Technology Corp | Solder pad structure for printed circuit boards and fabrication method thereof |
| CN106558566A (en) * | 2015-09-30 | 2017-04-05 | 瑞萨电子株式会社 | The method of semiconductor device and manufacture semiconductor device |
| CN109216307A (en) * | 2017-06-29 | 2019-01-15 | 瑞萨电子株式会社 | Semiconductor devices and its manufacturing method |
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